Detector circuit

Abstract

A device comprises a multiplication circuit configured to derive a product of a first signal S.sub.1 and a second signal S.sub.2, S.sub.2 having a phase difference relative to the first signal S.sub.1, a low pass filter configured to remove a selected frequency component from the product of S.sub.1 and S.sub.2 to derive a dot product S.sub.1S.sub.2; and a calculation circuit configured to receive the dot product S.sub.1S.sub.2 and generate a signal output having a ratio |S.sub.1|/|S.sub.2| and the phase difference .

Claims

1. A device, comprising: a sensing impedance Z.sub.sense; an impedance Z.sub.x connected in a series connection with the sensing impedance Z.sub.sense; a multiplication circuit configured to derive a signal representing a product of a first signal S.sub.1 received at a first signal input and a second signal S.sub.2 received at a second signal input, S.sub.2 having a phase difference relative to the first signal S.sub.1, wherein the first signal S.sub.1 is a voltage V.sub.10 across the series connection of the sensing impedance Z.sub.sense and the impedance Z.sub.x wherein the second signal S.sub.2 is a voltage V.sub.12 across the sensing impedance Z.sub.sense, and a third signal S.sub.3 received at a third signal input is a voltage Y.sub.20 across the impedance Z.sub.x, and wherein the third signal S.sub.3 has a phase difference relative to the first signal S.sub.1; a low pass filter configured to remove a selected frequency component from the signal representing the product of S.sub.1 and S.sub.2 to provide an output signal substantially proportional to a dot product S.sub.1 S.sub.2; and a calculation circuit configured to receive the output signal substantially proportional to the dot product S.sub.1 S.sub.2 and generate a signal output having a ratio |S.sub.1|/|S.sub.2| and the phase difference .

2. The device of claim 1, wherein the multiplication circuit and the low pass filter are configured to derive three dot-products S.sub.1 S.sub.2, S.sub.2 S.sub.3, and S.sub.1S.sub.3.

3. The device of claim 2, further comprising a feedback network configured to generate a ratio of two of the dot products S.sub.1 S.sub.2, S.sub.2 S.sub.3, and S.sub.1 S.sub.3.

4. The device of claim 1, further comprising three subtraction circuits configured to derive V.sub.10 and V.sub.12 from three input potentials P.sub.0, P.sub.1, P.sub.2.

5. The device of claim 1, wherein the multiplication circuit further comprises: two (2) double balanced mixers or Gilbert cells and a capacitance configured to generate a differential output voltage that represents a difference of the dot product S.sub.1 S.sub.2 and another dot product based on the third signal S.sub.3; a comparator configured to receive the differential output voltage and generate an up/down signal; and an up-down-counter responsive to the up/down signal and configured to control at least one of the two (2) double balanced mixers or Gilbert cells.

6. The device of claim 1, wherein the signal output is configured to provide: ratios |V.sub.10|/|V.sub.12|, |V.sub.12|/|V.sub.20|, |V.sub.20|/|V.sub.10|; a measure for the phase difference between V.sub.12 and V.sub.10; a measure for the phase difference between V.sub.20 and V.sub.10; and a measure for the phase difference between V.sub.20 and V.sub.12.

7. The device of claim 1, wherein the device is an impedance detector.

8. A device, comprising: a multiplication circuit configured to receive a first signal S.sub.1 and a second signal S.sub.2 having a phase difference relative to the first signal S.sub.1, the multiplication circuit comprising two double balanced mixers or Gilbert cells, a comparator, and an up-down-counter, the double balanced mixers or Gilbert cells and a capacitance configured to generate a differential output voltage representing a difference of a first dot product S.sub.1 S.sub.2 and another dot product based on a third signal S.sub.3 received by the multiplication circuit, the comparator configured to receive the differential output voltage and generate an up/down signal, the up-down-counter responsive to the up/down signal and configured to control at least one of the double balanced mixers or Gilbert cells; a low pass filter configured to remove a selected frequency component from a product of S.sub.1 and S.sub.2 to derive a signal representing the first dot product S.sub.1 S.sub.2; and a calculation circuit configured to receive the signal representing the first dot product S.sub.1 S.sub.2 and generate a signal output having a ratio |S.sub.1|/|S.sub.2| and the phase difference .

9. The device of claim 8, wherein: the first signal S.sub.1 is a voltage V.sub.10 across a serial connection of a sensing impedance Z.sub.sense and an impedance Z.sub.x; and the second signal S.sub.2 is a voltage V.sub.12 across the sensing impedance Z.sub.sense.

10. The device of claim 9, wherein: the multiplication circuit is configured to receive the third signal S.sub.3; the third signal S.sub.3 is a voltage V.sub.20 across the impedance Z.sub.x; and the third signal S.sub.3 has a phase difference relative to the first signal S.sub.1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as 102a or 102b, the letter character designations may differentiate two like parts or elements present in the same figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral encompass all parts having the same reference numeral in all figures.

(2) FIG. 1 schematically shows a detector circuit DC comprising a multiplication circuit MC and a calculation circuit CC.

(3) FIG. 2 shows an equivalent circuit diagram of a signal path comprising an unknown load impedance Zx and a sensing impedance Zsense.

(4) FIG. 3 shows fundamental correlations between the different input signals and their respective phase differences.

(5) FIG. 4A schematically shows a detector circuit comprising a multiplication circuit MC, a low pass filter LPF, a calculation circuit CC, and an analog/digital converter ADC.

(6) FIG. 4B shows an embodiment of a detector circuit where an analog/digital converter is connected between a low pass filter LPF and a calculation circuit CC.

(7) FIG. 4C shows an embodiment of a detector circuit with three signal inputs.

(8) FIG. 5 shows a detector circuit DC comprising three subtraction circuits, three multiplication circuits, three low pass filters, three analog/digital converters ADC and a calculation circuit CC.

(9) FIG. 6 shows an embodiment of a detector circuit similar to that of FIG. 5, further comprising amplifiers AMP.

(10) FIG. 7 shows an embodiment of the multiplication circuit comprising two Gilbert cells GC.

(11) FIG. 8 is a flowchart showing an exemplary embodiment of a method for operating a detector circuit.

DETAILED DESCRIPTION

(12) The word exemplary is used herein to mean serving as an example, instance, or illustration. Any aspect described herein as exemplary is not necessarily to be construed as preferred or advantageous over other aspects.

(13) In this description, the term application may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, an application referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.

(14) The term content may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, content referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.

(15) An exemplary embodiment of a detector circuit comprises a first signal input determined to receive a first signal S.sub.1, a second signal input determined to receive a second signal S.sub.2 having a phase difference relative to the first signal S.sub.1, and a multiplication circuit determined to derive the dot product S.sub.1S.sub.2. Further, the detector circuit comprises a signal output determined to provide the ratio |S.sub.1|/|S.sub.2|. The signals S.sub.1 and S.sub.2 can be visualized in the complex plane and, thus, be interpreted as vectors. Accordingly the dot product S.sub.1S.sub.2 is a well-defined quantity.

(16) An exemplary embodiment of a detector circuit may be used in an impedance measurement system for a signal path shown in FIG. 2. The signal path SP may be connected to an antenna having a variable load impedance. Such an antenna and its load impedance is represented by an impedance Z.sub.x. Further, the signal path SP comprises a sensing impedance Z.sub.sense which may be an inductive element IE. V.sub.20 denotes the voltage drop of the load impedance Z.sub.x. V.sub.12 denotes the voltage drop across the impedance Z.sub.sense. V.sub.10 is the sum of the voltages V.sub.20 and V.sub.12: V.sub.10=V.sub.20+V.sub.12. Thus, the impedance of the signal path SP equals the load impedance Z.sub.x plus the sensing impedance Z.sub.sense which may be a known impedance. From FIG. 2, it is clear that Z=Z.sub.sense V.sub.10/V.sub.12 where V.sub.10 and V.sub.12 are voltages representable as complex numbers.

(17) The situation shown in FIG. 2 can be described with parameters other than voltages V.sub.10, V.sub.12, and V.sub.20, i.e. exemplary embodiments of the detector circuit do not depend on details of parameters used as signal inputs for the detector circuit. Other parameters, e.g. current information, are also possible.

(18) Thus, deriving the unknown impedance Z can be accomplished by determining the ratio V.sub.10/V.sub.12. Here, V.sub.10 may be written as V.sub.10=|V.sub.10| exp (jt). Then, V.sub.12 may be written as V.sub.12=|V.sub.12|exp ((jt)+), i.e. V.sub.10 and V.sub.12 are signals of the same frequency with a phase difference of between V.sub.10 and V.sub.12. Accordingly, the ratio V.sub.10/V.sub.12 can be written as V.sub.10/V.sub.12=|V.sub.10|/|V.sub.12| exp (j). The correlations between V.sub.10, V.sub.12, and V.sub.20 are drawn in a complex plane view in FIG. 3.

(19) Accordingly, deriving the ratio V.sub.10/V.sub.12 can be accomplished by deriving the ratio of the absolute values |V.sub.10|/|V.sub.12| and by obtaining a measure for the phase difference . Previous circuits use two RSSI-chains to obtain the ratio of the absolute values. A further discrete phase detector is then used to obtain phase information.

(20) Exemplary embodiments of the detector circuit are based on the fact that the complex ratio V.sub.10/V.sub.12 intrinsically comprises the phase information. In an exemplary embodiment, the detector circuit provides direct access to phase information by processing three signals, e.g. V.sub.10, V.sub.20 and V.sub.12.

(21) In an exemplary embodiment, the detector circuit uses a geometric correlation between signal levels and phase information and electric circuitry that makes use of this correlation.

(22) Accordingly, an exemplary embodiment of the detector circuit comprises a multiplication circuit that derives the dot product V.sub.10V.sub.12 when V.sub.10 equals S.sub.1 and V.sub.12 equals S.sub.2.

(23) V.sub.10V.sub.12=|V.sub.10V.sub.12| cos . Thus, the dot product V.sub.10V.sub.12 is proportional to cos as a measure for the phase difference .

(24) In an exemplary embodiment, the detector circuit further comprises a third signal input configured to receive a third signal S.sub.3 having a phase difference relative to the first signal S.sub.1.

(25) Since S.sub.1S.sub.2=S.sub.3, two signals, selected from S.sub.1, S.sub.2 and S.sub.3 already contain enough information to determine the complex impedance Z. Processing the third signal enables technically advanced exemplary embodiments of the detector circuit with higher accuracy.

(26) In an exemplary embodiment, the multiplication circuit derives three dot products S.sub.1S.sub.2, S.sub.2S.sub.3, and S.sub.1S.sub.3.

(27) When the dot products S.sub.1S.sub.2, S.sub.2S.sub.3, and/or S.sub.1S.sub.3 are known then all ratios |S.sub.1|/|S.sub.2|, |S.sub.1|/|S.sub.3|, |S.sub.3|/|S.sub.2| and the respective inverse ratios can be obtained. Further, the values for cos , cos , and cos as measures for the phase differences between the signal inputs ( being the phase difference between S.sub.1 and S.sub.3; being the phase difference between S.sub.1 and S.sub.2, being the phase difference between S.sub.2 and S.sub.3) can be obtained.

(28) In an exemplary embodiment, one of the signals S.sub.1, S.sub.2, S.sub.3 is the sum of the respective other two signals.

(29) In an exemplary embodiment the multiplication circuit comprises a multiplier and a low pass filter.

(30) The multiplier circuit of the multiplication circuit may be fed with input signals of the form:
V.sub.1(t)=|V.sub.1|sin t(1)
V.sub.2(t)=|V.sub.2|sin(t+)(2)

(31) Multiplication yields:
V.sub.1(t)V.sub.2(t)=|V.sub.1V.sub.2|{cos cos(2t+)}(3)

(32) The low pass filter may absorb the component of the frequency 2 and provide a signal proportional to |V.sub.1V.sub.2| cos , which is exactly the dot product of V.sub.1V.sub.2.

(33) Thus, with V.sub.1, V.sub.2 being two values selected from S.sub.1, S.sub.2, S.sub.3, each of the dot products S.sub.1S.sub.2, S.sub.2S.sub.3, and S.sub.1S.sub.3 can be obtained.

(34) With:
k.sub.1=S.sub.1S.sub.2/S.sub.2S.sub.3
k.sub.2=S.sub.1S.sub.2/S.sub.1S.sub.3
k.sub.3=S.sub.2S.sub.3/S.sub.1S.sub.3

(35) The ratios of the rational numbers |S.sub.1|/|S.sub.2| can be obtained:
(|S.sub.1|/|S.sub.2|).sup.2=k.sub.1(k.sub.2+1)/(k.sub.2(k.sub.11))
and
|S.sub.1|/|S.sub.2|={square root over (k1(k2+1)/(k2(k11)))}

(36) Similarly |S.sub.1|/|S.sub.3| and |S.sub.2|/|S.sub.3| can be obtained.

(37) Further, by utilizing the cosine rule c.sup.2=a.sup.2+b.sup.22ab cos (with being the phase difference between a and b and a, b and c being understandable as the sides of a triangle) measures for the phase differences between the input signals can be obtained:
cos =(|S.sub.1|/|S.sub.2|+|S.sub.2|/|S.sub.1|(|S.sub.3|/|S.sub.1S.sub.3|/|S.sub.2|)).

(38) Similarly the respective other two phase differences can be obtained.

(39) Thus, obtaining all three input signals S.sub.1, S.sub.2, S.sub.3 is preferred. However, exemplary embodiments of the detector circuit can also work with two inputs for signals S.sub.1, S.sub.2 only. This is if the detector works in a mode where the three different signals are provided one after another. Then, a memory is used for storing processed values, but only one calculation circuit is needed.

(40) In an exemplary embodiment, the first signal S.sub.1, the second signal S.sub.2 and the third signal S.sub.3 are voltage or current signals. Then, S.sub.1 can equal V.sub.10, S.sub.2 can equal V.sub.12 and S.sub.3 can equal V.sub.20. The phase difference between V.sub.10, V.sub.12 and V.sub.20 are , and as shown in FIG. 3.

(41) In an exemplary embodiment, the detector circuit further comprises a calculation circuit. The calculation circuit can obtain signals that are proportional to |V.sub.1V.sub.2| cos for V.sub.1 and V.sub.2, etc. being the input signals from the multiplication circuit. Based on the above equations the ratios |S.sub.1|/|S.sub.2|, |S.sub.1|/|S.sub.3|, |S.sub.2|/|S.sub.3| and measures for the phase differences , , and =180 can easily be derived via the calculation circuit.

(42) In an exemplary embodiment, the detector circuit further comprises an analog/digital converter. The analog/digital converter can be connected between the multiplication circuit and the calculation circuit. Then the calculation circuit works in the digital domain. However, it is possible that the calculation circuit works in the analog domain and the analog/digital converter is connected behind the calculation circuit.

(43) In an exemplary embodiment, the analog/digital converter is connected before the multiplication circuit. Then, the multiplication circuit and the calculation circuit can work in the digital domain. In this configuration, the multiplication circuit can be integrated in the calculation circuit.

(44) In an exemplary embodiment, the detector circuit further comprises two subtraction circuits determined to derive V.sub.10 and V.sub.12 from three input potentials P.sub.0, P.sub.1, P.sub.2.

(45) In an exemplary embodiment, the detector circuit further comprises a feedback network that generates information about the ratio of two dot products.

(46) In an exemplary embodiment, the multiplication circuit of the detector circuit comprises two (2) double balanced mixers or Gilbert cells, a circuit that is adapted to iteratively generate a digital code based on up/down information at an 1 bit input or an updown-counter, and a feedback network.

(47) In an exemplary embodiment, the signal output of the detector circuit is determined to provide the ratios |V.sub.10|/|V.sub.12|, |V.sub.12|/|V.sub.20|, |V.sub.20|/|V.sub.10|, a measure for the phase difference between V.sub.12 and V.sub.10, a measure for the phase difference between V.sub.20 and V.sub.10, and a measure for the phase difference between V.sub.20 and V.sub.12.

(48) In an exemplary embodiment, the detector circuit is an impedance detector that may be utilized in an impedance measurement system, e.g. of a mobile communication device.

(49) In an exemplary embodiment, the calculation circuit of the detector circuit utilizes a lookup table. A lookup table is a simple but effective means to obtain an angle from cos . Thus, the phase differences , , and can easily be provided at the signal output of the detector circuit.

(50) FIG. 1 schematically shows an embodiment of the detector circuit DC 100 comprising a multiplication circuit MC 110 provided for obtaining two input signals S.sub.1, S.sub.2 at at least two signal inputs (SI.sub.1, SI.sub.2). The two signals S.sub.1 and S.sub.2 may have a form as shown in equations 1 and 2. By multiplying these two signals, e.g. via a dot product circuit in the multiplication circuit MC 110, a product signal is obtained that contains different frequency components as shown in equation 3. The frequency component having a frequency of 2 is removed by the low pass filter LPF 120 connected after the multiplication circuit MC 110. As a result, the low pass filter LPF 120 provides an output signal that is mainly proportional to the dot product S.sub.1S.sub.2. This dot product is analyzed by the calculation circuit CC 130. The dot product S.sub.1S.sub.2 contains information about the absolute value of S.sub.1, the absolute value of S.sub.2 and the phase difference between S.sub.1 and S.sub.2. By extracting the respective information from the input signals, the detector circuit DC 100 is able to provide the ratios. The input signals S1, S2 can carry three different quantities such as electric potentials, voltages or currents simultaneously or one after another.

(51) A multiplication circuit can comprise conventional mixer circuits and further circuit components. The multiplication circuit is, thus, not restricted to a mixer circuit.

(52) FIG. 2 schematically shows a circuit 200 having a signal path SP 210 in which radio frequency signals may propagate. A potentially variable load impedance is denoted as Z.sub.x 212. Further, the signal path SP 210 comprises a sensing element Z.sub.sense 220 used for determining impedance information Z.sub.x. The sensing impedance Z.sub.sense 220 could be established by an inductive element IE. V.sub.10, V.sub.20, and V.sub.12 could be the voltage differences, between the potentials P.sub.0, P.sub.1, and P.sub.2 respectively. In the circuit shown in FIG. 2, when the signals V.sub.10, V.sub.12, and V.sub.20 are voltages, then V.sub.10=V.sub.12+V.sub.20.

(53) FIG. 3 shows the correlations between the input signals V.sub.12, V.sub.10, and V.sub.20. V.sub.12 could be the voltage drop across the sensing element Z.sub.sense, which may be an inductive element. V.sub.10 may be the voltage between the input of the signal path and a ground potential. V.sub.20 is the voltage drop across the unknown load impedance Z.sub.x. Then, V.sub.10 is the sum of voltages V.sub.12 and V.sub.20. Accordingly, the three voltages establish a triangle defined by the length of the vectors and the respective angles. The cosine of each angle is determined by the ratios of the side lengths of the triangle.

(54) FIG. 4A shows an embodiment of the detector circuit 400 where an analog/digital converter ADC 450 is connected after the calculation circuit CC 430. Then, it is possible that a multiplier of the multiplication circuit MC 410, the low pass filter LPF 420 and the calculation circuit CC 430 work in the analog domain. The analog/digital converter ADC 450 provides digital information about amplitudes, amplitude ratios, and/or phase differences.

(55) FIG. 4B shows an embodiment of the detector circuit 401 where the analog/digital converter ADC 450 is connected between the low pass filter LPF 420 and the calculation circuit CC 430. Then, it is possible that a multiplier of the multiplication circuit MC 410 and the low pass filter LPF 420 work in the analog domain while the calculation circuit CC 430 works in the digital domain. It is, however, possible that the input signals, e.g. V.sub.10 and V.sub.12, are directly fed into an analog/digital converter ADC 450 and multiplication, low pass filtering and the calculation of amplitude information or phase difference information is done in the digital domain.

(56) FIG. 4C shows an embodiment of the detector circuit 402 where three input signals S.sub.1, S.sub.2, S.sub.3 can be received via signal inputs SI.sub.1, SI.sub.2, SI.sub.3 and processed simultaneously. Otherwise, the information may be provided by signals applied to two inputs one after another.

(57) FIG. 5 shows an embodiment of the detector circuit DC 500 where input signals V.sub.10, V.sub.12, and V.sub.20 are generated as voltage differences between electrical potentials P.sub.1, P.sub.0, and P.sub.2. The detector circuit DC 500 comprises subtractors 505a, 505b and 505c, configured to generate voltage differences between electrical potentials P.sub.1, P.sub.0, and P.sub.2. The detector circuit DC 500 comprises three chains, each chain comprising a multiplier 510a, 510b, 510c, a low pass filter LPF 520a, 520b, 520c, and an analog/digital circuit ADC 550a, 550b, 550c. With such a three-chain solution, the three dot products can be retrieved simultaneously which can be used to calculate phase differences and level ratios. The multiplication circuit MC comprises at least three sections. Each subsection may comprise a mixer and further circuit components.

(58) FIG. 6 shows an embodiment of the detector circuit 600 where the dot product ratios k.sub.1 and k.sub.2 can be obtained by a feedback loop. The detector circuit DC 600 comprises subtractors 605a, 605b and 605c, configured to generate voltage differences between electrical potentials P.sub.1, P.sub.0, and P.sub.2. The detector circuit 600 comprises three chains. Each chain comprises a multiplier 610a, 610b, 610c, a low pass filter, LPF, 620a, 620b, 620c, an amplifier, AMP, 622a, 622b, 622c, e.g. a variable gain amplifier and optionally an additional low pass filter, LPF, 625a, 625b, 625c. The second chain and the third chain have a feedback loop between the second low pass filter 625b, 625c, and the respective amplifier, AMP, 622b, 622c. The amplifiers 622b, 622c can be variable gain amplifiers. The feedback loop comprises an additional operational amplifier OA 660b and 660c in the second and third chains. The dot products are obtained at the output of the first low pass filter LPF 620a, 620b, 620c of each chain. The feedback loop ensures that the multiplied dot products are identical. For that, the output of the second low pass filter LPF 625a of the first chain is connected to the operational amplifiers OA 660b and 660c of the second and third chain, respectively. As a result of the feedback loops 665b, 665c of the second and third chain, respectively, connected to the output of the second low pass filter 625a of the first chain, the ratio of the gain of the second amplifier 622b and the gain of the first amplifier 622a is identical to the ratio of the dot products: (V.sub.10V.sub.12)/(V.sub.20V.sub.12). The ratio of the gain of the third amplifier 622c and the first amplifier 622a is identical to the ratio of the dot products: (V.sub.10V.sub.12)/(V.sub.12V.sub.20). When the gain of the first amplifier 622a is A.sub.0, the gain of the second amplifier 622b is A.sub.1 and the gain of the third amplifier 622c is A.sub.2 then k.sub.1=A.sub.2/A.sub.0 and k.sub.2=A.sub.1/A.sub.0. If A.sub.0 is a known fixed value A.sub.1 and A.sub.2 can be the input of analog/digital converters ADC 650a, 650b from which k.sub.1 and k.sub.2 can be derived by the calculation circuit CC 630.

(59) FIG. 7 shows an equivalent circuit diagram of a section of a detector circuit comprising two double balanced mixers, i.e. Gilbert cells GC 710 and 720. The lower double balanced mixer 720 multiplies V.sub.12 and V.sub.10. The upper double balanced mixer 710 multiplies V.sub.20 and V.sub.10. The outputs are subtracted from each other by combining the collectors and low pass filtering by the capacitor CAP 715. The differential output voltage is the difference of the two amplified dot products. A comparator COMP 760 in a feedback network FN 765 connected to the combined output of these multiplication circuits, i.e. mixers 710, 720, controls the up/down port of an up/down counter UDC 770 and the contents of the up/down counter UDC 770 controls one of the mixer gains by controlling its tail current. When settled, the ratio of the two tail currents is the ratio of the two dot products and is expressed directly in the digital contents of the up/down counter UDC 770. Instead of the up/down counter UDC 770, another digital block that, e.g. iteratively, generates a digital word based on the comparator output is also possible. Such a block may be a SAR-block (SAR=Successive Approximation Register).

(60) Another system can be used to obtain a dot product ratio, e.g. k.sub.1, as a digital word. Then, k.sub.1 and k.sub.2 can be used directly for the required calculations.

(61) FIG. 8 is a flowchart showing an exemplary embodiment of a method for operating a detector circuit. In block 802, three dot products are determined using at least two input signals. In block 804, at least two dot product ratios are generated from the three dot products. In block 806, amplitude ratios and phase differences are derived for the at least two input signals using the at least two dot product ratios.

(62) The detector circuit is not limited to the embodiments described in the specification or shown in the figures. Phase detectors comprising further elements such as further multiplication circuits, filter circuits and/or calculation circuits or combinations thereof are also comprised by the present invention. The features shown above do not exclude each other. The phase detector can comprise each feature in combination with other features.

LIST OF REFERENCE SYMBOLS

(63) ADC: analog/digital circuit; CAP: capacitive element; CC: calculation circuit; COMP: comparator; DC: detector circuit; FN: feedback network; GC: Gilbert cell; IE: inductive element; LPF: low pass filter; MC: multiplication circuit; OA: operational amplifier; P.sub.1, P.sub.0, P.sub.2: electric potentials; S.sub.1, S.sub.2, S.sub.3: input signals; SI.sub.1, SI.sub.2, SI.sub.3: signal inputs; SO: signal output; SP: signal path; SU: subtraction circuit; UDC: up/down counter; V.sub.10, V.sub.12, V.sub.20: input signals; V.sub.1, V.sub.2: input signals; Z, Z.sub.sense, Z.sub.x: impedances; , , : phase differences between input signals; , , , : phase differences between input voltages or currents.

(64) The detector circuit described herein may be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The detector circuit may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

(65) An apparatus implementing the detector circuit described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.

(66) In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

(67) As used in this description, the terms component, database, module, system, and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device may be a component. One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components may execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal).

(68) Although selected aspects have been illustrated and described in detail, it will be understood that various substitutions and alterations may be made therein without departing from the spirit and scope of the present invention, as defined by the following claims.