MEASUREMENT INSTRUMENT AND METHOD FOR ACQUIRING AN INPUT SIGNAL

Abstract

A measurement instrument for acquiring an input signal is described. The measurement instrument includes a first acquisition path with a first acquisition circuit having a first sampling rate. The measurement instrument includes at least one second acquisition path with a second acquisition circuit, having a second sampling rate. The measurement instrument is configured to acquire the input signal with an overall sampling rate being higher than the first sampling rate and the second sampling rate. The first acquisition path and the at least one second acquisition path each have a decimation filter and a decimator connected in series to the decimation filter, thereby equalizing a low frequency band in the input signal when processing the input signal. Further, method of acquiring an input signal is described.

Claims

1. A measurement instrument for acquiring an input signal, the measurement instrument comprising: a first acquisition path with a first acquisition circuit, the first acquisition circuit having a first sampling rate; and at least one second acquisition path with a second acquisition circuit, the second acquisition circuit having a second sampling rate; wherein the measurement instrument being configured to acquire the input signal with an overall sampling rate, the overall sampling rate being higher than the first sampling rate, the overall sampling rate being higher than the second sampling rate, and wherein the first acquisition path and the at least one second acquisition path each having a decimation filter and a decimator connected in series to the decimation filter, thereby equalizing a low frequency band in the input signal when processing the input signal.

2. The measurement instrument according to claim 1, wherein the respective decimation filters comprise distributed low pass filters.

3. The measurement instrument according to claim 1, wherein the measurement instrument has an adder that is associated with the decimators of the acquisition paths, and wherein the adder adds decimated output signals of the decimators, thereby providing an added signal.

4. The measurement instrument according to claim 3, wherein the measurement instrument has at least one low frequency equalization filter receiving the added signal for conducting a low frequency band equalization.

5. The measurement instrument according to claim 4, wherein the low frequency equalization filter is established by an infinite impulse response (IIR) filter.

6. The measurement instrument according to claim 4, wherein the low frequency equalization filter provides a filter output signal.

7. The measurement instrument according to claim 6, wherein the measurement instrument comprises a memory associated with the low frequency equalization filter, and wherein the memory is configured to store the filter output signal.

8. The measurement instrument according to claim 6, wherein the measurement instrument is configured to equalize a digitized input signal based on the filter output signal.

9. The measurement instrument according to claim 4, wherein the at least one low frequency equalization filter is a common low frequency equalization filter that is provided for the different acquisition paths commonly.

10. The measurement instrument according to claim 4, wherein the at least one low frequency equalization filter is established on a separate chip with respect to the acquisition paths.

11. The measurement instrument according to claim 4, wherein the at least one low frequency equalization filter is established on a chip on which at least one acquisition path is also established.

12. The measurement instrument according to claim 4, wherein the measurement instrument comprises a post-processing module that is connected with the at least one low frequency equalization filter and the acquisition paths.

13. The measurement instrument according to claim 12, wherein the post-processing module is configured to process a filter output signal of the at least one low frequency equalization filter and the acquired signals of the acquisition paths in a synchronized manner, thereby providing an equalized output signal.

14. The measurement instrument according to claim 1, wherein the acquisition paths are established in hardware circuitry.

15. The measurement instrument according to claim 1, wherein the decimator filters comprise a distributed periodic time variant filter for compensating frequency mismatches.

16. The measurement instrument according to claim 1, wherein the sum of the first sampling rate of the first acquisition circuit and the second sampling rate of the at least one second acquisition circuit equals the overall sampling rate.

17. The measurement instrument according to claim 1, wherein the first sampling rate and the second sampling rate are equal.

18. The measurement instrument according to claim 1, wherein the first acquisition circuit and the at least one second acquisition circuit are provided on separately formed circuit chips.

19. The measurement instrument according to claim 1, wherein the first acquisition circuit is established by an application-specific integrated circuit or a field-programmable gate array and/or wherein the second acquisition circuit is established by an application-specific integrated circuit or a field-programmable gate array.

20. A method of acquiring an input signal, the method comprising: acquiring the input signal with a first sampling rate within a first acquisition path by a first acquisition circuit; acquiring the input signal with a second sampling rate within at least one second acquisition path by a second acquisition circuit, wherein the measurement instrument acquiring the input signal with an overall sampling rate that is higher than the first sampling rate and the second sampling rate; and the first acquisition path and the at least one second acquisition path each equalizing a low frequency band in the input signal by a decimator connected in series to a decimation filter within the acquisition paths when processing the input signal.

Description

DESCRIPTION OF THE DRAWINGS

[0060] The foregoing aspects and many of the attendant advantages of the claimed subject matter will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

[0061] FIG. 1 schematically shows an overview of a measurement instrument according to an embodiment of the present disclosure;

[0062] FIG. 2 schematically shows an overview of a representative decimation filter used by the measurement instrument according to an embodiment of the present disclosure; and

[0063] FIG. 3 schematically shows an overview illustrating the distributed decimation filter architecture.

DETAILED DESCRIPTION

[0064] The detailed description set forth below in connection with the appended drawings, where like numerals reference like elements, is intended as a description of various embodiments of the disclosed subject matter and is not intended to represent the only embodiments. Each embodiment described in this disclosure is provided merely as an example or illustration and should not be construed as preferred or advantageous over other embodiments. The illustrative examples provided herein are not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed. Similarly, any steps described herein may be interchangeable with other steps, or combinations of steps, in order to achieve the same or substantially similar result. Moreover, some of the method steps can be carried serially or in parallel, or in any order unless specifically expressed or understood in the context of other method steps.

[0065] In the foregoing description, specific details are set forth to provide a thorough understanding of exemplary embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that the embodiments disclosed herein may be practiced without embodying all of the specific details. In some instances, well-known process steps have not been described in detail in order not to unnecessarily obscure various aspects of the present disclosure. Further, it will be appreciated that embodiments of the present disclosure may employ any combination of features described herein.

[0066] FIG. 1 schematically shows a measurement instrument 10 that may be established, for example, as an oscilloscope. The measurement instrument 10 has an input 12 for receiving an input signal with a certain data rate. The input signal may have a data rate of 320 GS/s.

[0067] The input 12, which is illustrated by the dashed lines, is established as a time-interleaved input that spreads the input signal across multiple acquisition paths 14, 16, 18, 20 by using delay lines 22 between adjacent acquisition paths 14-20. The acquisition paths 14-20 are labelled by RTCH0-RTCH3 in the shown embodiment since the acquisition paths 14-20 may be established by Reversed Traffic Channels.

[0068] Besides the delay lines 22, the input 12 also comprises decimators 24 associated with the acquisition paths 14-20 in order to reduce the data rate and to establish a time-interleaved acquisition architecture. The decimators 24 may have a decimation factor of 4 such that the acquisition paths 14-20 each have a sampling rate of 80 GS/s. Hence, the sum of the sampling rates of the acquisition paths 14-20 equals an overall sampling rate of the measurement instrument, namely 320 GS/s that corresponds to the data rate of the input signal. Moreover, the different acquisition paths 14-20 have an equal sampling rate, namely 80 GS/s. Accordingly, each of the acquisition paths 14-20 receives a decimated input signal that has been processed by a corresponding decimator 24 previously.

[0069] In some embodiments, the acquisition paths 16-20 each comprise a delayed and decimated input signal, as the input signal has been previously delayed by the respective delay lines 22.

[0070] In the shown embodiment, four acquisition paths 16-20 are provided such that three delay lines 22 are provided. The decimators 24 associated with the input 12 have a decimation factor or rather decimation ratio of 4 that corresponds to the number of acquisition paths 16-20, thereby ensuring the time-interleaved acquisition architecture.

[0071] The acquisition paths 14-20 each comprise a respective acquisition circuit 26-32 that is implemented, for example, on a certain chip. For instance, the acquisition circuits 26-32 may be established by application-specific integrated circuits (ASICs). Alternatively, the acquisition circuits 26-32 are established by field-programmable gate arrays (FPGAs). Hence, the acquisition circuits 26-32 may be implemented by integrated circuits (ICs). However, the acquisition paths 14-20, for example the respective acquisition circuits 26-32, may be provided on separately formed circuits, e.g., chips.

[0072] As shown in FIG. 1, each of the acquisition circuits 26-32 comprise a decimation filter 34-40 as well as a decimator 42-48 that is connected in series with the decimation filter of the respective acquisition path 14-20. Hence, a distributed filter architecture is established, wherein the decimation filters 34-40 correspond to low pass filters. Thus, distributed low pass filters are provided. In FIG. 2, a respective overview of an exemplary distributed low pass filter is provided.

[0073] The decimators 42-48 of the respective acquisition paths 14-20 may have a decimation factor of 64. Therefore, the data rate of the input signal corresponds to 320 GS/s, whereas the decimated output signal of the corresponding decimator 42-48 relates to 1.25 GS/s such that the decimation factor or rather decimation ratio is 256. For instance, two stages may be provided, wherein one sample per stage is processed. In other words, a two-tap decimation filter, e.g., a 2-tap finite impulse response (FIR) filter with constant coefficients is provided.

[0074] Generally, the decimation filters 34-40 together with the subsequent decimators 42-48 correspond to a decimating cascade-integrator comb (CIC) filter.

[0075] The respective concept is illustrated in FIG. 3, wherein each of the respective distributed low pass filters, e.g. the decimating CIC filter, may be defined as follows:

[00002]$H\left(z\right)={\left(\frac{1-z^{-\mathrm{RM}}}{1-z^{-1}}\right)}^N={\left(\underset{k=0}{\overset{\mathrm{RM}-1}{.Math.}}{z}^{-k}\right)}^N,$

[0076] wherein R corresponds to a decimation or interpolation ratio, M corresponds to a number of samples per stage, and N corresponds to the number of stages in the filter.

[0077] Generally, the decimators 42-48 process the filtered input signals, thereby providing decimated output signals for further processing.

[0078] The respective decimators 42-48 are connected with an adder 50 that adds the decimated output signals provided by the decimators 42-48, thereby providing an added signal.

[0079] In the shown embodiment, the adder 50, which is associated with the decimators 42-48 of the acquisition paths 14-20, is provided in a distributed manner, as the acquisition circuits 14-18 forward their decimated output signals to the respective next acquisition circuit 16-20 such that the added signal is provided by the last acquisition circuit 20. Alternatively, the adder 50 may be established on a separate circuit, e.g., chip, that is connected with all of the acquisition circuits 14-20 such that the decimated output signals of all acquisition circuits 14-20 is received and processed by the separately formed adder 50 that provides the added signal for further processing.

[0080] The added signal is forwarded to a low frequency equalization (LFEQ) filter 52 that conducts a low frequency band equalization on the added signal obtained. The low frequency equalization filter 52 may be established by an infinite impulse response (IIR) filter or rather a finite impulse response (FIR) filter. In any case, the low frequency equalization filter 52 receives a signal with a data rate significantly reduced compared to the data rate of the input signal, namely the added signal, as well as the output signals of the acquisition paths. In some embodiments, the added signal also has a data rate of 1.25 GS/s similar to the one of the decimated output signals of the respective decimators 42-48, whereas the input signal has a data rate of 320 GS/s, and wherein the acquisition paths 14-20 each provide an output signal with a data rate of 80 GS/s, as four acquisition paths 14-20 are provided. The low frequency equalization filter 52 processes the added signal while outputting a filter output signal that is used for further processing.

[0081] The measurement instrument 10 further comprises a post-processing module 54 that is connected with the different and separately formed acquisition paths 14-20 while receiving the output signals of the acquisitions paths 14-20 as shown in FIG. 1. Optionally, random access memories (RAM) 55 are interconnected between the post-processing module 54 and the acquisition paths 14-20. In addition, the post-processing module 54 also receives the filter output signal of the low frequency equalization filter 52. In some embodiments, the post-processing module 54 includes circuitry configured for carrying out some of or all of its functionality described herein.

[0082] The measurement instrument 10 also comprises at least one memory 56, such as a memory circuit, that is interconnected between the post-processing module 54 and the low frequency equalization filter 52. The memory 56 may be established by a random-access memory (RAM). Hence, the filter output signal may be stored previously prior to being post-processed by the post-processing module 54. Moreover, the filter out signal may be decimated or rather interpolated prior to being stored in the memory 56.

[0083] The measurement instrument 10 further may comprise an up-sampling circuit 58, for instance a cascaded integrator-comb interpolator (CICI) circuit. The up-sampling circuit 58 receives the filter output signal, for example from the memory 56. The up-sampling circuit 58 interpolates the filter output signal such that the post-processing module 54 receives a signal with the data rate of the input signal. Hence, the post-processing module 54 is enabled to add the up-sampled filter output signal to the output signals of the different acquisition paths 14-20.

[0084] The low frequency equalization filter 52 is a common low frequency equalization filter that is provided for the different acquisition paths 14-20 simultaneously, as the low frequency equalization filter 52 receives the added signal provided by the adder 50 that sums the decimated output signals of the decimators 42-48 of the individual acquisition paths 14-20.

[0085] Thus, the low frequency equalization filter 52 is associated with each of the individual acquisition paths 14-20 such that resources can be saved since the single low frequency equalization filter 52, which is established on a separate chip with respect to the acquisition paths 14-20, is sufficient for performing the low frequency response equalization on the input signal.

[0086] Accordingly, the measurement instrument 10 is generally configured to equalize a digitized input signal based on the filter output signal. The equalization is done by the post-processing module 54.

[0087] In some embodiments, the post-processing module 54 is provided on a separate circuit, e.g., chip, with respect to the acquisition paths 14-20.

[0088] In the embodiment shown in FIG. 1, the post-processing module 54 and the low frequency equalization filter 52 together are implemented on a common chip 60, for instance by a field-programmable gate array (FPGA). The several different acquisition paths 14-20 each are also implemented on different chips, for instance by application-specific integrated circuits (ASICs).

[0089] In some embodiments, the post-processing module 54 is established in hardware and software, whereas the acquisition paths 14-20 and the low frequency equalization filter 52 are established in hardware solely, thereby ensuring a real-time processing.

[0090] Furthermore, the decimator filters 34-40 may comprise a distributed periodic time variant filter for compensating frequency mismatches that take place between analog parts of the acquisition paths 14-20. In some embodiments, the distributed periodic time variant filter is configured to compensate a mismatch between transfer functions associated with different acquisition paths 14-20, for example based on digital output signals provided by the respective acquisition paths 14-20.

[0091] Certain embodiments disclosed herein, for example the respective module(s), filters, other electrical components, etc., utilize circuitry (e.g., one or more circuits) in order to implement standards, protocols, methodologies or technologies disclosed herein, operably couple two or more components, generate information, process information, analyze information, generate signals, encode/decode signals, convert signals, transmit and/or receive signals, control other devices, etc. Circuitry of any type can be used. It will be appreciated that the term “information” can be use synonymously with the term “signals” in this paragraph. It will be further appreciated that the terms “circuitry,” “circuit,” “one or more circuits,” etc., can be used synonymously herein.

[0092] In an embodiment, circuitry includes, among other things, one or more computing devices such as a processor (e.g., a microprocessor), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a system on a chip (SoC), or the like, or any combinations thereof, and can include discrete digital or analog circuit elements or electronics, or combinations thereof. In an embodiment, circuitry includes hardware circuit implementations (e.g., implementations in analog circuitry, implementations in digital circuitry, and the like, and combinations thereof).

[0093] In an embodiment, circuitry includes combinations of circuits and computer program products having software or firmware instructions stored on one or more computer readable memories that work together to cause a device to perform one or more protocols, methodologies or technologies described herein. In an embodiment, circuitry includes circuits, such as, for example, microprocessors or portions of microprocessor, that require software, firmware, and the like for operation. In an embodiment, circuitry includes one or more processors or portions thereof and accompanying software, firmware, hardware, and the like.

[0094] The present application may reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but exemplary of the possible quantities or numbers associated with the present application. Also in this regard, the present application may use the term “plurality” to reference a quantity or number. In this regard, the term “plurality” is meant to be any number that is more than one, for example, two, three, four, five, etc. The terms “about,” “approximately,” “near,” etc., mean plus or minus 5% of the stated value. For the purposes of the present disclosure, the phrase “at least one of A and B” is equivalent to “A and/or B” or vice versa, namely “A” alone, “B” alone or “A and B.”. Similarly, the phrase “at least one of A, B, and C,” for example, means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all further possible permutations when greater than three elements are listed.

[0095] The principles, representative embodiments, and modes of operation of the present disclosure have been described in the foregoing description. However, aspects of the present disclosure which are intended to be protected are not to be construed as limited to the particular embodiments disclosed. Further, the embodiments described herein are to be regarded as illustrative rather than restrictive. It will be appreciated that variations and changes may be made by others, and equivalents employed, without departing from the spirit of the present disclosure. Accordingly, it is expressly intended that all such variations, changes, and equivalents fall within the spirit and scope of the present disclosure, as claimed.