Circuit for improving clock rates in high speed electronic circuits using feedback based flip-flops

Abstract

A flip-flop circuit for enhancing clock rates in high speed electronic circuits, the flip-flop circuit having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal, comprising: two latches arranged in a master-slave configuration such that the input terminal of the first latch is also the input terminal of the flip-flop and the output terminal of the second latch is also the output terminal of the flip-flop; and at least one feedback path that adds signal to the input of the flip-flop from one of the outputs of the two latches.

Claims

1. A flip-flop having an input terminal and an output terminal, comprising: a first latch having an input terminal and an output terminal; a second latch having an input terminal and an output terminal, wherein the first latch and the second latch are arranged in a master-slave configuration such that the input terminal of the first latch is also the input terminal of the flip-flop and the output terminal of the second latch is also the output terminal of the flip-flop, and wherein the output terminal of the first latch is directly connected to the input terminal of the second latch; and at least one feedback path for adding signal from the output terminal of the second latch to the input terminal of the first latch wherein both the output terminal of the second latch and the input terminal of the first latch are directly connected to a first feedback circuit of the at least one feedback path, or from the output terminal of the first latch to the input terminal of the first latch wherein both the output terminal of the first latch and the input terminal of the first latch are directly connected to a second feedback circuit of the at least one feedback path; wherein the at least one feedback path comprises at least one of an always active (ON) transconductance stage and an always active (ON) inverter stage.

2. The flip-flop as claimed in claim 1, wherein the at least one feedback path comprises: a first feedback path from the output terminal of the first latch to the input terminal of the first latch; a second feedback path from the output terminal of the second latch to the input terminal of the second latch; and a third feedback path from the output terminal of the second latch to the input terminal of the first latch.

3. The flip-flop as claimed in claim 1, wherein the at least one feedback path comprises: a first feedback path from the output terminal of the first latch to the input terminal of the first latch; and a third feedback path from the output terminal of the second latch to the input terminal of the first latch.

4. The flip-flop as claimed in claim 1, wherein the at least one feedback path comprises: a second feedback path from the output terminal of the second latch to the input terminal of the second latch; a third feedback path from the output terminal of the second latch to the input terminal of the first latch.

5. The flip-flop as claimed in claim 1, wherein the at least one feedback path is a negative feedback path.

6. The flip-flop as claimed in claim 1, wherein a strength of a feedback of the at least one feedback path is adapted using a control mechanism.

7. The flip-flop as claimed in claim 1, wherein the at least one feedback path comprises: a first feedback path from the output terminal of the first latch to the input terminal of the first latch; and a second feedback path from the output terminal of the second latch to the input terminal of the second latch.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Reference will be made to embodiments of the invention, examples of which may be illustrated in accompanying figures. These figures are intended to be illustrative, not limiting. Although the invention is generally described in context of these embodiments, it should be understood that it is not intended to limit the scope of the invention to these particular embodiments.

(2) FIG. 1 is a block diagram of circuit according to present invention;

(3) FIG. 2 is a simulation result with input data at 11.9 Gb/s data rate;

(4) FIG. 3 is a block diagram of D-Flip-Flop based on feedback based latches;

(5) FIG. 4 is a schematic view of feedback based latches of a D Flip-Flop according to present invention;

(6) FIG. 5a is a block diagram of latch according to present invention;

(7) FIG. 5b shows equivalent circuit of the block diagram described in FIG. 4a;

(8) FIG. 6 is an equivalent circuit at the input of latch described in FIG. 4a;

(9) FIG. 7 is a time domain waveform for transparent mode of conventional latch and feedback based latch for =0.7;

(10) FIG. 8 is a frequency domain waveform for various for second order equations;

(11) FIG. 9 is a simulation result with input data at 12.2 Gb/s data rate;

(12) FIG. 10 is a block diagram of feedback based D-Flip-Flop using feedback based latches;

(13) FIG. 11 is a simulation result with input data at 13.5 Gb/s data rate;

(14) FIG. 12 is an eye diagram of feedback based D-Flip-Flop using feedback based latches output (13.5 Gb/s data rate, jitter.sub.pp=3.6 ps and eye opening=300 mv);

(15) FIG. 13 is a block diagram of 2.sup.71 PRBS generator;

(16) FIG. 14a is simulation result at 10.6 Gb/s data rate

(17) FIG. 14b is an eye diagram of XOR output at 10.6 Gb/s data rate (jitter.sub.pp=4 ps in the conventional PRBS generator and eye opening=160 mv);

(18) FIG. 15 is a block diagram of equalized XOR and D-Flip-Flop;

(19) FIG. 16a is a simulation result at XOR output node;

(20) FIG. 16b is a simulation results after D-Flip-Flop output node

(21) FIG. 16c is an eye diagram of compensated XOR, D-Flip-Flop at 10.6 Gb/s data rate (jitter.sub.pp=3.5 ps and eye opening=240 my in the proposed PRBS generator);

(22) FIG. 17a is a simulation result of 2.sup.71 PRBS generator (complete 127 cycles);

(23) FIG. 17b is eye diagram for 2.sup.71 PRBS generator at 13 Gb/s data rate (jitter.sub.pp=8 ps and eye opening=200 mv);

(24) FIG. 18 is a block diagram of clock and data recovery circuits with feedback based flip-flops;

(25) FIG. 19 is a simulation result of Hogge phase detector based CDR circuit;

(26) FIG. 20 is a block diagram of Serializer;

(27) FIG. 21 is a block diagram of Deserializer.

DETAILED DESCRIPTION OF THE INVENTION

(28) The present invention relates to circuit for enhancing clock rates in a high speed electronic circuits thereby improving the performance of high speed communication links.

(29) Finite output impedance of the source and large input capacitance in a conventional D-Flip Flop forms a low pass filter. To nullify the effect of this low pass filter, a high pass filter is needed. According to the present invention, this high pass filter is implemented by an always active (ON) negative feedback across D-Flip-Flop, where no external control is required for enabling and disabling the feedback. Each D-Flip-Flop of communication systems are thus used to equalize previous erroneous data which forms distributed equalizer so additional power hungry equalizers requirement is relaxed.

(30) FIG. 1 is a block diagram of circuit according to present invention. As shown in the circuit, an always active (ON) negative feedback loop 102 is connected across a conventional D-Flip-Flop 104 according to present invention to adjust or correct or enhance the clock input of the D-Flip-Flop, where no external control is required for enabling and disabling the feedback. Negative feedback across D-Flip-Flop also mitigates timing errors which is caused by RC delay at the input of D-Flip-Flop.

(31) FIG. 2 is a simulation result using the circuitry described in FIG. 1 with input data at 11.9 Gb/s data rate. FIG. 2a shows an input data at 11.9 Gb/s data rate. FIG. 2b shows the result of a conventional D-Flip-Flop wherein data rate of 11.9 Gb/s is not resolved. FIGS. 2c and 2d shows that D-Flip-Flop according to present invention is working fine with 200 mV input data in same simulation conditions. FIG. 2d relates to eye diagram of D-Flip-Flop according to present invention showing 326 mV eye opening with 7 ps jitter.sub.pp. It may be noted that any adaptive algorithm for finding feedback coefficient of feedback e.g. least square algorithm, least mean square algorithm may be implemented. The feedback can be adaptive, based on load conditions i.e. the feedback coefficient is adjusted based on adaptive algorithms.

(32) In another embodiment of the present invention, circuit according to present invention is a master slave configuration. FIG. 3 shows a master-slave configuration of D-Flip-Flop according to present invention. There are two CML latches 302; 304 having respective always active (ON) local feedback 306; 308. Each latch 302; 304 in a master-slave configuration have two modes of operation, transparent mode and latch mode. In, D-Flip-Flop when clock is high, master latch is in transparent mode and slave latch is in latch mode and vice-versa. As mentioned, always active (ON) local negative feedback 306; 308 is employed in each of the D-Flip-Flop, where no external control is required for enabling and disabling the feedback. In transparent mode, it will cause 2-stage amplification using amplifying stage. Here, it is shown as a buffer 310; 312 but it can be any gm cell. For two stage amplifiers, the overall dc gain and the bandwidth are obtained by G.sub.T=G.sup.2 and .sub.bw={square root over (2.sup.1/21)}.

(33) FIGS. 1, 3 and 10 particularly describes a flip-flop having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal. The flip-flop comprises two latches arranged in a master-slave configuration such that the input terminal of the first latch is also the input terminal of the flip-flop and the output terminal of the second latch is also the output terminal of the flip-flop; and at least one always active (ON) feedback path that adds signal to the input of the flip-flop from one of the outputs of the two latches. The feedback path may be a path from the output of the flip-flop and added to the input of the flip-flop or a path from the output of the first latch and is added to the input of the flip-flop. The flip-flop described herein may also comprise a first feedback path from the output of the first latch and is added to the input of the flip-flop; and a second feedback path from the output of the flip-flop and is added to the input of the second latch. The feedback path may further comprise a transconductance stage or an inverter stage. The feedback may be a negative feedback and further the strength of feedback can be adapted using a control mechanism.

(34) FIG. 4 is a schematic view of feedback based latches of a D Flip-Flop according to present invention. FIG. 4 shows an always active (ON) feedback circuit comprising transistors M5, M6 and M8, where no external control is required for enabling and disabling the feedback. Output voltages V.sub.out+ and V.sub.out are fed to the feedback circuit through transistors M6 and M5 respectively, wherein clock signal Clk and Clk+ are connected to transistors M13 and M9, respectively. In this regard when clock signal CLK+ is high the amplifier works and when clock signal CLK is low then the feedback circuit works.

(35) FIG. 5a is a block diagram of latch according to present invention comprising an amplifier 401, a positive feedback 402, buffer 404, and a feedback 403. Feedback 403 is an always active (ON) negative feedback where no external control is required for enabling and disabling the feedback, according to present invention as described hereinbefore. FIG. 5a describes a latch having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal, comprising: an amplifier stage whose input terminal is the input terminal of the latch and the output terminal is the output terminal of the latch; a positive feedback stage connected to the output terminal of the latch; and a feedback path that adds signal to the input of the latch from the output of the latch. The feedback path from the output terminal to the input terminal may be a transconductance stage or an inverter stage. The feedback may be a negative feedback and further the strength of feedback can be adapted using a control mechanism.

(36) FIG. 5b shows equivalent circuit of the block diagram described in FIG. 5a wherein the circuit comprises a latch amplifier 404, an always active (ON) latch feedback 405 and buffer 406. FIG. 6 is an equivalent circuit at the input of latch described in FIG. 4a wherein I.sub.in denotes input current, inductance L.sub.s connected with resistance R.sub.s whereas C.sub.p and R.sub.p are parallel capacitance and resistance of the circuit.

(37) Referring to FIGS. 4a and 4b, it gives:

(38) $\begin{array}{cc}-i_{\mathrm{in}}-g_{\mathrm{mf}}{V}_{\mathrm{out}}+V_1/R_1+V_1{C}_{1}s=0& \left(1\right)\\ g_{m2}-V_1+V_{\mathrm{out}}/R_L+V_{\mathrm{out}}{C}_{L}s=0& \left(2\right)\\ \frac{i_{\mathrm{in}}}{V_1}=\frac{\frac{1}{\left(R_L+C_{L}s\right)}}{g_{m2}{g}_{\mathrm{mf}}}+\frac{1}{R_1}+{\mathrm{sC}}_1& \left(3\right)\end{array}$

(39) Equation 3 shows an inductive peaking where, R.sub.p=R.sub.1, C.sub.p=C.sub.1,

(40) $R_s=\frac{R_L}{g_{m2}{g}_{\mathrm{mf}}}\mathrm{and}{C}_s=\frac{C_L}{g_{m2}{g}_{\mathrm{mf}}}.$
Transparent mode shows improvement because it generates inductive peaking at the input of latch. It causes parallel resonance.

(41) $\begin{array}{cc}\frac{V_{\mathrm{out}}}{V_1}=-\frac{g_{m2}}{\left(\frac{1}{R_L}+{\mathrm{sC}}_L\right)}& \left(4\right)\end{array}$

(42) Equation 4 shows gain stage but at the same time, V.sub.out/V.sub.in is determined by FIGS. 5a and 5b. Such an arrangement employs a transconductance stage G.sub.mf to return a fraction of the output to the input of G.sub.m2. The transfer function of the overall amplifier is given by:

(43) $\begin{array}{cc}\frac{V_{\mathrm{out}}}{V_{\mathrm{in}}}=\frac{A_{\mathrm{vo}}{n}^2}{s^1+2S+{}_n^2}\mathrm{Where},& \left(5\right)\\ A_{\mathrm{vo}}=\frac{G_{m1}{G}_{m2}{R}_1{R}_L}{1+G_{m1}{G}_{m2}{R}_1{R}_L}& \left(6\right)\\ =\frac{1}{2}\frac{R_1{C}_1+R_L{C}_L}{\sqrt{R_1{R}_L{C}_1{C}_L\left(1+G_{m1}{G}_{m2}{R}_1{R}_L\right)}}& \left(7\right)\\ n^2=\frac{1+G_{\mathrm{mf}}{G}_{m2}{R}_1{R}_L}{R_1{R}_L{C}_1{C}_L}& \left(8\right)\end{array}$

(44) Denominator of RHS of equation is second order equation 5. It provides complex conjugate poles which cause frequency resonance and peaking depending on as shown in FIG. 6. FIG. 7 is a time domain waveform for transparent mode of conventional latch and feedback based latch for =0.7 whereas FIG. 8 is a frequency domain waveform for various for second order equations. For an maximally-flat butter-worth response, ={square root over (2)}/2. The result reveals that always active (ON) local negative feedback increases the GBW in transparent phase of latch. In the place of buffer, any g.sub.m cell providing current to its capacitive load can be used. Time delay for latches are given by:

(45) $\begin{array}{cc}{T}_d=\ln \frac{V_{\mathrm{logic}}}{V}\mathrm{Where},=\frac{G_m}{C}& \left(9\right)\end{array}$
G.sub.m=Trans-conductance of latch transistors.
C=output capacitances.
V.sub.logic=Voltage level to be achieved.
V=Minimum input that can be resolved correctly.

(46) By using proposed D-Flip-Flop, V will be higher as compare to conventional D-Flip-Flop which leads to less time for latching for same clock frequency. Its application in serializers and deserilizers are shown in FIGS. 20 and 21.

(47) FIG. 9 is a simulation result with input data at 12.2 Gb/s data rate. Data rate of the D-Flip-Flop is enhanced by approximately 30% using local negative feedback in transparent phase of latch. This increases the data rate by 31% of the high speed D-Flip-Flop with 25% area and 12.5% power overhead. Simulation results in standard 90 nm CMOS technology of the high speed simulation confirmed the working of this technique with 12.2 Gb/s data rate, while consuming 18 mW off a 1V supply.

(48) FIG. 10 shows feedback based flip-flops using feedback based latches according to present invention. In this technique, advantage of feedback 1002; 1004 across latches 1008; 1010 based D-Flip-Flop and feedback based D-Flip-Flop are incorporated by adding same number of always active (ON) negative feedback loops across D-Flip-Flop, where no external control is required for enabling and disabling the feedbacks. This improves high speed D-Flip-Flop by 45%. This is applicable to all the applications mentioned hereinafter for feedback based flip-flops and negative feedback across latches based D-Flip-Flop. Feedback is provided by transconductance stage during implementation that can be made adaptive in nature based on process corner, temperature and decision of input. FIGS. 11 and 12 show simulation results of feedback based flip-flops with negative feedback across latches. This shows for 13.5 Gb/s input data-rate, only modified feedback based D-Flip-Flop with feedback across latches is working fine. A detailed comparison of D-Flip-Flops for same technology is shown in Table 1.

(49) TABLE-US-00001 TABLE 1 Feed- back Con- Feed- Feed- in DFF CML DFF ven- Series back back in and based on tional Inductors in DFFs latches Latches Power (mW) 16 16 17 18 19 Speed (Gb/s) 9.25 13 11.9 12.2 13.5 Area (um.sup.2) 30 40 200 220 30 44 30 50 30 54 Eye Opening (mV) 438 247 326 340 300 $Q=\frac{\mathrm{Eye}\text{-}\mathrm{opening}}{\mathrm{Max}\left(\mathrm{eye}\text{-}\mathrm{amp}.\right)}\left(\%\right)$ 87 56 60 62 81.3 Jitter.sub.pp (ps) 13 18 7 5.3 3.6 $\mathrm{FOM}\left(\frac{\mathrm{Gbit}}{J\mathrm{Hz}{m}^2}\right)$ 4.01 0.15 4.41 3.76 3.65

(50) $\mathrm{FOM}=\frac{\mathrm{DataRate}}{f_T\mathrm{Area}\mathrm{Power}}\left(\mathrm{The}\mathrm{higher}\mathrm{the}\mathrm{better}\right)$

Example 1

(51) Pseudo Random Binary Sequence Generator (PRBSG)

(52) FIG. 13 is a block diagram of 2.sup.71 PRBS generator. A Pseudo Random Binary Sequence Generator (PRBSG) is based on linear feedback shift registers (LFSR). It contains minimum N flip-flops for 2.sup.N1 PRBSG. Number of XORs and tapping of XORs ensure pseudo random sequence. 2.sup.71 PRBSG and its critical path are shown in FIG. 13. Maximum clock frequency is given by:

(53) $\begin{array}{cc}{f}_{{\mathrm{Clk}}_{\max }}=\frac{1}{T_{D{67}_{\mathrm{Clk}-Q}}+T_{\mathrm{PXOR}}+T_{D{1}_{\mathrm{set}-\mathrm{up}}}}& \left(10\right)\end{array}$
Where, T.sub.D67.sub.Clk-Q=Max(T.sub.D6.sub.Clk-Q, T.sub.D7.sub.Clk-Q), T.sub.D6.sub.Clk-Q=Clock-to-Q delay of 6th D-Flip-Flop, T.sub.D7.sub.Clk-Q=Clock-to-Q delay of 7th D-Flip-Flop, T.sub.PXOR=propagation delay of XOR and T.sub.D1.sub.set-up=Setup time of D-Flip-Flop.

(54) In propagation delay of XOR, interconnect delay is major contributor because it contains longest path as shown in FIG. 13 thus making it the critical path. Each node of the PRBSG consist of parasitic resistance and capacitance which causes ISI. For example, parasitic resistance and capacitance at the XOR output node consist of
R.sub.par=R.sub.int(11)
C.sub.par=C.sub.D.sub.XOR+C.sub.int+C.sub.G.sub.DFF(12)
Where, R.sub.par=Parasitic resistance of XOR output,
R.sub.int=Parasitic resistance of interconnect,
C.sub.D.sub.XOR=Parasitic capacitance at output XOR,
C.sub.int=Parasitic capacitance of interconnect,
C.sub.G.sub.DFF=Parasitic capacitance of the input of the D-Flip-Flop.

(55) In the present invention work, interconnect is considered as an RC delay line as shown in FIG. 13 and an always active (ON) negative feedback across D-Flip-Flops are applied to enhance its bandwidth. Once the critical path is compensated as mentioned above, the signal path between 2 D-Flip-Flop's becomes the frequency limiting channel. This channel consists of 2 filters, 1) Interconnect between the latch output and CML buffer input of the D-Flip-Flop. 2) Between the CML buffer output and the input of subsequent D-Flip-Flop. These channels are also compensated by putting an always active (ON) feedback around a subsequent D-Flip-Flop's in the same manner. Multiple feedback coefficients can also be used with and without adaptation for improving the performance further. Any adaptation algorithm can be used to estimate feedback factors. FIG. 14a is simulation result at 10.6 Gb/s data rate and FIG. 14b is an eye diagram of XOR output at 10.6 Gb/s data rate (jitter.sub.pp=24 ps in the conventional PRBS generator and eye opening=160 mv).

(56) CML D-Flip-Flop is used to provide delay and output of D-Flip-Flop is fed back to Y through one trans-conductance stage as shown in FIG. 15. The incorporation of the feedback stages changes the parasitic loading. Hence some empirical optimization of the feedback factor at the circuit level needs to be done, which leads to a feedback factor of 0.3. Output of equalized PRBSG is shown in FIG. 16b. FIG. 16c shows the eye diagram which has vertical eye opening of 250 mV and jitter.sub.pp of 3.5 ps. Same technique is employed on other nodes of PRBSG for enhancing data-rate. Only inspection of the eye diagram may not be sufficient, as even a single misinterpreted bit by XOR can reduce the run length of the PRBS drastically. Hence one should verify the PRBS by examining the total generated sequence. Comparison between conventional, inductive peaking based and modified PRBS generator is shown in Table 2.

(57) TABLE-US-00002 TABLE 2 PRBS Gen. Conventional Inductor based Proposed Power (mW) 190 190 222 Maximum Speed (Gb/s)) 10.6 13 13 Area (PRBS core) (um.sup.2) 64 187 800 400 64 220 Eye Opening (mV) 263 247 200 Jitter.sub.pp (ps) 9 15 8 0$\mathrm{FOM}\left(\frac{\mathrm{Gbit}}{J\mathrm{Hz}{m}^2}\right)$ 93.1 3.48 90.84

(58) $\mathrm{FOM}=\frac{{\log }_2\left(\mathrm{MLS}\right)\mathrm{DataRate}}{f_T\mathrm{Area}\mathrm{Power}}\left(\mathrm{The}\mathrm{higher}\mathrm{the}\mathrm{better}\right)$

(59) In modified PRBSG, speed is increased with approximately same FOM. Simulation results at 13-Gb/s confirm correct functional operation of the PRBS as shown in FIG. 17a and FIG. 17b. As a worst case a triangular waveform is used as the clock. Simulation are performed in typical-typical corner with temperature of 100 C. For optimized performance across temperature and process variations, the feedback factor can be adjusted by adjusting current in the feedback amplifier.

Example 2

(60) Clock and Data Recovery (CDR) Circuit

(61) Clock and data recovery (CDR) circuits are used for clock extraction and re-timing of data at receiver side. In this demonstration of feedback across latches based D-Flip-Flop, phase detector of CDR circuit is modified. Hogge phase detector is shown in FIG. 18. Simulation results shown in FIG. 19 reflects proposed D-Flip-Flop based CDR has good eye opening with less jitter as compare to conventional D-Flip-Flop based CDR which helps it in settle quickly. Similarly, any type of phase detector can be used in same fashion with proposed negative feedback based D-Flip-Flop. This technique can also be employed on serialization of data before the multiplexer and also in de-multiplexing of data.

Example 3

(62) Serializers and Deserializers

(63) Implementation of negative feedback across latches based D-Flip-Flop, as described in FIG. 3, in serializers and deserializers are shown in FIGS. 20 and 21. This technique improves performance of D-Flip-Flop by improving each latch performance using feedback based latches. Feedback factor of local loop of latches can be made adaptive based on process corner and temperature i.e. the feedback coefficient is adjusted automatically based on a process and temperature detection circuitry.

(64) As described hereinbefore, performance of D-Flip-Flop is improved by an always active (ON) negative feedback and individual latches are also improved by always active (ON) negative feedbacks. Negative feedback across D-Flip-Flop mitigates timing errors which is caused by RC delay at the input of D-Flip-Flop. Similarly, latches are also improved. The difference between these two feedbacks are, feedback based flip-flops is discrete time in nature and negative feedback based latches are continuous time in nature. Individually, these improve speed by 35% and 25% respectively and combination of these two types of feedback provides 45% improvement in speed while consuming 18.75% power and 35% area with respect to conventional D-Flip-Flop. Timing errors are also corrected so efficiently that it creates distributed equalization in communication links and helps to relax requirement of equalizers using negative feedbacks.

(65) While the present invention has been described with respect to certain embodiments, it will be apparent to those skilled in the art that various changes and modification may be made without departing from the scope of the invention as defined in the following claims.