Low power DC-DC converter

Abstract

A DC-DC converter comprises an oscillator and a charge pump, to ensure operation at low voltage. The oscillator comprises one or more source degenerated transistors comprising a degeneration impedance located between a source of the transistor and a ground connection. The degeneration impedance comprises an inductor and a capacitor. Also provided is an energy harvesting device comprising such a DC-DC converter.

Claims

1. A DC-DC converter comprising an oscillator with a charge pump wherein the oscillator comprises one or more source degenerated transistors, wherein each transistor comprises a degeneration impedance located between a source of the transistor and a ground connection, wherein the degeneration impedance comprises an inductor and a capacitor.

2. The DC-DC converter of claim 1, being a boost converter.

3. The DC-DC converter of claim 1, wherein the oscillator is a low voltage oscillator.

4. The DC-DC converter of claim 1, wherein the oscillator is a differential oscillator.

5. The DC-DC converter of claim 1, wherein the charge pump comprises a plurality of charge pump stages.

6. An energy harvesting device comprising a DC-DC converter that includes an oscillator with a charge pump wherein the oscillator comprises one or more source degenerated transistors, wherein each transistor comprises a degeneration impedance located between a source of the transistor and a ground connection, wherein the degeneration impedance comprises an inductor and a capacitor.

7. The energy harvesting device of claim 6, wherein the DC-DC converter is a boost converter.

8. The energy harvesting device of claim 6, wherein the oscillator is a low voltage oscillator.

9. The energy harvesting device of claim 6, wherein the oscillator is a differential oscillator.

10. The energy harvesting device of claim 6, wherein the charge pump comprises a plurality of charge pump stages.

11. A method of DC-DC conversion comprising the step of: providing an oscillator with a charge pump wherein the oscillator comprises one or more source degenerated transistors, wherein each transistor comprises a degeneration impedance located between a source of the transistor and a ground connection, wherein the degeneration impedance comprises an inductor and a capacitor.

12. The method of claim 11, being a boost conversion.

13. The method of claim 11, wherein the oscillator is a low voltage oscillator.

14. The method of claim 11, wherein the oscillator is a differential oscillator.

15. The method of claim 11, wherein the charge pump comprises a plurality of charge pump stages.

16. A method of harvesting energy comprising the step of: providing a DC-DC converter that includes an oscillator with a charge pump wherein the oscillator comprises one or more source degenerated transistors, wherein each transistor comprises a degeneration impedance located between a source of the transistor and a ground connection, wherein the degeneration impedance comprises an inductor and a capacitor.

17. The method claim 16, wherein the DC-DC converter is a boost converter.

18. The method of claim 16, wherein the oscillator is a low voltage oscillator.

19. The method of claim 16, wherein the oscillator is a differential oscillator.

20. The method of claim 16, wherein the charge pump comprises a plurality of charge pump stages.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) According to a further aspect of the disclosure there is provided a DC-DC converter substantially as herein described with reference to FIGS. 1-5; and with reference to FIGS. 6-13.

(2) The disclosure will be described, by way of example only, with reference to the accompanying drawings, in which:

(3) FIG. 1 shows a DC-DC converter according to an embodiment of the disclosure;

(4) FIG. 2 shows a low voltage differential oscillator which may form part of the converter of FIG. 1;

(5) FIG. 3 shows out of phase clock signals CLK and CLK.sub. generated by the oscillator of FIG. 2;

(6) FIG. 4 shows a charge pump stage which may form part of the converter of FIG. 1;

(7) FIG. 5 shows a circuit architecture of a DC-DC converter;

(8) FIG. 6 shows an example system architecture of a body sensor node;

(9) FIG. 7 shows a die photograph of a DC-DC converter according to an embodiment of the disclosure;

(10) FIG. 8 shows the percentage distribution of chip samples used for testing versus a minimum input voltage;

(11) FIG. 9 shows a transient of output voltage of the DC-DC converter of FIG. 3 at 96 mV input voltage;

(12) FIG. 10 illustrates a clock voltage from generated by an oscillator of the converter of FIG. 7;

(13) FIG. 11 shows converter output voltage and the power consumption versus the input voltage;

(14) FIG. 12 shows an output voltage in steady state condition at the edge of the input voltage range; and

(15) FIG. 13 shows how a minimum supply voltage deceases by augmentation of a degeneration capacitance in an oscillator circuit.

DESCRIPTION

(16) FIG. 1 illustrates the general concept of the disclosure. A voltage V.sub.EH from an energy harvesting device is input to a DC-DC converter 100 which provides an output voltage V.sub.OUT stored at an output capacitor C.sub.LOAD for powering a device.

(17) The DC-DC converter 100 comprises an oscillator together with a charge pump. The oscillator is preferably a differential oscillator to provide a double output peak voltage. The oscillator (differential or otherwise) may also preferably be a low voltage oscillator. The charge pump may comprise a plurality of charge pump stages, which may be connected in series with the output of an earlier stage providing the input for a later stage. Each stage may operate to pump a unit of charge from its relatively lower voltage input to its relatively higher voltage output with each transition of a clock signal.

(18) As an example, the DC-DC converter 100 may step up an input voltage of 80 mV to an output voltage of 400 to 1000 mV. The output impedance may be proportional to the number of charge pump stages.

(19) FIG. 2 shows an example of a low voltage differential oscillator which may be used as part of the converter 100. It comprises a cross coupled NMOS transistors pair (M1, M2), with a degeneration impedance on the transistors' sources provided by an LC tank, and a resonant LC load on the transistors' drains.

(20) The oscillator is powered by an energy harvesting device such as a thermoelectric generator, receiving a supply voltage (usually a positive supply, VDD), which may be a few tens of millivolts, in this example 80 mV. The differential structure generates out of phase signals CLK and CLK_, as shown in FIG. 3.

(21) Source degenerations of transistors allow low voltage operation. This is demonstrated by the analytical analysis reported below. In particular FIG. 13 shows how the minimum supply voltage deceases by augmenting the degeneration capacitance C1.

(22) FIG. 4 shows an example charge pump stage which may be used as part of the converter 100. A plurality of these stages may be used, with the output OUT shown in FIG. 4 providing the input IN for another stage. The CLK peak to peak amplitude is about the double of the supply voltage (about 180 mV in this embodiment). The output voltage of the stage is roughly equal to the sum of V.sub.PK (peak to peak oscillation amplitude) and V.sub.DD (supply voltage).

(23) FIG. 5 shows an embodiment of a DC-DC converter comprising a low voltage differential oscillator and a charge pump. Two charge pump stages are illustrated but any number can be provided. The output voltage, VOUT, is given by:
V.sub.OUT=V.sub.DD+N*V.sub.PKCcp1/(Ccp1+CS)I.sub.OUT*R.sub.OUT
While
(R.sub.OUT)=N/(f*(Ccp1+Cs))

(24) Ccp1 is the capacitance included in each stage of the charge pump, Cs is the parasitic capacitance between the source of the NMOS and PMOS transistors node and the ground in the charge pump. It includes the parasitic capacitances of the terminals of each charge pump capacitor to the substrate, the parasitic capacitances of interconnection lines and the source to substrates parasitic capacitances of transistors. The parasitic capacitance is about 2.5 pF in this embodiment. N represents the number of charge pump stages.

(25) This layout has been shown to provide the following characteristics:

(26) TABLE-US-00001 V.sub.IN (mV) f.sub.CLK (MHz) V.sub.OUT (mV) 80 0.3 515 100 0.3 570 200 0.28 725 300 0.25 850 400 0.22 1000

(27) With this architecture there is no need to use an external voltage or mechanical switches to generate a start-up voltage.

(28) A body sensor node (BSN) is one example of an energy harvesting device. A BSN can be powered by a combination of energy harvested from multiple sources, for example from human body heat using a micro-Thermo-Electric Generator (TEG) and energy recovered by a RF harvester.

(29) As the TEG provides only few tens of mV at its output, it is important to provide an ultra-low power DC-DC converter able to operate at very low voltage.

(30) FIG. 6 illustrates an example system architecture of a body sensor node. The RF energy harvester comprises an antenna (which may for example be a 50- dipole-like antenna), and an RF-DC rectifying circuit. Both rectifier and antenna may work at suitable frequency bands, for example, 866.5 MHz in the European UHF RFID band. Other frequencies within this band may be used, or frequencies in other appropriate RF standards and conventions. The antenna harvests and converts into usable energy for its operation the same RF power transmitted by the reader for the sensor interrogation. The rectified DC voltage is used to power up an ultra-low power micro-controller and the RFID chip.

(31) Here, the micro-controller (controller) enables the supply of the sensor interface, samples the output of the analog front end (AFE) of the sensor, and transfers the data to a UHF RFID chip for the transmission. The analog front-end of the sensor includes a set of analog signal conditioning circuitry that uses operational amplifiers, filters providing a configurable and flexible electronics functional block, needed to interface with a variety of sensors. Any type of sensor may be used. To give one non-limiting example, the sensors may be in the healthcare domain providing significant benefits by enabling continuous monitoring, actuation, and logging of patient bio-signal data, which can help medical personnel to diagnose, prevent, and respond to various illnesses such as diabetes, asthma, and heart attacks. Such sensors may comprise (for example) motion sensors, photoplethysmographic sensors, temperature sensors, or acoustic sensors. The AFE is supplied by the energy harvested by a TEG. The TEG is intended to be used in environments with low temperature differentials (i.e., the human body in a room temperature setting). It provides an output voltage (stored in the C.sub.TEG capacitor), which in a specific embodiment is 430 mV when the temperature gradient is 40 C. However, the surrounding air presents a large thermal resistance that dramatically reduces the effective temperature gradient across the thermopiles composing the TEG, further limiting the voltage available at the TEG output. This voltage is only tens of mV, requiring a high conversion ratio DC-DC converter to generate a usable supply voltage. The output of the DC-DC converter is enabled by the micro-controller after an appropriate time in order to ensure that the voltage has reached its maximum value.

(32) FIG. 5 shows a circuit architecture of a DC-DC converter which is suitable for use with the circuit of FIG. 6 but can also be applied in any other context where a very low voltage needs to be stepped up to a useful supply voltage. The converter comprises an oscillator and a charge pump. The charge pump may comprise a plurality of stages. In this embodiment, the converter comprises an ultra-low voltage LC oscillator and a five stage charge pump. The L.sub.1, L.sub.2, L.sub.3, L.sub.4 inductors and C.sub.L2 capacitor may be provided as off-chip components if desired.

(33) As the DC-DC converter input voltage, V.sub.dd, corresponds to the oscillator supply voltage, a low voltage oscillator providing sufficiently large oscillation should be supplied in order to obtain very low voltage operation. An LC resonant circuit with cross coupled MOS transistors may be used at low voltage. As a circuit with minimum configuration, this oscillator is suitable for low voltage operation with only one MOS transistor between ground and power supply. However, if the supply voltage is lower than a MOS transistor threshold, V.sub.TH, the oscillation becomes difficult. As a consequence, to reduce the start-up voltage the ultra-low voltage oscillator shown in FIG. 5 can be used. With respect of the LC resonant circuit with cross coupled MOS transistors, the proposed oscillator has a degeneration impedance on the sources of the NMOS transistors that helps in reducing the minimum required supply voltage. This has been demonstrated by the following analytical analysis:

(34) By imposing the start-up condition (i.e. the condition required by the oscillator to start working) the following equation is obtained:

(35) $\begin{array}{cc}\frac{g_m.Math.{}_0.Math.L_1.Math.Q_1}{.Math.1+g_m.Math.\left(\frac{1}{i.Math.{}_0.Math.C_1}+i.Math.{}_0.Math.L_2\right).Math.}>1& \left(\mathrm{Eqn}1\right)\end{array}$
where g.sub.m is the transconductance of the NMOS transistors, .sub.0 is the resonance frequency of the oscillator, and Q.sub.1 is the quality factor of the L.sub.1 and L.sub.2 inductors. At the low voltage supplied to the oscillator by the external device (such as TEG) the NMOS transistors operate in weak inversion. Therefore, the transconductance of the NMOS transistors is given by:

(36) $\begin{array}{cc}{g}_m=\frac{I_s.Math.e^{\frac{V_{\mathrm{dd}}}{n.Math.V_t}}}{n.Math.V_t}& \left(\mathrm{Eqn}2\right)\end{array}$
where I.sub.s is the reverse saturation current, n is the slope factor of M.sub.1 and M.sub.2, V.sub.t is the thermal voltage, and V.sub.dd is the supply voltage.

(37) The resonance frequency, .sub.0, depends on the resonant load at the drains of M.sub.1 and M.sub.2. It is given by:

(38) $\begin{array}{cc}{}_0=\frac{1}{\sqrt{L_1.Math.\left(5.Math.{(C}_{\mathrm{cp}1}+C_{\mathrm{par}})\right)}}\frac{1}{\sqrt{L_1.Math.5.Math.C_{\mathrm{cp}1}}}& \left(\mathrm{Eqn}3\right)\end{array}$
where C.sub.par is the parasitic capacitance including the parasitic capacitances of the terminals of each charge pump capacitor to the substrate, the parasitic capacitances of interconnection lines and the pad capacitances. By combining equations (1), (2) and (3), the minimum input voltage, V.sub.dd,min, is shown to be:

(39) $\begin{array}{cc}{V}_{\mathrm{dd},\min }=n.Math.V_t.Math.\ln \left(\frac{1}{I_s.Math.\sqrt{{\left({}_0.Math.L_1.Math.Q_1\right)}^2-{\left({}_0.Math.L_2\right)}^2-\frac{1}{{\left({}_0.Math.C_1\right)}^2}+2.Math.\frac{L_2}{C_1}}}\right)& \left(\mathrm{Eqn}4\right)\end{array}$

(40) FIG. 13 shows that the Vdd,min decreases when a degenerated C1 capacitance is increased, demonstrating the source degeneration impedance helps in reducing the minimum required supply voltage.

(41) Table I reports the values of the circuit components and the values of I.sub.s, and n of M.sub.1 and M.sub.2, which have been obtained by simulations and optimizations.

(42) TABLE-US-00002 TABLE I VALUES OF THE CIRCUITS COMPONENTS AND NMOS PARAMETERS Component value L.sub.1 (mH) 3.3 C.sub.cp1 (pF) 24 Q.sub.1 270 L.sub.3 (H) 2.2 C.sub.1 (pF) 1 I.sub.s (nA) 53.4 N 1.33

(43) The circuit is symmetrical, therefore L4=L3, Ccp1=Ccp2, L1=L2 and C1=C2, and the slope factor n is common to all the transistors.

(44) According to equation 4, the resulting minimum voltage at the DC-DC converter input, V.sub.dd,min, is 91 mV. However, both I.sub.s and n undergo the process spread. Table II reports the values of I.sub.s and n at the process corners and the respective values of V.sub.dd,min obtained by equation (4).

(45) TABLE-US-00003 TABLE II VALUES OF V.sub.DD,MIN AT THE PROCESS CORNERS Process corner I.sub.s (nA) n V.sub.dd,min (mV) typical 53.4 1.33 91 fast 81.3 1.23 72 slow 24.5 1.41 124

(46) Both I.sub.s and n have a strong dependency on the temperature. However, the sensor node is supposed to work close to the human body. Therefore, the working temperature is kept around 36 C. with limited variations around this value. As a consequence, the dependency of the start-up voltage on the temperature can be waived.

(47) The peak-to-peak oscillation amplitude, V.sub.CLK, is the double of the supply voltage, i.e.:
V.sub.CLK=2.Math.V.sub.dd (Eqn 5)

(48) The oscillator provides the clock driving the C.sub.cp1 and C.sub.cp2 capacitances of each stage of the charge pump.

(49) The output voltage, V.sub.out, of the charge pump with k stages is given by:

(50) $\begin{array}{cc}{V}_{\mathrm{out}}=V_{\mathrm{dd}}.Math.\left({\left(1-\mathrm{.Math.}\right)}^{k+1}+2.Math.\frac{C_{\mathrm{cp}1}}{C_{\mathrm{cp}1}+C_{\mathrm{par}}}k.Math.\underset{j=1}{\overset{k}{.Math.}}{\left(1-\mathrm{.Math.}\right)}^{k+1-j}\right)& \left(\mathrm{Eqn}6\right)\end{array}$
where is the charging error due to the finite resistances of the MOS transistors. The charging error, , is calculated as follows:

(51) $\begin{array}{cc}\mathrm{.Math.}=e^{\frac{T_{\mathrm{CLK}}}{4.Math..Math.R_{\mathrm{SW}}.Math.C_{\mathrm{cp}1}}}1-\frac{\sqrt{L1.Math.k}}{2.Math.R_{\mathrm{SW}}.Math.\sqrt{C_{\mathrm{cp}1}}}& \left(\mathrm{Eqn}7\right)\end{array}$
where R.sub.SW is the resistance of the MOS transistors and T.sub.CLK is the clock period. According to equation 7, in order to reduce the charging error , R.sub.SW and C.sub.cp1 should be designed as small as possible, while L.sub.1 and k should be designed as large as possible. However R.sub.SW is limited by the reduce supplied voltage, C.sub.p1 has a lower limit due to the parasitic capacitances C.sub.par, while augmenting the number of stages k increases the power consumption. Therefore, it may be chosen to have a very large L.sub.1 and L.sub.2 inductors by using off-chip components.

(52) The number of stages k has been calculated in order to reach a 500 mV output voltage starting from the minimum input voltage required by the oscillator (91 mV). Therefore a conversion ratio higher than 5 is required. By adopting a 5 stages charge pump an ideal gain of 11 can be reached. However, due to the losses caused by the parasitic capacitances and the charging error, a effective convertion ratio slightly higher than 5 is obtained by simulations.

(53) An embodiment of the DC-DC converter has been designed in a 0.18 m CMOS technology. FIG. 7 shows the die photograph. Chip sizes are 1130 m533 m. The output capacitance comprises the parallel of the integrated capacitance C.sub.L1 of 100 pF (implemented by an NMOS cap), and an off chip capacitance C.sub.L2 of 1 F.

(54) Ten chip samples were available for measurements. FIG. 8 shows the percentage distribution of the chip samples versus the minimum input voltage. The 60% of the available samples have a minimum input voltage in the 90 mV-99 mV range, while the mean value is 96 mV. This value is close to the calculated one. Measurements here reported are relative to the sample with a minimum input voltage equal to 96 mV as the mean one.

(55) FIG. 9 shows the transient of the output voltage. After about 15 s transient the output voltage reaches 500 mV at the steady state. This transient time decreases at the increasing of the input voltages. For input voltages larger than 200 mV, it is in the range of few milliseconds.

(56) FIG. 10 shows the clock voltage. The peak-to-peak clock amplitude is 195 mV.sub.pp, which is close to the double of the input voltage, as calculated by equation 5.

(57) FIG. 11 shows the output voltage (upper graph) and the power consumption (lower graph) versus the input voltage. At the increasing of input voltage, the MOS transistors of charge pump pass from sub-threshold to linear operating region, therefore the power consumption increases considerably (from 1 W at 96 mV V.sub.dd, up to 50 W at 400 mV V.sub.dd).

(58) FIG. 12 shows the output voltage in steady state condition at the edges of the input voltage range (96 mV, and 400 mV). At 96 mV V.sub.dd, the output voltage is equal to 500 mV with a 10 mV.sub.pp ripple. At 400 mV V.sub.dd, the output voltage is 1.1V, while the ripple reaches its maximum value of 70 mV.sub.pp.

(59) Output ripple can be reduced by increasing the off chip output capacitance C.sub.L2, at the cost of a slower transient of the output voltage to reach the steady state value.

(60) The DC-DC converter of the present disclosure has better minimum input voltage and power consumption than existing solutions, and furthermore does not need mechanical switching or pre-charged external batteries to start-up the oscillator.

(61) An ultra-low power DC-DC converter has been disclosed. One example use case is the embedding into body sensor nodes. The converter may be used to step-up the voltage at the output of a TEG. The specific example disclosed herein features a 96 mV minimum input voltage while consuming 1 W. The output voltage ranges between 0.5V and 1.1V. These results compare favourably as compared with existing solutions in terms of minimum input voltage and power consumption.

(62) Various improvements and modifications can be made to the above without departing from the scope of the disclosure.