VDS equalizer offset compensation for a current sense circuit

Abstract

A current sense circuit for a pass transistor is described. The current sense circuit comprises a sense transistor, a differential amplifier comprising a differential input and a differential output, and a differential difference amplifier, referred to as DD amplifier, comprising a main differential input, an auxiliary differential input and an output; wherein the differential output of the differential amplifier is coupled to the auxiliary differential input of the DD amplifier; wherein the output port of the pass transistor is coupled to a first port of the main differential input and wherein the output port of the sense transistor is coupled to a second port of the main differential input. The output of the DD amplifier is used to control a voltage drop across the sense transistor and the pass transistor.

Claims

1. A current sense circuit for a pass transistor, wherein the current sense circuit comprises, a sense transistor having an input port that is coupled to an input port of the pass transistor and having a gate that is coupled to a gate of the pass transistor; a differential amplifier comprising a differential input and a differential output; wherein an output port of the pass transistor is coupled to a first port of the differential input and wherein an output port of the sense transistor is coupled to a second port of the differential input; and a differential difference amplifier, referred to as DD amplifier, comprising a main differential input, an auxiliary differential input and an output; wherein the differential output of the differential amplifier is coupled to the auxiliary differential input of the DD amplifier; wherein the output port of the pass transistor is coupled to a first port of the main differential input and wherein the output port of the sense transistor is coupled to a second port of the main differential input; wherein the output of the DD amplifier is used to control a voltage drop across the sense transistor and the pass transistor; and an output transistor which is controlled by the output of the DD amplifier; wherein an output port of the output transistor is coupled to the output port of the sense transistor; and wherein a sense current through the output transistor provides an indication of a current through the pass transistor, wherein the sense current through the output transistor is fed back to the gates of the pass transistor and of the sense transistor to control the voltage drop across the sense transistor and the pass transistor.

2. The current sense circuit of claim 1, further comprising a current source configured to set a control current; wherein a voltage level at the gates of the pass transistor and of the sense transistor is dependent on the control current.

3. The current sense circuit of any of claim 1, further comprising one or more current mirrors for mirroring the sense current to the gates of the pass transistor and of the sense transistor.

4. The current sense circuit of claim 1, wherein the differential amplifier comprises an offset compensated differential amplifier or an amplifier with a relatively low offset.

5. The current sense circuit of claim 1, wherein the differential amplifier comprises an analog-to-digital converter configured to derive a digital signal from the voltages at the differential input of the differential amplifier; a digital filter configured to filter the digital signal, to provide a filtered signal; and a digital-to-analog converter configured to derive voltages at the differential output of the differential amplifier based on the filtered signal.

6. The current sense circuit of claim 5, wherein the differential amplifier further comprises a dithering unit configured to apply a dither signal to the voltages at the differential input of the differential amplifier.

7. The current sense circuit of claim 1, wherein the differential amplifier comprises a first sub-amplifier and a second sub-amplifier that are arranged in parallel with regards to the differential input and the differential output of the differential amplifier.

8. The current sense circuit of claim 7, wherein the first sub-amplifier and the second sub-amplifier are operated in an auto-zero phase and in an amplification phase in an alternating manner.

9. The current sense circuit of claim 8, wherein the first sub-amplifier and the second sub-amplifier are operated in the auto-zero phase in a mutually exclusive manner, such that the first sub-amplifier is in the amplification phase, when the second sub-amplifier is in the auto-zero phase, and such that the second sub-amplifier is in the amplification phase, when the first sub-amplifier is in the auto-zero phase.

10. The current sense circuit of claim 8, wherein the differential amplifier comprises auto-zero capacitors for the first sub-amplifier; the auto-zero capacitors are arranged in series with an input port of the first sub-amplifier, when the first sub-amplifier is in the auto-zero phase; and the auto-zero capacitors couple the input port of the first sub-amplifier to ground, when the first sub-amplifier is in the amplification phase.

11. The current sense circuit of claim 8, wherein the alternation of the auto-zero phase and of the amplification phase is controlled using a clock signal.

12. The current sense circuit of claim 1, wherein the pass transistor, the sense transistor and the output transistor are metal oxide semiconductor transistors; the input port of the pass transistor and of the sense transistor is a drain or a source; and the output port of the pass transistor, of the sense transistor and of the output transistor is a source or a drain.

13. A method for providing a sense current which is indicative of a current through a pass transistor, the method comprising, arranging a sense transistor such that an input port of the sense transistor is coupled to an input port of the pass transistor and such that a gate of the sense transistor is coupled to a gate of the pass transistor; amplifying a delta voltage corresponding to a difference between a pass voltage at an output port of the pass transistor and a sense voltage at an output port of the sense transistor to provide a second delta voltage; amplifying the delta voltage and the second delta voltage using respective differential input ports of a differential difference amplifier, referred to as DD amplifier, to provide a differential output voltage; using an output of the DD amplifier to control a voltage drop across the sense transistor and the pass transistor; and providing an output transistor which is controlled by the output of the DD amplifier, wherein an output port of the output transistor is coupled to the output port of the sense transistor; and wherein a sense current through the output transistor provides an indication of a current through the pass transistor wherein the sense current through the output transistor is fed back to the gates of the pass transistor and of the sense transistor to control the voltage drop across the sense transistor and the pass transistor.

14. The method according to claim 13, further comprising the step of: setting a control current by a current source; wherein a voltage level at the gates of the pass transistor and of the sense transistor is dependent on the control current.

15. The method according to claim 13, further comprising the step of: mirroring by one or more current mirrors the sense current to the gates of the pass transistor and of the sense transistor.

16. The method according to claim 13, wherein the differential amplifier comprises an offset compensated differential amplifier or an amplifier with a relatively low offset.

17. The method according to claim 16, wherein using the differential amplifier comprises the steps of: deriving with an analog-to-digital converter a digital signal from the voltages at the differential input of the differential amplifier; filtering with a digital filter the digital signal, to provide a filtered signal; and deriving with a digital-to-analog converter voltages at the differential output of the differential amplifier based on the filtered signal.

18. The method according to claim 17, wherein using the differential amplifier further comprising the step of: applying with a dithering unit a dither signal to the voltages at the differential input of the differential amplifier.

19. The method according to claim 13, wherein the differential amplifier comprises a first sub-amplifier and a second sub-amplifier that are arranged in parallel with regards to the differential input and the differential output of the differential amplifier.

20. The method according to claim 19, wherein the first sub-amplifier and the second sub-amplifier are operated in an auto-zero phase and in an amplification phase in an alternating manner.

21. The method according to claim 20, wherein the first sub-amplifier and the second sub-amplifier are operated in the auto-zero phase in a mutually exclusive manner, such that the first sub-amplifier is in the amplification phase, when the second sub-amplifier is in the auto-zero phase, and such that the second sub-amplifier is in the amplification phase, when the first sub-amplifier is in the auto-zero phase.

22. The method according to claim 20, wherein the differential amplifier comprises auto-zero capacitors for the first sub-amplifier; the auto-zero capacitors are arranged in series with an input port of the first sub-amplifier, when the first sub-amplifier is in the auto-zero phase; and the auto-zero capacitors couple the input port of the first sub-amplifier to ground, when the first sub-amplifier is in the amplification phase.

23. The method according to claim 20, wherein the alternation of the auto-zero phase and of the amplification phase is controlled using a clock signal.

24. The method according to claim 13, wherein the pass transistor, the sense transistor and the output transistor are metal oxide semiconductor transistors; the input port of the pass transistor and of the sense transistor is a drain or a source; and the output port of the pass transistor, of the sense transistor and of the output transistor is a source or a drain.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention is explained below in an exemplary manner with reference to the accompanying drawings, wherein

(2) FIG. 1a shows a block diagram of an example current sense/current regulation circuit;

(3) FIG. 1b shows a circuit diagram of an example current sense/current regulation circuit;

(4) FIG. 2 shows a circuit diagram of an example current sense/current regulation circuit with offset compensation;

(5) FIG. 3 shows a circuit diagram of a multi auto-zero amplifier;

(6) FIGS. 4a and 4b show simulation results;

(7) FIG. 5 shows a circuit diagram of a mixed signal sigma delta loop;

(8) FIG. 6 shows a flow chart of a method for sensing the current through a pass transistor; and

(9) FIGS. 7a and 7b show circuit diagrams of example current sense circuit for a battery switch architecture.

DESCRIPTION

(10) Power management functions, e.g. for battery charging, which make use of a pass transistor typically comprise a current sense circuit to sense and/or control the actual current sourced or sunk by external components. Integrated current sensing may be performed by means of a sense transistor which is a down-scaled copy of the pass transistor.

(11) In order to reduce the charging time, battery chargers may require relatively high charging currents (of several Amperes). In this context, the voltage drop at the pass transistor (e.g. the V.sub.DS of a MOS transistor) is pushed as low as possible, in order to increase the system efficiency of the pass transistor. As a result of this, there is a need for implementing the current sense with a reduced offset voltage. Since in normal operation, the pass transistor is typically pushed into a deep linear region, the matching between the pass current (through the pass transistor) and the sense current (through the sense transistor) is strongly dependent on the matching of the voltages across the pass transistor and the sense transistor. In particular a mismatch in V.sub.DS of a pass transistor and of a sense transistor directly impacts a mismatch in the pass current and in the sense current.

(12) The current I.sub.D through a MOS transistor is given by
I.sub.D=C.sub.OXW/L(V.sub.GSV.sub.THV.sub.DS/2)V.sub.DS.

(13) This can be simplified with V.sub.GSV.sub.TH>>V.sub.DS as
I.sub.D=C.sub.OXW/L(V.sub.GSV.sub.TH)V.sub.DS.

(14) In the above formulas, V.sub.GS is the gate-source voltage at a MOS transistor, V.sub.TH is the threshold voltage of the MOS transistor, W/L is the width-to-length ratio of the MOS transistor, C.sub.OX is the capacitance of the oxide layer of the MOS transistor and is the charge-carrier effective mobility.

(15) From the above formulas, it can be seen that the drain-source current I.sub.D through a MOS transistor is directly dependant on the drain-source voltage V.sub.DS across the MOS transistor. As a result of this, it is typically important to match the drain-source voltages across the pass transistor and across the sense transistor, in order to ensure that the sense current provides an accurate indication of the pass current.

(16) A block diagram of an example current sense and current control circuit 100 is illustrated in FIG. 1a. FIG. 1a shows the pass transistor 101 which is implemented as a p-type MOS transistor with the source being coupled (directly) to a supply voltage 121 and with the drain providing an output voltage 122 (e.g. a battery voltage for charging a battery). The pass transistor 101 is controlled via a gate. The sense transistor 111 is also implemented as a p-type MOS transistor which exhibits a width-to-length ratio that is typically smaller than the width-to-length ratio of the pass transistor 101 by a factor of 100, 1000 or more. The drain of the sense transistor 111 is also coupled (directly) to the supply voltage 121 and the gate of the sense transistor 111 is (directly) coupled to the gate of the pass transistor 101. The gates of the sense transistor 111 and of the pass transistor 101 are controlled using a control circuit 131 (e.g. a power management circuit).

(17) The current sense and current control circuit 100 comprises a differential amplifier 102 which is configured to amplify a delta voltage at the input of the differential amplifier 102. The delta voltage corresponds to the difference between the output voltage 122 of the pass transistor 101 and the output voltage 124 of the sense transistor 111. The amplified delta voltage at the output of the amplifier 102 is fed back to one of the differential inputs of the differential amplifier 102 (and to the source of the sense transistor 111) via the output transistor 103. As a result of this, the output voltage 124 of the sense transistor 111 is regulated to be equal to the output voltage 122 of the pass transistor 101, thereby matching the V.sub.DS across the pass transistor 101 and the V.sub.DS across the sense transistor 111. The sense current 123 is provided by the output transistor 103 and via current readout circuitry 132.

(18) FIG. 1b shows a circuit diagram of a current sense and current control circuit 100. The circuit 100 comprises a first current mirror 104, 105 and a second current mirror 106, 107 for copying the sense current 123 to the gates of the sense transistor 111 and the pass transistor 101. The copied sense current is offset with a control current that is set by a current source 108, in order to control the gates of the sense transistor 111 and the pass transistor 101 and in order to set the current through the pass transistor 101 in accordance to the control current.

(19) Operational amplifiers 102 typically exhibit an amplifier offset. This amplifier offset affects the precision of the sense current 123. Chopping or Correlated Double Sampling techniques may be applied to compensate such an amplifier offset. However, these techniques are difficult to apply in case of single ended differential amplifiers (as shown in FIG. 1a). Furthermore, chopping requires output offset ripple filtering which increases the complexity and/or which may cause disturbances at the chopping clock frequency that may affect the regulated output current. In addition, Correlated Double Sampling techniques suffer from high frequency aliasing and require a blind phase (i.e. offset sampling phase) implementing a sampled data regulated current.

(20) The differential amplifier 102 should ideally have zero offset in order to improve the pass transistor 101 and the sense transistor 111 current matching. Furthermore, the main sensing/regulation loop should be continuous instead of having a discrete time topology. In addition, the current sense and current control circuit 100 should be robust to the aliasing of high frequency disturbances such that a residual offset of the differential amplifier 102 is not affected by injected noise.

(21) FIG. 2 shows a current sense and current control circuit 200 which comprises a Differential Difference Amplifier (DDA or DD amplifier) 201 that may be used in addition to a differential amplifier 202. The DDA 201 comprises two differential control ports 204 (the main port) and 205 (the auxiliary port). The main port 204 may be used to replace the differential amplifier 102 of FIG. 1b. The DDA offset 203 of this path is also shown in FIG. 2.

(22) The auxiliary port 205 is coupled to a fully differential amplifier 202 which determines the main DC gain and offset of the current sensing/regulation loop. Apart from finite gain errors, the DDA offset 203 at the main port 204 may be compensated by the differential amplifier 202 which is coupled to the auxiliary port 205. A.sub.1 is the gain of the differential amplifier 202 and A.sub.main and A.sub.aux are the input-output voltage gains for the DDA 201 with respect to its main port 204 and its auxiliary port 205, respectively. The residual offset is then given by
Vos.sub.TOT=V.sub.OFFA.sub.main/(A.sub.AUXA.sub.1)+Vos.sub.AMP,
where V.sub.OFF is the DDA offset 203 and where Vos.sub.AMP is the differential amplifier offset 206 of the differential amplifier 202. If the voltage gains of the main port 204 and of the auxiliary port 205 are matched (i.e. A.sub.main=A.sub.aux), the main amplifier offset can be expressed as:
Vos.sub.TOT=V.sub.OFF/A.sub.1+Vos.sub.AMP.

(23) Hence, the DDA offset 203 can be reduced by the gain A.sub.1 of the differential amplifier 202. The differential amplifier offset 206 may be reduced by using e.g. an auto-zeroed differential amplifier 202.

(24) The sensing/regulation loop of the circuit 200 of FIG. 2 is such that, if the delta voltage at the main port 204 and the delta voltage at the auxiliary port 205 are exactly the same and if the differential amplifier 202 and the DDA 201 have an infinite gain, and in case of a systematic offset 203 at the main port 204 of the DDA 201, the differential amplifier 202 loop reacts by showing the same DC amplitude of the DDA offset 203 but with opposite sign at the auxiliary port 205 of the DDA 201, thereby compensating the DDA offset 203.

(25) The fully differential amplifier 202 can make use of discrete time auto-zero topologies. The advantage of the compensation loop of FIG. 2 is that the entire compensation loop it fully differential. A further advantage of using the arrangement of FIG. 2 is that the overall V.sub.DS equalizer amplifier gain of the differential amplifier 202 in combination with the DDA 201 remains constant, even if the differential amplifier 202 is implemented by two matched amplifiers working alternately (as outlined in the context of FIG. 3). The total amplifier gain is given by:
A.sub.TOT=A.sub.MAIN+A.sub.1A.sub.AUX.

(26) As indicated above, the differential amplifier 202 may be implemented by two amplifiers that work during two non-overlapping phases. During a first phase, the first amplifier may compensate its offset (i.e. the first amplifier may be in its auto-zeroing phase) and the other amplifier may be working as an amplifier within the sensing loop (i.e. the other amplifier may be in its amplification phase). During a second phase, the situation may be vice versa. By making use of a differential amplifier 202 which comprises multiple amplifiers that are operated in different phases, the circuit 200 becomes robust against noise. It should be noted, however, that other offset compensation schemes adopting an auto-zero topology may be used to compensate the differential amplifier offset 206.

(27) FIG. 3 shows a fully differential amplifier 202 which comprises two sub-amplifiers 310, 320 that are operated alternately in two different phases, an auto-zero phase and an amplification phase. The phases may be controlled using a master clock signal 300 from which a first clock signal 301 and a second clock signal 302 for controlling first switches 311, 321 and second switches 312, 322 of the sub-amplifiers 310, 320, respectively, may be derived. In particular, the first switches 311, 321 may be controlled using the first clock signal 301 and the second switches 312, 322 may be controlled using the second clock signal 302. The switches 311, 321, 312, 322 are closed, when the respective clock signal 301, 302 is high. On the other hand, the switches 311, 321, 312, 322 are opened, when the respective clock signal 301, 302 is low. It can be seen that the clock signals 301, 302 have non-overlapping phases, when the clock signals 301, 302 are high, thereby ensuring that the first switches 311, 321 and the second switches 321, 322 are closed in a mutually exclusive manner.

(28) When the first clock signal 301 is high, the auto-zero capacitors 323 of the second sub-amplifier 320 are charged, i.e. the second sub-amplifier 320 is within the auto-zero phase. On the other hand, the auto-zero capacitors 313 of the first sub-amplifier 310 are used to compensate an offset of the first sub-amplifier 310 while the first sub-amplifier 310 is operated in the amplification phase. When the second clock signal 302 is high, the situation is vice versa.

(29) It should be noted that the multi auto-zeroed amplifier 202 may comprise more than two sub-amplifiers 310, 320 which are operated in different phases. This may be advantageous for optimizing the power consumption.

(30) FIG. 4a shows a simulation result for the operation of a current sense and regulation circuit 200 which comprises a differential amplifier 202 that comprises only a single auto-zeroed sub-amplifier. In this case, the output of the differential amplifier 202 is kept on hold during the auto-zero compensation phase of the sub-amplifier. FIG. 4a shows the clock signal 300, 400 (as a function of time) which is applied to the differential amplifier 202 for alternating the sub-amplifier between the auto-zero compensation phase and the amplification phase. Furthermore, FIG. 4a shows the noise superimposed onto the supply voltage 122, 422. The noise may be due to a switched power converter that is used to generate the supply voltage 122, 422, therefore exhibiting noise with a frequency that corresponds to the commutation cycle rate of the power converter. In addition, FIG. 4a shows the delta voltage 405 at the auxiliary port 205 of the DDA 201, i.e. at the output of the differential amplifier 202. The sampling errors that are caused by aliasing which is due to the random phase difference between the auto-zero sampling clock 400 and the noise superimposed to the supply voltage 405 can clearly be seen.

(31) FIG. 4b shows the situation for a differential amplifier 202 which comprises two sub-amplifiers 310, 320 that are operated in an alternating manner. The output 405 of the differential amplifier 202 exhibits a distorted response depending on the moment at which the clock signal 400 toggles. However, the output 405 of the differential amplifier 202 recovers to the correct values after a few commutation cycles of the switched power converter that provides the supply voltage 122, 422.

(32) As such, a current sensing/regulation circuit 200 is described which comprises a V.sub.DS equalizer that comprises a multi auto-zeroed differential amplifier 202 with a plurality of sub-amplifiers 310, 320. The use of a plurality of sub-amplifiers 310, 320 allows implementing a continuous and stable sensing/regulation loop, while at the same time providing offset compensation. As a result of this, accurate and stable current sensing/regulation may be provided. Stability and offset compensation may be further improved by using a DDA 201 in addition (or alternatively) to a multi auto-zeroed differential amplifier 202.

(33) In particular, the use of a multi auto-zeroed amplifier 202 in conjunction with a DDA 201 allows for a continuous time regulation of the pass current with a high immunity to disturbances. The advantage of implementing a differential amplifier 202 with non-overlapped auto-zeroed sub-amplifiers 310, 320 that work in time division, allows removing errors that are caused by the aliasing of high frequency disturbances (e.g. at the commutation cycle rate of the power converter that provides the supply voltage 122). Another advantage is that the main regulation/sense loop gain remains constant, thereby avoiding pass current ripple at the auto-zero frequency.

(34) FIG. 5 shows a current sensing/regulation circuit 200 which makes use of a sigma delta ADC (analog-to-digital converter) 502 and a DAC (digital-to-analog converter) 505 within the control loop. Such a control loop provides increased flexibility as it allows changing the response bandwidth of a digital low pass filter 503 depending on the operation mode. Furthermore, a current offset 504 may be used. In addition, the offset may be measured and its value may be stored within a register. Subsequently, the sensing components may be shut down. The control loop of FIG. 5 also comprises an RC filter 507 for anti-aliasing. In view of the fact that the sigma delta ADC 502 typically cannot read a DC value, a relatively small dithering signal 501 with an average value equal to zero may be added at the input of the sigma delta ADC 502. In addition, the DAC 505 may be configured to apply a gain 506.

(35) FIG. 6 shows a flow chart of an example method 600 for providing a sense current 123 which is indicative of a current through a pass transistor 101. The method 600 comprises arranging 601 a sense transistor 111 such that an input port (e.g. a source) of the sense transistor 111 is coupled to an input port (e.g. a source) of the pass transistor 101 and such that a control port (e.g. a gate) of the sense transistor 111 is coupled to a control port (e.g. a gate) of the pass transistor 101. Furthermore, the method 600 comprises amplifying 602 a delta voltage corresponding to a difference between a pass voltage 122 at an output port (e.g. a drain) of the pass transistor 101 and a sense voltage 124 at an output port (e.g. a drain) of the sense transistor 124 to provide a second delta voltage.

(36) The method 600 further comprises amplifying 603 the delta voltage and the second delta voltage using respective differential input ports of a differential difference amplifier, referred to as DD amplifier, 201 to provide a differential output voltage. In addition, the method 600 comprises coupling 604 an output port (e.g. a drain) of an output transistor 103 to the output port (e.g. a drain) of the sense transistor 111. Furthermore, the method 600 comprises controlling 605 the output transistor 103 using the differential output voltage, wherein the sense current 123 corresponds to the current through the output transistor 103.

(37) FIGS. 7a and 7b show how the offset compensation/auto-zeroing may be used within a battery switch architecture 700. In both circuit diagrams a constant current charging of a battery 701 is implemented. The current for charging the battery 701 is provided at the output of a DC-DC power converter 702, 703, 704 (e.g. a buck converter), which comprises a converter network 702, an inductor 703 and an output capacitor 704. The current for charging the battery is set by the control current source 708. In FIG. 7a, the control current source 708 provides a control current directly to the output of the sense transistor 111, in order to set the current through the sense transistor 111 (and in order to thereby set the current through the pass transistor 101). In FIG. 7b, the control current source 708 provides the control current to the output of the sense transistor 111 via a current mirror 104, 105 and via the output transistor 103.

(38) The pass transistor 101 for a control loop for the power converter 702, 703, 704, and the control loop operates the power converter 702, 703, 704 to set the supply voltage 121 such that the desired current flows through the pass transistor 101. In both architectures, the output voltage 124 of the sense transistor 111 and the output voltage 122 of the pass transistor 101 are maintained at the same voltage using the precise auto-zeroing provided by the differential amplifier 202 and the DD amplifier 201.

(39) In the circuit diagrams of FIGS. 7a and 7b, the gates of the pass transistor 101 and of the sense transistor 111 are tied to ground. As a result of this, the V.sub.DS of both transistors 101, 111 is typically substantially lower compared to a linear charger as illustrated in FIG. 2. Hence offset compensation is even more critical in the case of FIGS. 7a and 7b.

(40) It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiment outlined in the present document are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.