QUANTUM ANNEALING DEBUGGING SYSTEMS AND METHODS

Abstract

Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.

Claims

1. A method of operation of a control system communicatively coupled to a quantum processor, the control system comprising at least one processor and at least one nontransitory processor-readable medium that stores at least one of processor-executable instructions or data, the method comprising: determining, by the control system, an annealing evolution schedule to perform a quantum annealing evolution computation on a problem representation in a quantum processor; causing, by the control system, a start of at least a first iteration of an annealing evolution of the quantum processor with the problem representation in accordance with the annealing evolution schedule; and at least once during a performance of the first iteration of the annealing evolution: determining, by the control system, at least one characteristic of the quantum processor at at least a first point in time between the start of the first iteration of the annealing evolution and before a completion of the annealing evolution schedule; and causing, by the control system, at least one of: a reinitializing of the annealing evolution, a reversal of the annealing evolution from the first point in time at which the at least characteristic was determined, or a continuing of the annealing evolution from the first point in time at which the at least characteristic was determined.

2. The method of claim 1, further comprising: causing, by the control system, at least one interruption of the annealing evolution of the quantum processor before completion of the annealing evolution schedule.

3. The method of claim 2 wherein the determining at least one characteristic of the quantum processor occurs during the interrupting of the annealing evolution of the quantum processor before completion of the annealing evolution schedule.

4. The method of claim 1, further comprising: causing, by the control system, a ramping of the annealing evolution of at least a portion of the quantum processor before completion of the annealing evolution schedule, wherein the determining at least one characteristic of the quantum processor occurs concurrently with or immediately following the ramping.

5. The method of claim 4, further comprising: causing, by the control system, a pausing of the annealing evolution immediately prior to the ramping.

6. The method of claim 4 wherein the causing of the ramping the annealing evolution of at least the portion of the quantum processor occurs without causing a pausing the annealing evolution immediately prior to the ramping.

7. The method of claim 1 wherein determining at least one characteristic comprises reading out a state of each of a number of qubits.

8. The method of claim 1 wherein determining at least one characteristic comprises reading out a state of each of a number of qubits via a number of weakly coupled detectors.

9. The method of claim 1 wherein determining at least one characteristic comprises continually reading out a state of each of a number of qubits via a number of weakly coupled detectors during the annealing evolution.

10. The method of claim 1, further comprising: autonomously comparing, by the control system, the determined at least one characteristic of the quantum processor to a set of user specified dynamics.

11. The method of claim 1, further comprising: autonomously identifying, by the control system, a deviation from a set of user specified dynamics; and producing an alert, by the control system, in response to identification of a deviation from the set of user specified dynamics that exceeds a threshold deviation.

12. The method of claim 1, further comprising: autonomously identifying, by the control system, an occurrence of an event based at least in part on the determined at least one characteristic of the quantum processor; and producing an alert, by the control system, in response to identification of the event.

13. The method of any of claim 10, further comprising: receiving, by the control system, a user specified expected behavior expected to occur during at least one iteration of the annealing evolution, the user specified expected behavior specified as at least one mathematical model.

14. The method of claim 1, further comprising: providing to an end user device, via the control system, a representation of a behavior during a portion of the annealing evolution of the quantum processor, subsequent to performance of the portion of the annealing evolution.

15. The method of claim 14, further comprising: transforming, via the control system, a set of low level machine state information into a set of higher level representation information.

16. The method of claim 1, further comprising: repeatedly: determining, by the control system, at least one characteristic of the quantum processor at a number of subsequent points in time between the first point in time in the annealing evolution schedule and before the completion of the annealing evolution schedule; and causing, by the control system, at least one of: a reinitializing of the annealing evolution, a reversal of the annealing evolution from the subsequent points in time at which the at least characteristic was determined, or a continuing of the annealing evolution from the subsequent points in time at which the at least characteristic was determined.

17. A system, comprising: a quantum processor; a control system communicatively coupled to the quantum processor, the control system comprising at least one processor and at least one nontransitory processor-readable medium that stores at least one of processor-executable instructions or data which, when executed by the at least one processor, causes the at least one processor to: determine an annealing evolution schedule to perform a quantum annealing evolution computation on a problem representation in a quantum processor; start at least a first iteration of an annealing evolution of the quantum processor with the problem representation in accordance with the annealing evolution schedule; and at least once during performance of the first iteration of the annealing evolution, determine at least one characteristic of the quantum processor at at least a first point in time between the start of the first iteration of the annealing evolution and before a completion of the annealing evolution schedule; and at least one of: a initialization of the annealing evolution, a reversal of the annealing evolution from the first point in time at which the at least one characteristic was determined, or a continuation of the annealing evolution from the first point in time at which the at least characteristic was determined.

18. (canceled)

19. A method of operation of a control system communicatively coupled to a quantum processor, the control system comprising at least one processor and at least one nontransitory processor-readable medium that stores at least one of processor-executable instructions or data, the method comprising: receiving, by the control system, a user specified expected behavior expected to occur during at least one iteration of an annealing evolution; starting at least a first iteration of the annealing evolution of the quantum processor with a first representation of a problem; at one or more times during a performance of the first iteration of the annealing evolution: determining, by the control system, at least one characteristic of the quantum processor at at least a first point in time between the start of the first iteration of the annealing evolution and before a completion of an annealing evolution schedule; and determining, by the control system, whether a performance of the annealing evolution matches a specified performance based at least on part of the determined at least one characteristic of the quantum processor.

20. (canceled)

21. (canceled)

22. The method of claim 19 wherein determining whether a performance of the annealing evolution matches a specified performance includes autonomously identifying, by the control system, a deviation from a set of user specified dynamics.

23. The method of claim 22, further comprising: producing an alert, by the control system, in response to identification of a deviation from the set of user specified dynamics that exceeds a threshold deviation.

24-60. (canceled)

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0028] In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn, are not necessarily intended to convey any information regarding the actual shape of the particular elements, and may have been solely selected for ease of recognition in the drawings.

[0029] FIG. 1 is a schematic diagram that illustrates a hybrid computing system comprising an analog processor and a digital processor.

[0030] FIG. 2 illustrates a schematic diagram of a portion of a quantum processor.

[0031] FIG. 3A is a graph showing an evolution of an analog processor where the normalized evolution coefficient increases over time.

[0032] FIG. 3B is a graph showing an exemplary evolution of an analog processor where the normalized evolution coefficient increases and decreases over time during the course of an annealing schedule.

[0033] FIG. 4 is a flow diagram of a computational method using a hybrid computing system for evolving a quantum processor wherein characteristics of the quantum processor are determined before completion of an annealing evolution schedule, and the annealing evolution is reinitialized.

[0034] FIG. 5 is a flow diagram of a computational method using a hybrid computing system for evolving a quantum processor wherein characteristics of the quantum processor are determined before completion of an annealing evolution schedule, and the annealing evolution is reversed.

[0035] FIG. 6 is a flow diagram of a computational method using a hybrid computing system for evolving a quantum processor wherein characteristics of the quantum processor are determined before completion of an annealing evolution schedule, and the annealing evolution is continued after the determination.

[0036] FIG. 7 is a flow diagram of a computational method using a hybrid computing system for evolving a quantum processor wherein an annealing evolution is optionally paused and then ramped in order to determine the characteristics of the quantum processor before completion of an annealing evolution schedule, suitable for use in performing the methods of FIGS. 4-6.

[0037] FIG. 8 is a flow diagram of a computational method using a hybrid computing system autonomously identifying deviation of the determined characteristics of the quantum processor from user specified dynamics, suitable for use with the methods of FIGS. 4-7.

[0038] FIG. 9 is a flow diagram of a computational method using a hybrid computing system to autonomously identify occurrence of events during an annealing evolution, provide an alert and optionally stop the annealing evolution in response to the event, suitable for use with the methods of FIGS. 4-8.

[0039] FIG. 10 is a flow diagram of a computational method using a hybrid computing system to receive user specified expected behavior of at least part of a quantum processor expected to occur during iteration(s) of an annealing evolution and to provide a representation of actual behavior of the part(s) of the quantum processor, suitable for use with the methods of FIGS. 4-9.

[0040] FIG. 11 is a flow diagram of a computational method using a hybrid computing system to transform low level machine state information into higher level representation information, suitable for use with the methods of FIGS. 4-10.

[0041] FIGS. 12A and 12B are a flow diagram of a computational method using a hybrid computing system for evolving a quantum processor wherein characteristics of the quantum processor are determined before completion of an annealing evolution schedule, performance of the annealing is evaluated, and optionally an alert is produced, the annealing evolution stopped, or the annealing evolution is reinitialized, reversed, or continued based on the evaluation.

[0042] FIG. 13 is a flow diagram of a computational method using a hybrid computing system for evolving a quantum processor wherein user specified expected behavior is received as one or more mathematical models, suitable for use in performing the method of FIGS. 12A and 12B.

[0043] FIG. 14 is a flow diagram of a computational method using a hybrid computing system for evolving a quantum processor wherein a second representation of a problem is received for embedding into a hardware graph of the analog processor, suitable for use in performing the method of FIGS. 12A and 12B.

[0044] FIG. 15 is a flow diagram of a computational method using a hybrid computing system for evolving a quantum processor wherein variable dynamics of the quantum processor are confirmed to be homogeneous and not frozen before late in an annealing evolution, and the annealing evolution is optionally stopped based on an outcome of the confirmation, suitable for use in performing the method of FIGS. 12A and 12B.

[0045] FIG. 16 is a flow diagram of a computational method using a hybrid computing system for evolving a quantum processor wherein a distribution of classical states that represent a projection of a quantum distribution of states of a quantum processor are determined after ramping a rate of an annealing evolution at one or more intermediate points in annealing evolution, either with or without a preceding pause in the annealing evolution, suitable for use in performing the method of FIGS. 12A and 12B.

[0046] FIG. 17 is a flow diagram of a computational method using a hybrid computing system for evolving a quantum processor wherein a determination is made as to whether a classical value of a variable at a beginning of an annealing evolution is zero for an Ising model problem, suitable for use in performing the method of FIGS. 12A and 12B.

[0047] FIG. 18 is a flow diagram of a computational method using a hybrid computing system for evolving a quantum processor wherein a determination is made as to whether a product of two coupled spins at a beginning of an annealing evolution is zero for an Ising model problem, suitable for use in performing the method of FIGS. 12A and 12B.

[0048] FIG. 19 is a flow diagram of a computational method using a hybrid computing system for evolving a quantum processor wherein a confirmation is made that at least one or more chains of qubits is or are not broken, suitable for use in performing the method of FIGS. 12A and 12B.

[0049] FIG. 20 is a graph showing a progression of an annealing evolution (s) as a function of time, suitable for use in performing the various methods with ramping of the annealing evolution that are described herein.

[0050] FIG. 21 is a flow diagram of a computational method of operation of a hybrid computing system for evolving a quantum processor wherein at least two components (e.g., qubits) are annealed at different rates, and information about a first component is used to modify an annealing evolution of the second component, suitable for use in performing various methods taught herein.

[0051] FIG. 22 is a flow diagram of a computational method 2200 of operation of a hybrid computing system for evolving a quantum processor wherein an annealing rate is changed based on determined characteristics which were determined at one or more intermediary points during an annealing evolution, suitable for use in performing various methods taught herein.

DETAILED DESCRIPTION

[0052] In the following description, certain specific details are set forth in order to provide a thorough understanding of various disclosed implementations. However, one skilled in the relevant art will recognize that implementations may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with computer systems, server computers, and/or communications networks have not been shown or described in detail to avoid unnecessarily obscuring descriptions of the implementations.

[0053] Unless the context requires otherwise, throughout the specification and claims that follow, the word comprising is synonymous with including, and is inclusive or open-ended (i.e., does not exclude additional, unrecited elements or method acts).

[0054] Reference throughout this specification to one implementation or an implementation means that a particular feature, structure or characteristic described in connection with the implementation is included in at least one implementation. Thus, the appearances of the phrases in one implementation or in an implementation in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations.

[0055] As used in this specification and the appended claims, the singular forms a, an, and the include plural referents unless the context clearly dictates otherwise. It should also be noted that the term or is generally employed in its sense including and/or unless the context clearly dictates otherwise.

[0056] The headings and Abstract of the Disclosure provided herein are for convenience only and do not interpret the scope or meaning of the implementations.

[0057] FIG. 1 illustrates a hybrid computing system 100 including a digital computer 102 coupled to an analog computer 104. In some implementations the analog computer 104 is a quantum computer. The exemplary digital computer 102 includes a digital processor (CPU) 106 that may be used to perform classical digital processing tasks.

[0058] Digital computer 102 may include at least one digital processor (such as central processor unit 106 with one or more cores), at least one system memory 108, and at least one system bus 110 that couples various system components, including system memory 108, to central processor unit 106.

[0059] The digital processor may be any logic processing unit, such as one or more central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic controllers (PLCs), etc.

[0060] Unless described otherwise, the construction and operation of the various blocks shown in FIG. 1 are of conventional design. As a result, such blocks need not be described in further detail herein, as they will be understood by those skilled in the relevant art.

[0061] Digital computer 102 may include a user input/output subsystem 112. In some implementations, the user input/output subsystem includes one or more user input/output components such as a display 114, mouse 116, and/or keyboard 118.

[0062] System bus 110 can employ any known bus structures or architectures, including a memory bus with a memory controller, a peripheral bus, and a local bus. System memory 108 may include non-volatile memory, such as read-only memory (ROM), static random access memory (SRAM), Flash NAND; and volatile memory such as random access memory (RAM) (not shown).

[0063] Digital computer 102 may also include other non-transitory computer-or processor-readable storage media or non-volatile memory 120. Non-volatile memory 120 may take a variety of forms, including: a hard disk drive for reading from and writing to a hard disk, an optical disk drive for reading from and writing to removable optical disks, and/or a magnetic disk drive for reading from and writing to magnetic disks. The optical disk can be a CD-ROM or DVD, while the magnetic disk can be a magnetic floppy disk or diskette. Non-volatile memory 120 may communicate with digital processor via system bus 110 and may include appropriate interfaces or controllers 122 coupled to system bus 110. Non-volatile memory 120 may serve as long-term storage for processor- or computer-readable instructions, data structures, or other data (sometimes called program modules) for digital computer 102.

[0064] Although digital computer 102 has been described as employing hard disks, optical disks and/or magnetic disks, those skilled in the relevant art will appreciate that other types of non-volatile computer-readable media may be employed, such a magnetic cassettes, flash memory cards, Flash, ROMs, smart cards, etc. Those skilled in the relevant art will appreciate that some computer architectures employ volatile memory and non-volatile memory. For example, data in volatile memory can be cached to non-volatile memory. Or a solid-state disk that employs integrated circuits to provide non-volatile memory.

[0065] Various processor- or computer-readable instructions, data structures, or other data can be stored in system memory 108. For example, system memory 108 may store instruction for communicating with remote clients and scheduling use of resources including resources on the digital computer 102 and analog computer 104.

[0066] In some implementations system memory 108 may store processor-or computer-readable calculation instructions to perform pre-processing, co-processing, and post-processing to analog computer 104. System memory 108 may store a set of analog computer interface instructions to interact with the analog computer 104.

[0067] Analog computer 104 may include an analog processor such as quantum processor 124. The analog computer 104 can be provided in an isolated environment, for example, in an isolated environment that shields the internal elements of the quantum computer from heat, magnetic field, and other external noise (not shown).

[0068] FIG. 2 is a schematic diagram of a portion of an exemplary superconducting quantum processor 200 designed for quantum annealing (and/or adiabatic quantum computing) which may be used to implement the present systems and devices. The portion of superconducting quantum processor 200 shown in FIG. 2 includes two superconducting qubits 201, and 202. Also shown is a tunable ?.sub.i.sup.z?.sub.j.sup.z coupling (diagonal coupling) via coupler 210 therebetween qubits 201 and 202. While the portion of quantum processor 200 shown in FIG. 2 includes only two qubits 201, 202 and one coupler 210, those of skill in the art will appreciate that quantum processor 200 may include any number of qubits and any number of couplers coupling information therebetween.

[0069] The portion of quantum processor 200 shown in FIG. 2 may be implemented to physically realize quantum annealing and/or adiabatic quantum computing. Quantum processor 200 includes a plurality of interfaces 221-225 that are used to configure and control the state of quantum processor 200. Each of interfaces 221-225 may be realized by a respective inductive coupling structure, as illustrated, as part of a programming subsystem and/or an evolution subsystem. Such a programming subsystem and/or evolution subsystem may be separate from quantum processor 200, or it may be included locally (i.e., on-chip with quantum processor 200) as described in, for example, U.S. Pat. Nos. 7,876,248 and 8,035,540.

[0070] In the operation of quantum processor 200, interfaces 221 and 224 may each be used to couple a flux signal into a respective compound Josephson junction 231 and 232 of qubits 201 and 202, thereby realizing the Aj terms in the system Hamiltonian. Similarly, interfaces 222 and 223 may each be used to apply a flux signal into a respective qubit loop of qubits 201 and 202, thereby realizing the h.sub.i terms in the system Hamiltonian. Furthermore, interface 225 may be used to couple a flux signal into coupler 210, thereby realizing the J.sub.ij term(s) in the system Hamiltonian.

[0071] Throughout this specification and the appended claims, the term quantum processor is used to generally describe a collection of physical qubits (e.g., qubits 201 and 202) and couplers (e.g., coupler 210). The physical qubits 201 and 202 and the coupler 210 are referred to as the programmable elements of the quantum processor 200 and their corresponding parameters (e.g., the qubit h.sub.i values and the coupler J.sub.ij values) are referred to as the programmable parameters of the quantum processor. In the context of a quantum processor, the term programming subsystem is used to generally describe the interfaces (e.g., programming interfaces 222, 223, and 225) used to apply the programmable parameters (e.g., the h.sub.i and J.sub.ij terms) to the programmable elements of the quantum processor 200 and other associated control circuitry and/or instructions.

[0072] As previously described, the programming interfaces of the programming subsystem may communicate with other subsystems which may be separate from the quantum processor or may be included locally on the processor. The programming subsystem may, in operation, receive programming instructions in a machine language of the quantum processor and execute the programming instructions to program the programmable elements in accordance with the programming instructions. Similarly, in the context of a quantum processor, the term evolution subsystem generally includes the interfaces (e.g., evolution interfaces 221 and 224) used to evolve the programmable elements of the quantum processor 200 and other associated control circuitry and/or instructions. For example, the evolution subsystem may include annealing signal lines and their corresponding interfaces (221, 224) to the qubits (201, 202).

[0073] Quantum processor 200 also includes readout devices 251 and 252, where readout device 251 is associated with qubit 201 and readout device 252 is associated with qubit 202. In some embodiments, such as shown in FIG. 2, each of readout devices 251 and 252 includes a DC-SQUID inductively coupled to the corresponding qubit. In the context of quantum processor 200, the term readout subsystem is used to generally describe the readout devices 251, 252 used to read out the final states of the qubits (e.g., qubits 201 and 202) in the quantum processor to produce a bit string. The readout subsystem may also include other elements, such as routing circuitry (e.g., latching elements, a shift register, or a multiplexer circuit) and/or may be arranged in alternative configurations (e.g., an XY-addressable array, an XYZ-addressable array, etc.). Qubit readout may also be performed using alternative circuits, such as that described in U.S. Pat. No. 8,854,074.

[0074] While FIG. 2 illustrates only two physical qubits 201, 202, one coupler 210, and two readout devices 251, 252, a quantum processor (e.g., processor 200) may employ any number of qubits, couplers, and/or readout devices, including a larger number (e.g., hundreds, thousands or more) of qubits, couplers and/or readout devices. The application of the teachings herein to processors with a different (e.g., larger) number of computational components should be readily apparent to those of ordinary skill in the art.

[0075] FIG. 3A is a graph 300a of an evolution of an analog processor over time. An analog processor may be a quantum processor comprising superconducting qubits and couplers.

[0076] Vertical axis 301 represents the normalized evolution coefficient s and the horizontal axis 302 represents the time of the evolution of the analog processor. The normalized evolution coefficient s may represent the normalized flux applied to a compound Josephson junction or the normalized persistent current Ip of a flux qubit. The normalized evolution coefficient s changes monotonically over time, increasing from 0 to a maximum value of 1. A person skilled in the art will understand that the rate of change of the normalized evolution coefficient s over time is shown in FIG. 3A for illustration purposes only and in other implementations the normalized evolution coefficient can increase at a slower or faster rate. In some implementations the normalized evolution coefficient s can change non-linearly. Examples of evolution schedules of analog processors are described in greater detail in Patent Publication No. U.S. 2015/0363708, which is here incorporated by reference.

[0077] Techniques described herein are used to operate a hybrid processor comprising an analog processor and a digital processor where the normalized evolution coefficient s may increase and/or decrease over the course of the operation of the hybrid processor. For certain operations it may be desirable to operate the hybrid processor such that the analog processor reaches a predetermined classical spin state at the end of a first or initial evolution. This technique may allow study of problem dynamics or it may be used for obtaining samples from the analog processor.

[0078] FIG. 3B is a graph of an example evolution 300b of an analog processor over time, operating with a digital processor to form a hybrid processor according to the present systems, methods and apparatus. An analog processor may comprise a quantum processor. Vertical axis 301 represents the normalized evolution coefficient s and the horizontal axis 302 the time of the evolution of the analog processor.

[0079] Before the start of example evolution 300b, the hybrid processor may determine a classical spin state and apply preparatory bias to the analog processor to target the evolution of the analog processor towards the classical spin state. Preparatory bias may be applied via the analog processor's circuitry components, for example, via on-chip DACs or analog lines. Preparatory bias may influence the evolution of the analog processor towards any classical state. When the analog processor is a quantum processor with n qubits, there are 2.sup.n classical states.

[0080] In example evolution 300b the normalized evolution coefficient s increases from 0 to 1 in time t.sub.1. A person skilled in the art will understand that the rate of the evolution from 0 to t.sub.1 is shown in FIG. 3B for illustration purposes only and in other implementations the rate of the evolution of the analog processor from 0 to t.sub.1 may be faster of slower than illustrated. A faster evolution may be referred to as a ramp or described as ramping relative to another rate of evolution (e.g. a prior rate at which the problem was evolved, a standard and/or benchmark rate of evolution, a user-defined rate, a predominant rate of evolution of that problem, etc.).

[0081] At t.sub.1 the evolution is paused until time t.sub.2. During the time interval t.sub.1-t.sub.2, shown in FIG. 3B as time interval 310, the digital processor may remove the preparatory bias applied before the start of example evolution 300b. A person skilled in the art will understand that time interval 310 is dependent on the particular hardware and configuration of the analog processor and the digital processor comprising the hybrid processor. Therefore, the time needed for the digital processor to reprogram the analog processor and remove the applied preparatory bias may be different than shown in FIG. 3B. In some implementations time interval 310 may range, for example, from 100 ?s to 200 ?s. When the analog processor is a quantum processor, the digital processor may pause the evolution and retain the target classical spin state by keeping the energy barrier of the qubits high.

[0082] Additionally or alternatively, the hybrid processor may pause the evolution of the analog processor for a time interval longer than needed to reprogram the analog processor, thereby performing other operations, such as readout or post-processing, during time interval 310.

[0083] After time interval 310, the evolution of the analog processor resumes in a direction opposite the direction before time interval 310, i.e., backwards. During this phase the normalized evolution coefficient s decreases from 1 to a value s* until time t.sub.3. The digital processor may determine the value of e before the start of example evolution 300b or during time interval 310.

[0084] Where the analog processor is a quantum processor, after time interval 310, the energy barriers of the qubits are lowered until an intermediate transverse field and/or tunneling energy is reached. The intermediate transverse field and/or tunneling energy may be determined by the digital processor.

[0085] After time t.sub.3, the evolution of the analog processor is paused for a time interval 320. Time interval 320 may be determined by the digital processor, either before the start of example evolution 300b or during time interval 310. In some implementations time interval 320 may, for example, range from 1 ?s to milliseconds.

[0086] A person skilled in the art will understand that the rate of change of the normalized evolution coefficient s between time t.sub.2 and time t.sub.3 may be the same as the rate of change between 0 and time t.sub.1 or may be different. The digital processor may, for example, determine the rate of change of the normalized evolution coefficient.

[0087] After time interval 320, the evolution of the analog processor resumes in the same direction as the evolution from 0 to time t.sub.1, i.e., the normalized evolution coefficient s increases from value s*to 1 until the analog processor reaches a classical spin state at time t.sub.5. Where the analog processor is a quantum processor, the digital processor may raise the energy barriers of the qubits to reach a classical spin state. The classical spin state reached at time t.sub.5 may not be the same as the classical spin state reached at time t.sub.1, given that the preparatory bias has been removed at time interval 310.

[0088] After time t.sub.5, the digital processor may read out the classical spin state reached at t.sub.5 and may perform post-processing.

[0089] In an alternative implementation, the hybrid processor performs post-processing on the obtained classical spin states at time interval 310 using classical methods. Therefore, the evolution of the analog processor is paused for a length of time necessary for the digital processor to perform the post-processing operations. An example of a classical post-processing method is Houdayer cluster moves, performed for a predetermined number of times; however, other classical algorithms can be used.

[0090] Alternatively, or in addition, post-processing may be used to improve samples obtained by the analog processor at time t.sub.1. In an effort to improve the diversity of the samples obtained from the analog processor, the samples obtained at t.sub.1 can be post processed as described above and used as feedback to run the evolution of the analog processor one or more times. During the time interval 310, after the digital processor has completed the post-processing operation, the digital processor sets preparatory bias to the analog processor using the post-processed samples as input to influence the evolution of the analog processor towards obtaining a more diverse set of samples (e.g., obtaining samples from regions in the energy landscape that had not been explored by the analog processor). At time t.sub.2 the evolution of the processor resumes backwards as described above until the normalized evolution coefficient reaches value e at t.sub.3. As noted above, the samples obtained at t.sub.5 may not be equal to the samples obtained at t.sub.1 or the post-processes samples at t.sub.1. After time t.sub.5 the digital processor may read out the samples obtained by the analog processor.

[0091] FIG. 4 shows a computational method 400 of operation of a hybrid computing system to evolve a quantum processor, wherein characteristics of the quantum processor are determined before completion of an annealing evolution schedule, and the annealing evolution is reinitialized. The determined characteristics relate to a state of the quantum processor during the evolution, and may include (for example) qubit spin, flux, charge, magnetization, and/or other physical manifestations of qubits' states, as well as (or alternatively) coupling strengths between qubits.

[0092] The method 400 starts at 402, for example, in response to receipt of a problem, application of power, or a call or invocation from another routine.

[0093] At 404, at least one component of a hybrid computing system, for example, a digital processor, determines an annealing evolution schedule to perform a quantum annealing evolution computation on a problem representation. The annealing schedule may be determined before a start of an annealing evolution, which follows the determined annealing schedule.

[0094] At 406, at least one component of the hybrid computing system causes a start of one or more iterations of an annealing evolution of a quantum processor with a problem representation embedded in a hardware graph of the quantum processor. The annealing evolution is performed in accordance with the annealing evolution schedule.

[0095] At 408, at least one component of the hybrid computing system causes an iterative loop to execute. The iterative loop may execute until an exit condition is reached, for example, a defined number of times, an answer is reached or a consensus answer is reached, and/or an error condition occurs or is detected. Within the iterative loop, at 410, at least one component of the hybrid computing system optionally causes one or more interruptions of the annealing evolution before a completion of the annealing evolution schedule. Within the iterative loop, at 412, at least one component of the hybrid computing system determines characteristic(s) of a quantum processor at point(s) between start of respective iterations of the annealing evolution and before completion of the annealing evolution schedule. The characteristics may be determined after optionally interrupting the annealing evolution. Various ways of determining the characteristics are discussed herein. Within the iterative loop, at 414, at least one component of the hybrid computing system causes a reinitialization of the annealing evolution before a completion of the annealing evolution schedule. The reinitialization reinitializes the various values of the quantum processor to restart the annealing evolution on the same representation or instance of the problem. Within the iterative loop, at 416, at least one component of the hybrid computing system determines whether an exit condition (e.g., defined number of times, answer is reached, consensus answer is reached, and/or an error condition occurred) has been reached.

[0096] The method 400 terminates at 418, for example, until invoked again. Alternatively, the method 400 may repeat until a problem or all problems have been processed.

[0097] FIG. 5 is a computational method 500 using a hybrid computing system for evolving a quantum processor wherein characteristics of the quantum processor are determined before completion of an annealing evolution schedule, and the annealing evolution is reversed.

[0098] The method 500 starts at 502, for example, in response to receipt of a problem, application of power, or a call or invocation from another routine.

[0099] At 504, at least one component of a hybrid computing system, for example, a digital processor, determines an annealing evolution schedule to perform a quantum annealing evolution computation on a problem representation. The annealing schedule may be determined before a start of an annealing evolution, which follows the determined annealing schedule.

[0100] At 506, at least one component of the hybrid computing system causes a start of one or more iterations of an annealing evolution of a quantum processor with a problem representation embedded in a hardware graph of the quantum processor. The annealing evolution is performed in accordance with the annealing evolution schedule.

[0101] At 508, at least one component of the hybrid computing system causes an iterative loop to execute. The iterative loop may execute until an exit condition is reached, for example, a defined number of times, an answer is reached or a consensus answer is reached, and/or an error condition occurs or is detected. Within the iterative loop, at 510, at least one component of the hybrid computing system optionally causes one or more interruptions of the annealing evolution before a completion of the annealing evolution schedule. Within the iterative loop, at 512, at least one component of the hybrid computing system determines characteristic(s) of a quantum processor at point(s) between start of respective iteration of the annealing evolution and before completion of the annealing evolution schedule. The characteristics may be determined after optionally interrupting the annealing evolution. Various ways of determining the characteristics are discussed herein. Within the iterative loop, at 514, at least one component of the hybrid computing system causes a reversal of the annealing evolution, before a completion of the annealing evolution schedule. Various ways of reversing the annealing evolution are discussed elsewhere herein. Within the iterative loop, at 516, at least one component of the hybrid computing system determines whether an exit condition (e.g., defined number of times, answer is reached, consensus answer is reached, and/or an error condition occurred) has been reached.

[0102] The method 500 terminates at 518, for example, until invoked again. Alternatively, the method 500 may repeat until a problem or all problems have been processed.

[0103] FIG. 6 shows a computational method 600 of operation of a hybrid computing system for evolving a quantum processor wherein characteristics of the quantum processor are determined before completion of an annealing evolution schedule, and the annealing evolution is continued after the determination.

[0104] The method 600 starts at 602, for example, in response to receipt of a problem, application of power, or a call or invocation from another routine.

[0105] At 604, at least one component of a hybrid computing system, for example, a digital processor, determines an annealing evolution schedule to perform a quantum annealing evolution computation on a problem representation. The annealing schedule may be determined before a start of an annealing evolution, which follows the determined annealing schedule.

[0106] At 606, at least one component of the hybrid computing system causes a start of one or more iterations of an annealing evolution of a quantum processor with a problem representation embedded in a hardware graph of the quantum processor. The annealing evolution is performed in accordance with the annealing evolution schedule.

[0107] At 608, at least one component of the hybrid computing system causes an iterative loop to execute. The iterative loop may execute until an exit condition is reached, for example, a defined number of times, an answer is reached or a consensus answer is reached, and/or an error condition occurs or is detected. Within the iterative loop, at 612, at least one component of the hybrid computing system determines characteristic(s) of a quantum processor at point(s) between the start of respective iteration of the annealing evolution and before completion of the annealing evolution schedule. The characteristics may be determined after optionally interrupting the annealing evolution. Various ways of determining the characteristics are discussed herein. Within the iterative loop, at 614, at least one component of the hybrid computing system causes a continuation of the annealing evolution, without any interruptions of the annealing evolution before the completion of the annealing evolution schedule. Various ways of reversing the annealing evolution are discussed elsewhere herein. Within the iterative loop, at 616, at least one component of the hybrid computing system determines whether an exit condition (e.g., defined number of times, answer is reached, consensus answer is reached, and/or an error condition occurred) has been reached.

[0108] The method 600 terminates at 618, for example, until invoked again. Alternatively, the method 600 may repeat until a problem or all problems have been processed.

[0109] FIG. 7 shows a computational method 700 of operation of a hybrid computing system for evolving a quantum processor wherein an annealing evolution is optionally paused and then ramped in order to determine the characteristics of the quantum processor before completion of an annealing evolution schedule, suitable for use in performing the methods of FIGS. 4-6.

[0110] Optionally at 702, at least one component of the hybrid computing system causes a pause of an annealing evolution of a quantum processor to occur. The pause may, for example, occur immediately prior to the determination the characteristics 412, 512 of the methods 400 (FIG. 4) and 500 (FIG. 5), or as part thereof. The pause is notably absent from the method 600 (FIG. 6).

[0111] At 704, at least one component of the hybrid computing system causes a ramping of the annealing evolution of the quantum processor before completion of the annealing evolution schedule. The determination of at least one characteristic of the quantum processor 412, 512, 612 (FIGS. 4, 5, 6) occurs concurrently with or immediately following the ramping of the annealing evolution of the quantum processor.

[0112] At 706, at least one component of the hybrid computing system reads out respective states of one or more qubits in order to determine the characteristics of the quantum processor. For example, detectors may be coupled to qubits and the states of the detectors may be influenced by the qubits to which they are coupled. The states of the detectors may be read and used to infer the states of the qubits to which they are coupled. In general, the weaker the coupling, the less that the quantum state of the quantum processor is likely to be affected. In some implementations, the detectors are weakly coupled to the qubits. For example, the strength of a coupling between detector and qubit may be limited to a threshold coupling strength that is dominated by the maximum coupling strength in the problem and/or by the maximum coupling strength between the qubit and other qubits in the problem. For instance, the coupling strength between qubit and detector may be 90%, 50%, 10%, or some other less-than-100% proportion of the dominating coupling strength.

[0113] By ramping at an intermediate point in the anneal, either with or without a preceding pause, it is possible to determine or characterize a distribution of classical states that represents a projection of the quantum distribution of quantum processor states. In simple terms, it is possible to observe what is happening in the quantum processor throughout an anneal. While the projection to the classical space is a sort of shadow of what the quantum processor is doing, it still provides valuable information allowing useful adjustments to be made, for example, recasting a representation of a problem to execute more effectively on the quantum processor.

[0114] The expected (classical) value of a variable at a beginning of an anneal should be zero in an Ising model. The same should be true of the product of two coupled spins. By tracking these measurements through the anneal, it is possible to determine where the values stop changing, which indicates when a variable freezes. This provides a new approach for estimating freeze out that can be run in parallel, i.e., for all devices, with no auxiliary devices or fluxes. A possible drawback of such an approach is that the anneal ramp is not instantaneous. It may or may not be advantageous to pause immediately before ramping of the anneal.

[0115] Tracking other measurements through the anneal is also potentially useful. When tracking the expected product of two spins with a chain coupling between them, a tendency to break (i.e., go to a product much less than +1, e.g. as low as ?1) early in the anneal would likely indicate that the chain edge should be stronger. A tendency to break late in the anneal might indicate that the chain edge should be stronger or that the chain must be more dynamical. One way to make a chain more dynamical is, for example, to delay it in the anneal.

EXAMPLE

[0116] 1. For a mesh of important values of s, e.g., {0:20; 0:21; . . . , 0:69; 0:70}, do the following: [0117] (a) Run the problem many times with a fast ramp at s. Gather the set S(s) of samples. [0118] (b) For each qubit q, do the following: [0119] i. Analyze the statistics of S(s) with respect to q. [0120] ii. Gather the function F.sub.q(s), defined as the average value of q at point s. [0121] (c) For each pair of coupled qubits q, q do the following: [0122] i. Analyze the statistics of S(s) with respect to the product q.Math.q. [0123] ii. Gather the function G.sub.q.sup.q(s), defined as the average value of q.Math.q at point s.

[0124] 2. Now analyze these functions F.sub.q and G.sub.q.sup.q and apply the knowledge to debug the system.

[0125] In the case where there are no fields, i.e., the input Ising problem (h,J) hash={right arrow over (0)}, each function F.sub.q(s) should ideally be zero everywhere for every q. If h is nonzero, then F.sub.q can approach ?1 at some point in the anneal. The earlier this occurs, the earlier q decides on a value, and the more we might delay q in order to homogenize dynamics with other qubits.

[0126] Whether or not there are fields, each function G.sub.q.sup.q(s) can go to near ?1 at some point in the anneal; the earlier this happens, the earlier this coupler decides to be frustrated or unfrustrated. A qubit incident to many early-deciding couplers can likely be delayed in order to homogenize dynamics with other qubits.

[0127] If a chain coupling between q and q has G.sub.q.sup.q(s) tend to a value much less than 1 at an early point in the anneal, it may indicate that the chain is insufficiently dynamic It may be appropriate to delay the qubits in such a case. If it tends to a value much less than 1 later in the anneal, it may indicate that the chain coupling is insufficient to ensure chain fidelity. It may be appropriate to increase the chain coupling in such a case.

[0128] FIG. 8 shows a computational method 800 of operation of a hybrid computing system autonomously identifying deviation of the determined characteristics of the quantum processor from user specified dynamics, suitable for use with the methods of FIGS. 4-7.

[0129] At 802, at least one component of the hybrid computing system receives a set of user specified dynamics.

[0130] At 804, at least one component of the hybrid computing system autonomously compares a set of determined characteristics to the set of user specified dynamics.

[0131] At 806, at least one component of the hybrid computing system autonomously identifies one or more deviations of the set of determined characteristics from the set of user specified dynamics.

[0132] Optionally at 808, at least one component of the hybrid computing system produces one or more alerts in response to an identification of a deviation from the set of user specified dynamics, for example, a deviation that exceeds a defined threshold deviation. For example, the at least one component can produce an electronic notification or message, cause a visual display (e.g., flashing light, color change) and/or an aural (e.g., beep) or tactile alert.

[0133] Optionally at 810, in response to detection of the deviation, the at least one component of the hybrid computing system autonomously stops the annealing evolution before an end thereof as specified by the annealing evolution schedule.

[0134] FIG. 9 shows a computational method 900 of operation of a hybrid computing system to autonomously identify occurrence of events during an annealing evolution, provide an alert and optionally stop the annealing evolution in response to the event, suitable for use with the methods of FIGS. 4-8.

[0135] At 902, at least one component of the hybrid computing system autonomously identifies an occurrence of at least one event based at least in part on the determined characteristics of the quantum processor as determined during the annealing evolution of the quantum processor. The events may be one of a set of defined events.

[0136] Optionally at 904, at least one component of the hybrid computing system produces an alert in response to an identification of an occurrence of one or more events. For example, the at least one component can produce an electronic notification or message, cause a visual display (e.g., flashing light, color change) and/or an aural (e.g., beep) or tactile alert.

[0137] Optionally at 906, at least one component of the hybrid computing system optionally autonomously stops the annealing evolution before an end thereof as specified by the annealing evolution schedule.

[0138] Alternatively, at least one component of the hybrid computing system can even autonomously take corrective action. For example, at least one component of the hybrid computing system can autonomously strengthen a chain edge in response to detecting a broken chain, thereby implementing quantum auto-debugging.

[0139] FIG. 10 shows a computational method 1000 of operation of a hybrid computing system to receive user specified expected behavior of at least part of a quantum processor expected to occur during iteration(s) of an annealing evolution and to provide a representation of actual behavior of the part(s) of the quantum processor, suitable for use with the methods of FIGS. 4-9.

[0140] At 1002, at least one component of the hybrid computing system receives a user specified expected behavior of the quantum processor or portions thereof, which user specified expected behavior is expected to occur during at least one portion of the annealing evolution of at least one of the iterations.

[0141] At 1004, at least one component of the hybrid computing system provides a representation of a behavior that occurred during at least a portion of the annealing evolution of the quantum processor. For example, the at least one component (e.g., control system) of the hybrid computing system may provide the representation to an end user device. The provision of the representation typically occurs subsequent to a performance of the respective portion of the annealing evolution.

[0142] FIG. 11 shows a computational method 1100 of operation of a hybrid computing system to transform low level machine state information into higher level representation information, suitable for use with the methods of FIGS. 4-19.

[0143] At 1102, at least one component of the hybrid computing system (e.g., control system) transforms a set of low level machine state information into a set of higher level representation information. For example, the at least one component can transform a set of low level machine state information that represents a behavior that occurred during at least a portion of the annealing evolution of the quantum processor into a set of higher level representation information, which is more readily understood by a human technician. The user can find where her specification of the problem is not what she intended or conceivably find and identify improvements in the quantum annealer itself that will deliver better behavior.

[0144] FIGS. 12A and 12B show a computational method 1200 of operation of a hybrid computing system for evolving a quantum processor wherein characteristics of the quantum processor are determined before completion of an annealing evolution schedule, performance of the annealing is evaluated, and optionally an alert is produced, the annealing evolution stopped, or the annealing evolution is reinitialized, reversed, or continued based on the evaluation.

[0145] The method 1200 starts at 1202, for example, in response to receipt of a problem, application of power, or a call or invocation from another routine.

[0146] At 1204, at least one component of the hybrid computing system receives a user specified expected behavior of the quantum processor, the user specified expected behavior which specifies a behavior of the quantum processor expected to occur during one or more iterations of the annealing evolution.

[0147] At 1206, at least one component of the hybrid computing system embeds a first representation of a problem in a hardware graph of the quantum processor. Various techniques of embedding are discussed elsewhere herein an in the various commonly assigned patent literature which is incorporated herein by reference.

[0148] At 1208, at least one component of the hybrid computing system starts one or more iterations of an annealing evolution of the quantum processor with the first representation of the problem embedded therein.

[0149] During each iteration of the annealing evolution on the first representation of the problem, at 1210 at least one component of the hybrid computing system determines a set of characteristics of the quantum processor at one or more points of time between a start of a respective iteration of the annealing evolution and before a completion of an annealing evolution schedule.

[0150] During each iteration of the annealing evolution on the first representation of the problem, at 1212 at least one component of the hybrid computing system determines whether a performance of the annealing evolution matches a specified performance, for example, based at least in part on the set of determined characteristics of the quantum processor.

[0151] During each iteration of the annealing evolution on the first representation of the problem, optionally at 1214 at least one component of the hybrid computing system produces an alert. For instance, at least one component of the hybrid computing system produces an alert in response to the performance of the annealing evolution of the quantum processor failing to match or satisfy a specified performance. The at least one component can, for example, produce an electronic notification or message, cause a visual display (e.g., flashing light, color change) and/or an aural (e.g., beep) or tactile alert.

[0152] During each iteration of the annealing evolution on the first representation of the problem, optionally at 1216 at least one component of the hybrid computing system stops the annealing evolution. For instance, at least one component of the hybrid computing system can stop at least the respective iteration of the annealing evolution in response to the performance of the annealing evolution of the quantum processor failing to match or satisfy a specified performance.

[0153] During each iteration of the annealing evolution on the first representation of the problem, optionally at 1218 at least one component of the hybrid computing system determines if an exit condition has occurred. The exit condition can, for example, constitute the performance of the annealing evolution of the quantum processor failing to match or satisfy a specified performance. Additionally or alternatively, the exit condition can, for example, be completion of a defined number of iterations, an answer is reached, a consensus answer is reached, and/or an error condition has occurred.

[0154] At 1220, at least one component of the hybrid computing system determines a second representation of the problem based at least in part on a set of feedback from at least part of a first iteration of an annealing evolution of the quantum processor with the first representation of problem embedded therein. For example, the second representation of the problem may comprise a modification of the first representation of the problem to follow an alternative annealing evolution schedule.

[0155] At 1222, at least one component of the hybrid computing system embeds a second representation of a problem in a hardware graph of the quantum processor. Various techniques of embedding are discussed elsewhere herein and in the various commonly assigned patent literature which is incorporated herein by reference.

[0156] At 1224, at least one component of the hybrid computing system starts one or more iterations of an annealing evolution of the quantum processor with the second representation of the problem embedded therein.

[0157] During each iteration of the annealing evolution on the first representation of the problem, at 1226 at least one component of the hybrid computing system determines a set of characteristics of the quantum processor at one or more points of time between a start of a respective iteration of the annealing evolution and before a completion of an annealing evolution schedule.

[0158] During each iteration of the annealing evolution on the first representation of the problem, at 1228 at least one component of the hybrid computing system determines whether a performance of the annealing evolution matches a specified performance, for example, based at least in part on the set of determined characteristics of the quantum processor.

[0159] During each iteration of the annealing evolution on the second representation of the problem, optionally at 1230 at least one component of the hybrid computing system produces an alert. For instance, at least one component of the hybrid computing system produces an alert in response to the performance of the annealing evolution of the quantum processor failing to match or satisfy a specified performance. The at least one component can, for example, produce an electronic notification or message, cause a visual display (e.g., flashing light, color change) and/or an aural (e.g., beep) or tactile alert.

[0160] During each iteration of the annealing evolution on the first representation of the problem, optionally at 1232 at least one component of the hybrid computing system stops the annealing evolution. For instance, at least one component of the hybrid computing system can stop at least the respective iteration of the annealing evolution in response to the performance of the annealing evolution of the quantum processor failing to match or satisfy a specified performance.

[0161] During each iteration of the annealing evolution on the second representation of the problem, optionally at 1234 at least one component of the hybrid computing system determines if an exit condition has occurred. The exit condition can, for example, constitute the performance of the annealing evolution of the quantum processor failing to match or satisfy a specified performance. Additionally or alternatively, the exit condition can, for example, be completion of a defined number of iterations, an answer is reached, a consensus answer is reached, and/or an error condition has occurred.

[0162] The method 1200 terminates at 1236, for example, until invoked again. Alternatively, the method 1200 may repeat until a problem or all problems have been processed.

[0163] FIG. 13 shows a computational method 1300 of operation of a hybrid computing system for evolving a quantum processor wherein user specified expected behavior is received as one or more mathematical models, suitable for use in performing the method of FIGS. 12A and 12B.

[0164] At 1302, at least one component of the hybrid computing system receives one or more mathematical models that specify a user specified expected behavior.

[0165] FIG. 14 shows a computational method 1400 of operation of a hybrid computing system for evolving a quantum processor wherein a second representation of a problem is received for embedding into a hardware graph of the analog processor, suitable for use in performing the method of FIGS. 12A and 12B.

[0166] At 1402, at least one component of the hybrid computing system receives a second representation. The second representation may be a different representation of the same fundamental problem as represented by the first representation. The second representation can, in some implementations, be based on what was learned from attempting to solve the first representation of the problem, for example the need to increasing a certain chain strength.

[0167] FIG. 15 shows a computational method 1500 of operation of a hybrid computing system for evolving a quantum processor wherein variable dynamics of the quantum processor are confirmed to be homogeneous and not frozen before late in an annealing evolution, and the annealing evolution is optionally stopped based on an outcome of the confirmation, suitable for use in performing the method of FIGS. 12A and 12B.

[0168] At 1502, at least one component of the hybrid computing system confirms that a set of variable dynamics are homogeneous, and not frozen before a threshold point in annealing evolution. For example, the threshold point may be determined based on predicted and/or observed dynamics of the problem (e.g. the threshold may be the point s* at which a proportion of qubits in the problem have frozen; the proportion may be, for instance, 10%, 20%, 50%, 80%, or some other suitable proportion), based on a proportion of an annealing evolution (e.g. s*=0.25, 0.5, 0.75, or some other suitable proportion), provided by a user, and/or otherwise obtained.

[0169] At 1504, at least one component of the hybrid computing system causes the annealing evolution to stop in response to detecting that one or more states of the components (e.g., qubits, couplers) of the quantum processor have stopped changing, which indicates the existence of a variable freeze.

[0170] FIG. 16 shows a computational method 1600 of operation of a hybrid computing system for evolving a quantum processor wherein a distribution of classical states that represent a projection of a quantum distribution of states of a quantum processor are determined after ramping a rate of an annealing evolution at one or more intermediate points in annealing evolution, either with or without a preceding pause in the annealing evolution, suitable for use in performing the method of FIGS. 12A and 12B.

[0171] At 1602, at least one component of the hybrid computing system determines a distribution of classical states that represent a projection of a quantum distribution of states of the quantum processor after ramping a rate of annealing evolution at one or more intermediate points in the annealing evolution. Depending on the specific implementation, such can be performed either with, or without, a preceding pause in the annealing evolution immediately before the ramping.

[0172] FIG. 17 shows a computational method 1700 of operation of a hybrid computing system for evolving a quantum processor wherein a determination is made as to whether a classical value of a variable at a beginning of an annealing evolution is zero for an Ising model problem, suitable for use in performing the method of FIGS. 12A and 12B.

[0173] At 1702, at least one component of the hybrid computing system determines whether a classical value of one or more variables at a beginning of an annealing evolution is zero where the problem is an Ising model problem.

[0174] FIG. 18 shows a computational method 1800 of operation of a hybrid computing system for evolving a quantum processor wherein a determination is made as to whether a product of two coupled spins at a beginning of an annealing evolution is zero for an Ising model problem, suitable for use in performing the method of FIGS. 12A and 12B.

[0175] At 1802, at least one component of the hybrid computing system determines whether a product of two coupled spins at a beginning of an annealing evolution is zero where the problem is an Ising model problem.

[0176] FIG. 19 shows a computational method 1900 of operation of a hybrid computing system for evolving a quantum processor wherein a confirmation is made that at least one or more chains of qubits is or are not broken, suitable for use in performing the method of FIGS. 12A and 12B.

[0177] At 1902, at least one component of the hybrid computing system confirms that one or more chains of qubits (e.g., logical qubits) is not broken.

[0178] FIG. 20 is a graph 2000 showing a progression of an annealing evolution (s) as a function of time, suitable for use in performing the various methods with ramping of the annealing evolution that are described herein.

[0179] Spikes correspond to intermediary-anneal read-outs s.sub.1 and s.sub.2.

[0180] In addition to or in place of the various approaches described above, a hybrid computing system may implement variable rate annealing, which can be used to modify an amount of time spent near a quantum phase transition. The amount of time can, for example, be increased, for instance, to more thoroughly search for the ground state. The amount of time can, for example, be decreased, for instance, to pass through an avoided crossing and intentionally evolve to an excited state. This can be implemented as a form of auto-debugging (i.e., autonomous debugging and adjustment). For instance, a number of samples or determinations of characteristics of the quantum processor may be taken over a course of an annealing evolution on a given problem, and the intermediary-anneal points at which excited states are likely to be entered identified. Once those points are identified, the user can be notified and/or the hybrid system can autonomously modify the annealing schedules of affected qubits to pass through avoided crossings.

[0181] In addition to or in place of the various approaches described above, qubits can be paired so that a problem is represented twice, on two parallel sets of qubits. Each pair of qubits can be strongly coupled so that their states correlate. One set of qubits (i.e., one of each pair) is evolved faster than the other set of qubits. The faster-annealing set of qubits can, for example, be ramped at one or more intermediary-anneal points, and/or may be generally evolved faster over the course of the annealing evolution. The results of the faster-annealing qubits may be used to capture an intermediate state of the other (normally-annealing) set of qubits, thereby providing debugging information. In some implementations, the pairs of qubits might be uncoupled at a point in the anneal where the faster-annealing qubits are ramped.

[0182] In addition to or in place of the various approaches described above, a hybrid computing system may generate and/or use spectrographic information via tunneling spectography. Briefly, a probe device (such as a qubit or a specialized device) may be slowed down relative to inspected devices (e.g., down to MHz scale from GHz scale) in order to obtain spectrographic information. This can be done by advancing the annealing process for probe devices. This can avoid the need to adjust annealing signals on a global annealing signal line, which disadvantageously slows down many qubits, even if only one probe qubit is targeted. This makes it possible to, for example, use the per-qubit annealing technique, to adjust the annealing schedule of selected probe devices (e.g., just one, a pair, or any other selected number of probe devices).

[0183] FIG. 21 shows a computational method 2100 of operation of a hybrid computing system for evolving a quantum processor wherein at least two components (e.g., qubits) are annealed at different rates, and information about a first component is used to modify an annealing evolution of the second component, suitable for use in performing various methods taught herein. While two pairs of qubits are discussed, this approach can be applied to any number of pairs of qubits or other quantum processor components, devices or elements (e.g., couplers).

[0184] The method 2100 starts at 2102, for example, in response to receipt of a problem, application of power, or a call or invocation from another routine.

[0185] At 2104, at least one component of a hybrid computing system, for example, a digital processor, optionally strongly couples a second qubit of a first pair of qubits with a first qubit of the first pair of qubits. The first and second qubits of the first pair of qubits may remain strongly coupled throughout at least the respective iteration of an annealing evolution of the first and the second qubits of the first pair of qubits.

[0186] At 2106, at least one component of a hybrid computing system, for example, a digital processor, optionally strongly couples a second qubit of a second pair of qubits with the first qubit of the second pair of qubits. The first and second qubits of the second pair of qubits may remain strongly coupled throughout at least the respective iteration of an annealing evolution of the first and the second qubits of the second pair of qubits.

[0187] At 2108, at least one component of a hybrid computing system, for example, a digital processor, causes annealing of the first qubit of the first pair of qubits toward a solution at a first rate.

[0188] At 2110, at least one component of a hybrid computing system, for example, a digital processor, optionally causes annealing of the first qubit of the second pair of qubits toward a solution at a first rate. This first rate may, for example, be the same or different than the first rate at which the first qubit of the first pair of qubits is annealed.

[0189] At 2112, at least one component of a hybrid computing system, for example, a digital processor, causes annealing of the second qubit of the first pair of qubits toward the solution at a second rate, concurrently with the annealing of the first qubit bit of the first pair of qubits. The second rate at which the second qubit of the first pair of qubits is annealed is faster than the first rate at which the first qubit of the first pair of qubits is annealed.

[0190] At 2114, at least one component of a hybrid computing system, for example, a digital processor, optionally causes annealing of the second qubit of the second pair of qubits toward a solution at a second rate, concurrently with the annealing of the first qubit of the second pair of qubits. The second rate at which the second qubit of the second pair of qubits is annealed is faster than the first rate at which the first qubit of the second pair of qubits is annealed.

[0191] At 2116, at least one component of a hybrid computing system, for example, a digital processor, determines a state of the second qubit of the first pair of qubits at a first intermediary time or point, the first intermediary time or point being before an end of the annealing of the first qubit of the first pair of qubits. This allows the hybrid computing system to use one device (e.g., second qubit of the pair) as a proxy for another device (e.g., first qubit of the pair), which is at an advanced state of the annealing evolution relative to the other device.

[0192] At 2118, at least one component of a hybrid computing system, for example, a digital processor, optionally determines a state of the second qubit of the second pair of qubits at a first intermediary time or at a point before an end of the annealing of the first qubit of the second pair of qubits. This allows the hybrid computing system to use one device (e.g., second qubit of the pair) as a proxy for another device (e.g., first qubit of the pair), which is at an advanced state of the annealing evolution relative to the other device.

[0193] At 2120, at least one component of a hybrid computing system, for example, a digital processor, modifies the annealing of the first qubit of the first pair of qubits based at least in part on the determined state of the second qubit of the first pair of qubits.

[0194] At 2122, at least one component of a hybrid computing system, for example, a digital processor, optionally modifies the annealing of the first qubit of the second pair of qubits based at least on part on the determined state of the second qubit of the second pair of qubits.

[0195] The method 2100 terminates at 2124, for example, until invoked again. Alternatively, the method 2100 may repeat until a problem or all problems have been processed.

[0196] FIG. 22 shows a computational method 2200 of operation of a hybrid computing system for evolving a quantum processor wherein an annealing rate is changed based on determined characteristics which were determined at one or more intermediary points during an annealing evolution, suitable for use in performing various methods taught herein.

[0197] The method 2200 starts at 2202, for example, in response to receipt of a problem, application of power, or a call or invocation from another routine.

[0198] At 2204, at least one component of a hybrid computing system, for example, a digital processor, determines an annealing evolution schedule to perform a quantum annealing evolution computation on a problem representation in a quantum processor,

[0199] At 2206, at least one component of a hybrid computing system, for example, a digital processor, causes a start of a number of iterations (e.g., at least a first iteration) of an annealing evolution of the quantum processor, with the problem representation embedded in the quantum processor, in accordance with the annealing evolution schedule.

[0200] During a performance of the iteration(s) of the annealing evolution, at 2208 at least one component of a hybrid computing system determines at least one characteristic of the quantum processor at at least a first point in time, between a start of the first iteration of the annealing evolution and before a completion of the annealing evolution schedule.

[0201] During a performance of the iteration(s) of the annealing evolution, at 2210 at least one component of a hybrid computing system causes a change in a rate of the annealing evolution from a rate specified by a previous annealing evolution schedule. The change in rate is based at least in part on the determined at least one characteristic of the quantum processor.

[0202] The method 2200 terminates at 2212, for example, until invoked again. Alternatively, the method 2200 may repeat until a problem or all problems have been processed.

[0203] The above described method(s), process(es), or technique(s) could be implemented by a series of processor readable instructions stored on one or more nontransitory processor-readable media. Some examples of the above described method(s), process(es), or technique(s) are performed in part by a specialized device such as an adiabatic quantum computer or a quantum annealer or a system to program or otherwise control operation of an adiabatic quantum computer or a quantum annealer, for instance, a computer that includes at least one digital processor. The above described method(s), process(es), or technique(s) may include various acts, though those of skill in the art will appreciate that in alternative examples certain acts may be omitted and/or additional acts may be added. Those of skill in the art will appreciate that the illustrated order of the acts is shown for exemplary purposes only and may change in alternative examples. Some of the exemplary acts or operations of the above described method(s), process(es), or technique(s) are performed iteratively. Some acts of the above described method(s), process(es), or technique(s) can be performed during each iteration, after a plurality of iterations, or at the end of all the iterations.

[0204] The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Although specific implementations of and examples are described herein for illustrative purposes, various equivalent modifications can be made without departing from the spirit and scope of the disclosure, as will be recognized by those skilled in the relevant art. The teachings provided herein of the various implementations can be applied to other methods of quantum computation, not necessarily the exemplary methods for quantum computation generally described above.

[0205] The various implementations described above can be combined to provide further implementations. All of the commonly assigned U.S. patent application publications, U.S. patent applications, foreign patents, and foreign patent applications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety, including but not limited to: U.S. Provisional Patent Application Ser. No. 62/364,169 filed Jul. 19, 2016; U.S. Provisional Patent Application Ser. No. 62/417,940 filed Nov. 4, 2016; U.S. Patent Publication No. U.S. 2015/0269124; U.S. Patent Publication No. U.S. 2015/0161524; U.S. Pat. No. 7,876,248, U.S. Pat. No. 8,035,540, U.S. Pat. No. 8,854,074, PCT Patent application PCT/US2016/031885, and Patent Publication U.S. 2015/0363708.

[0206] These and other changes can be made to the implementations in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific implementations disclosed in the specification and the claims, but should be construed to include all possible implementations along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.