Hall electromotive force signal detection circuit having a difference calculation circuit and current sensor thereof

Abstract

The present invention relates to a hall electromotive force signal detection circuit and a current sensor thereof each of which is able to achieve excellent wide-band characteristics and fast response as well as high accuracy. A difference calculation circuit samples a component synchronous with a chopper clock generated by a chopper clock generation circuit, out of an output voltage signal of a signal amplifier circuit, at a timing obtained from the chopper clock, so as to detect the component. An integrating circuit integrates an output from the difference calculation circuit in the time domain. An output voltage signal from the integrating circuit is fed back to a signal amplifier circuit via a third transconductance element.

Claims

1. A hall electromotive force signal detection circuit, comprising: a hall element configured to generate a signal that includes a hall electromotive force signal and an offset signal component; a first switching circuit configured to modulate the hall electromotive force signal at a frequency of a chopper clock to generate an output voltage signal from the first switching circuit; a signal amplifier circuit configured to amplify the output voltage signal from the first switching circuit to output a first output signal having the hall electromotive force signal and the offset signal component, the offset signal component being modulated at the frequency of the chopper clock; and a feedback circuit configured to generate a feedback signal representing a ripple in the first output signal to the signal amplifier circuit, wherein the signal amplifier circuit comprises: a first transconductance element configured to convert the output voltage signal from the first switching circuit into a first current; a second switching circuit configured to demodulate the hall electromotive force signal based on a primary current to generate the first output signal; a pair of resistors connected in series and configured to perform voltage-division on a component included in the first output signal at a predetermined ratio to generate a divided voltage; a third switching circuit directly connected to the pair of the resistors and configured to invert a polarity of the divided voltage generated by the voltage-division based on the frequency of the chopper clock to generate an output voltage; and a second transconductance element configured to convert the output voltage from the third switching circuit into a second current, and configured to output the second current to the second switching circuit, wherein the feedback circuit comprises a third transconductance element configured to convert the feedback signal into a third current, and configured to output the third current to the second switching circuit, and wherein the primary current is a sum of the first current, the second current, and the third current.

2. The hall electromotive force signal detection circuit according to claim 1, wherein the feedback circuit configured to perform time derivatives of the first output signal.

3. The hall electromotive force signal detection circuit according to claim 1, wherein the feedback circuit comprises a switched capacitor circuit.

4. The hall electromotive force signal detection circuit according to claim 1, wherein the signal amplifier circuit further includes an output stage coupled to the second switching circuit and provided in a subsequent stage of the first transconductance element.

5. The hall electromotive force signal detection circuit according to claim 1, wherein the third transconductance element has its output directly connected between the first transconductance element and the second switching circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A and 1B illustrate hall electromotive force detection at the time when the direction of a driving current that biases a hall element is switched between 0 degree and 90 degrees every time the phase of the chopper clock is changed between two values, i.e., ϕ1 and ϕ2.

(2) FIGS. 2A to 2D illustrate signal waveforms occurring in the hall element.

(3) FIG. 3 illustrates a signal spectrum of a signal Vhall occurring in the hall element.

(4) FIG. 4 is a circuit configuration diagram to describe a hall electromotive force signal detection circuit as a premise of the present embodiment.

(5) FIG. 5 is a circuit configuration diagram to understand FIG. 4.

(6) FIG. 6 illustrates a signal spectrum in an output voltage Vout of a signal amplifier circuit.

(7) FIG. 7 is a circuit configuration diagram to describe one example of the hall electromotive force signal detection apparatus according to the present embodiment.

(8) FIGS. 8A to 8C illustrate a state where Vout(ϕ1) and Vout(ϕ2) are detected by sampling in a case where there is no time variation in a target magnetic field to be detected by a magnetic sensor using a hall element or the time variation is moderately slow.

(9) FIGS. 9A to 9C illustrate waveforms of a signal amplifier circuit Vout in a case where the time variation is fast in a target magnetic field B to be detected by the magnetic sensor using a hall element.

(10) FIG. 10 is a circuit configuration diagram in which a difference calculation circuit and an integrating circuit in the hall electromotive force signal detection circuit according to the present embodiment are implemented with switched capacitor circuits.

(11) FIG. 11 is a circuit configuration diagram in which the difference calculation circuit and the integrating circuit in the hall electromotive force signal detection circuit according to the present embodiment are implemented with an AD converter, an integrator by use of digital circuit, and a DA converter.

(12) FIG. 12 is a circuit configuration diagram illustrating an example of the difference calculation circuit in the hall electromotive force signal detection circuit according to the present embodiment, and an integrating circuit including an ΔΣ-type AD converter and a DA converter.

(13) FIG. 13 is a circuit configuration diagram illustrating an example using a double-integral AD converter, as the difference calculation circuit in the hall electromotive force signal detection circuit according to the present embodiment, and an integrating circuit including a DA converter.

(14) FIG. 14 illustrates the operation of the double-integral AD converter.

(15) FIG. 15 is a circuit configuration diagram illustrating an example of a feedback circuit that is different from the feedback circuit of the hall electromotive force signal detecting apparatus according to the present embodiment as illustrated in FIG. 7.

DESCRIPTION OF EMBODIMENTS

(16) With reference to drawings, the following describes embodiments of the present invention.

(17) The above-mentioned description deals with offset cancellation technique by use of the driving method (the spinning current method) of a hall element using a chopper clock. As to the hall element that performs the spinning current method, the following describes a configuration of a hall electromotive force signal detection circuit, which will be a premise of the present embodiment, with reference to FIG. 4.

(18) FIG. 4 is a circuit configuration diagram to describe a hall electromotive force signal detection circuit, as a premise of the present embodiment, and FIG. 5 is a circuit configuration diagram to understand FIG. 4. In these figures, a reference sign 1 indicates a hall element, a reference sign 2 indicates a first switching circuit, a reference sign 3 indicates a signal amplifier circuit, a reference sign 4 indicates a chopper clock generation circuit, a reference sign 31 indicates a first transconductance element (a transistor differential pair; Gm, 1), a reference sign 32 indicates a second switching circuit, a reference sign 33 indicates a second transconductance element (a transistor differential pair; Gm, 2), a reference sign 34 indicates a third switching circuit, a reference sign 35 indicates an output stage of the signal amplifier circuit 3 (a transistor differential pair; Gm, out), and a reference sign 36 indicates an operational amplifier.

(19) In the hall electromotive force signal detection circuit illustrated in FIG. 4, a signal Vhall input into the signal amplifier circuit 2 from the hall element 1 is input to the transistor differential pair Gm, 1, and a current I1 is generated according to Expression 2. Here, there also exist an offset Vos(Gm, 1) in the transistor differential pair Gm, 1 of the signal amplifier circuit, and therefore, the current I1 is affected by this offset voltage Vos(Gm, 1).

(20) Note that, in FIG. 4, the current I1 is a differential signal. In view of this, in regard to reference signs I1+ and I1− in FIG. 4, the following relationship is assumed: I1=(I1+)−(I1−).

(21) $\begin{array}{cc}\left[\mathrm{Math}.2\right]& \end{array}$$\begin{array}{cc}\mathrm{Output}\mathrm{Current}I1\mathrm{from}\mathrm{Transistor}\mathrm{Differential}\mathrm{Pair}\mathrm{Gm},1& \end{array}$$\begin{array}{cc}\{\begin{array}{c}\begin{array}{c}I1\left(\mathrm{\varphi 1}\right)=\mathrm{Gm},1.Math.\left(\mathrm{Vhall}\left(\mathrm{\varphi 1}\right)+\mathrm{Vos}\left(\mathrm{Gm},1\right)\right)=\mathrm{Gm},1.Math.\\ \left(+\mathrm{Vsig}\left(B\right)+\mathrm{Vos}\left(\mathrm{Hall}\right)+\mathrm{Vos}\left(\mathrm{Gm},1\right)\right)\left(\mathrm{Chopper}\mathrm{Clock}=\mathrm{\varphi 1}\right)\end{array}\\ \begin{array}{c}I1\left(\mathrm{\varphi 2}\right)=\mathrm{Gm},1.Math.\left(\mathrm{Vhall}\left(\mathrm{\varphi 2}\right)+\mathrm{Vos}\left(\mathrm{Gm},1\right)\right)=\mathrm{Gm},1.Math.\\ \left(-\mathrm{Vsig}\left(B\right)+\mathrm{Vos}\left(\mathrm{Hall}\right)+\mathrm{Vos}\left(\mathrm{Gm},1\right)\right)\left(\mathrm{Chopper}\mathrm{Clock}=\mathrm{\varphi 2}\right)\end{array}\end{array}& \mathrm{Expression}2\end{array}$

(22) Note that in the hall electromotive force signal detection circuit illustrated in FIG. 4, the number of hall elements 1 is one. However, since a hall electromotive force signal generated in the hall element 1 is converted into a current according to Expression 2, even in the case where a plurality of hall elements is used, it is possible to detect the sum of the hall electromotive force signals generated in the plurality of hall elements by converting hall electromotive force signals corresponding to respective hall elements into currents and adding those currents together.

(23) In the hall electromotive force signal detection circuit illustrated in FIG. 4, a feedback from the output voltage Vout by use of resistors R1 and R2 is prepared, and a feedback voltage Vfb from the output voltage Vout is generated according to Expression 3.

(24) $\begin{array}{cc}\left[\mathrm{Math}.3\right]& \end{array}$$\begin{array}{cc}\mathrm{Feedback}\mathrm{from}\mathrm{Output}\mathrm{Voltage}\mathrm{Vout}\mathrm{of}\mathrm{Signal}\mathrm{Amplifier}\mathrm{Circuit}& \end{array}$$\begin{array}{cc}\mathrm{Vfb}=\frac{R1}{R1+R2}\mathrm{Vout}& \mathrm{Expression}3\end{array}$

(25) The transistor differential pair Gm, 2 in the signal amplifier circuit 3 is driven by the feedback voltage Vfb represented by Expression 3 from the output voltage Vout. However, since there exists an offset Vos(Gm, 2) in the transistor differential pair Gm, 2, a current I2 output from Gm, 2 is represented by Expression 4.

(26) Note that, in FIG. 4, the current I2 is a differential signal. In view of this, in regard to reference signs I2+ and I2− in FIG. 4, the following relationship is assumed: I2=(I2+)−(I2−).

(27) $\begin{array}{cc}\left[\mathrm{Math}.4\right]& \end{array}$$\begin{array}{cc}\mathrm{Output}\mathrm{Current}I2\mathrm{from}\mathrm{Transistor}\mathrm{Differential}\mathrm{Pair}\mathrm{Gm},2& \end{array}$$\begin{array}{cc}\begin{array}{cc}\{\begin{array}{c}\begin{array}{c}\begin{array}{c}I2\left(\mathrm{\varphi 1}\right)=+\mathrm{Gm},2.Math.\mathrm{Vfb}+\\ \mathrm{Gm},2.Math.\mathrm{Vos}\left(\mathrm{Gm},2\right)\left(\mathrm{Chopper}\mathrm{Clock}=\mathrm{\varphi 1}\right)\end{array}\\ \begin{array}{c}I2\left(\mathrm{\varphi 2}\right)=-\mathrm{Gm},2.Math.\mathrm{Vfb}+\\ \mathrm{Gm},2.Math.\mathrm{Vos}\left(\mathrm{Gm},2\right)\left(\mathrm{Chopper}\mathrm{Clock}=\mathrm{\varphi 2}\right)\end{array}\end{array}\\ \end{array}& \end{array}& \mathrm{Expression}4\end{array}$

(28) In the hall electromotive force signal detection circuit illustrated in FIG. 4, the feedback works so that the sum of the output current I1 from the transistor differential pair Gm, 1 and the output current I2 from the transistor differential pair Gm, 2 becomes zero. Accordingly, when the output voltage Vout of the hall electromotive force signal detection circuit of FIG. 4 is calculated on the basis of I1+I2=0, Expression 5 is obtained.

(29) Here, as represented by Expression 5, it should be noted that the signal Vsig(B) which is modulated by the chopper clock of the chopper clock generation circuit 4 is demodulated by the third switching circuit 34 in FIG. 4. As such, the signal Vsig (B) to be detected is modulated by the chopper clock in the previous stage, and then demodulated by the chopper clock in the subsequent stage. In view of this, the category of the circuit which includes the signal amplifier circuit 3 of FIG. 4 is called chopper amplifier.

(30) $\begin{array}{cc}\left[\mathrm{Math}.5\right]& \end{array}$$\begin{array}{cc}\begin{array}{c}\mathrm{Output}\mathrm{Voltage}\mathrm{Vout}\mathrm{of}\\ \mathrm{Hall}\mathrm{Electromotive}\mathrm{Force}\end{array}\text{}\mathrm{Signal}\mathrm{Detection}\mathrm{Circuit}& \end{array}$$\begin{array}{cc}\{\begin{array}{c}\begin{array}{c}\mathrm{Vout}\left(\mathrm{\varphi 1}\right)=\left(1+\frac{R2}{R1}\right)\left(\frac{\mathrm{Gm},1}{\mathrm{Gm},2}\right)\mathrm{Vsig}\left(B\right)-\\ \left\{\frac{\begin{array}{c}\mathrm{Gm},1+\mathrm{Vout}\left(\mathrm{Hall}\right)+\mathrm{Gm},1+\mathrm{Vout}\\ \left(\mathrm{Gm},1\right)+\mathrm{Gm},2+\mathrm{Vout}\left(\mathrm{Gm},2\right)\end{array}}{\mathrm{Gm},2}\right\}\left(\mathrm{Chopper}\mathrm{Clock}=\mathrm{\varphi 1}\right)\end{array}\\ \begin{array}{c}\mathrm{Vout}\left(\mathrm{\varphi 2}\right)=\left(1+\frac{R2}{R1}\right)\left(\frac{\mathrm{Gm},1}{\mathrm{Gm},2}\right)\mathrm{Vsig}\left(B\right)+\\ \left\{\frac{\begin{array}{c}\mathrm{Gm},1+\mathrm{Vout}\left(\mathrm{Hall}\right)+\mathrm{Gm},1+\mathrm{Vout}\\ \left(\mathrm{Gm},1\right)+\mathrm{Gm},2+\mathrm{Vout}\left(\mathrm{Gm},2\right)\end{array}}{\mathrm{Gm},2}\right\}\left(\mathrm{Chopper}\mathrm{Clock}=\mathrm{\varphi 2}\right)\end{array}\end{array}& \mathrm{Expression}5\end{array}$

(31) The polarity of the part which is placed between parentheses “{“and ”}” in Expression 5 is inverted every time the phase of the chopper clock is switched between ϕ1 and ϕ2. As can be seen from this, in the hall electromotive force signal detection circuit illustrated in FIG. 4, every time the phase of the chopper clock is switched between ϕ1 and ϕ2, the sum of the offset voltage of the hall element, the offset voltage of Gm, 1 and the offset voltage of Gm, 2 is modulated by the chopper clock, and ripple-shaped noise in the output Vout of the signal amplifier circuit is generated. From Expression 5, it can be understood that the signal spectrum of the output Vout of the signal amplifier circuit exhibits a spectrum as illustrated in FIG. 6. In FIG. 6, the component located in the chopper clock frequency f_chop is ripple-shaped noise superposed on the output signal Vout of the signal amplifier circuit.

(32) Further, in a case where presence of the above-mentioned ripple-shaped noise is removed from Expression 5, Expression 6 is obtained. It is shown that, in the hall electromotive force signal detection circuit illustrated in FIG. 4, the hall electromotive force signal Vsig(B) corresponding to a target magnetic field B to be detected by the magnetic sensor is amplified by the predetermined signal amplification gain (1+R2/R1) (Gm, 1/Gm, 2).

(33) $\begin{array}{cc}\left[\mathrm{Math}.6\right]& \end{array}$$\begin{array}{cc}\mathrm{Expression}\mathrm{of}\mathrm{Signal}\mathrm{Amplification}\mathrm{of}\mathrm{Hall}\mathrm{Electromotive}\mathrm{Force}\mathrm{Signal}& \end{array}$$\begin{array}{cc}\begin{array}{cc}\mathrm{Vout}=\left(1+\frac{\mathrm{R2}}{\mathrm{R1}}\right)\left(\frac{\mathrm{Gm},1}{\mathrm{Gm},2}\right)\mathrm{Vsig}\left(B\right)& \end{array}& \mathrm{Expression}6\end{array}$

(34) With reference to drawings, the following describes embodiments of the present invention.

(35) FIG. 7 is a circuit configuration diagram to describe one example of the hall electromotive force signal detection circuit according to the present embodiment. In the figure, a reference sign 11 indicates a hall element, a reference sign 12 indicates a first switching circuit, a reference sign 13 indicates a signal amplifier circuit, a reference sign 14 indicates a chopper clock generation circuit, a reference sign 15 indicates a difference calculation circuit, a reference sign 16 indicates an integrating circuit, a reference sign 17 indicates a third transconductance element (a transistor differential pair; Gm, 3), a reference sign 131 indicates a first transconductance element (a transistor differential pair; Gm, 1), a reference sign 132 indicates a second switching circuit, a reference sign 133 indicates a second transconductance element (a transistor differential pair; Gm, 2), a reference sign 134 indicates a third switching circuit, and a reference sign 135 indicates an output stage of the signal amplifier circuit 13 (a transistor differential pair; Gm, out). Note that the first switching circuit 12 is a switching circuit which is prepared to implement the spinning current method. Further, the portion (a circuit including “a third transconductance element 17”) which receives an output of the integrating circuit 16 and returns it to the signal amplifier circuit 13 is called feedback circuit.

(36) The present embodiment is a hall electromotive force signal detection circuit for generating an output voltage signal obtained by amplifying a hall electromotive force signal generated in a hall element, with a predetermined signal amplification gain. The first switching circuit 12 is configured to perform switching operations on the terminal pairs of the hall element 11 in which a terminal pair for driving a driving current to the hall element 11 and a terminal pair for detecting a hall electromotive force signal are interchanged, and to modulate a hall electromotive force signal generated in the hall element 11 at the frequency of the chopper clock.

(37) Further, the chopper clock generation circuit 14 generates a chopper clock for periodically driving the first switching circuit 12. Further, the signal amplifier circuit 13 amplifies an output voltage signal from the first switching circuit 12.

(38) Further, the difference calculation circuit 15 samples a signal component synchronized with the chopper clock generated by the chopper clock generation circuit 14, out of the output voltage signal of the signal amplifier circuit 13, at a timing obtained from the chopper clock, so as to detect the signal component. Further, the integrating circuit 16 integrates an output of the difference calculation circuit 15 in the time domain. Further, the third transconductance element 17 converts an output voltage of the integrating circuit 16 into a current to generate a third current.

(39) Further, the signal amplifier circuit 13 includes: the first transconductance element 131 for converting a hall electromotive force signal into a current so as to generate a first current; resistors R1 and R2 for performing voltage-division on the output voltage signal at a given ratio; the second switching circuit 132 for reversing a polarity of a voltage generated by the voltage-division, according to the chopper clock; the second transconductance element 133 for converting an output voltage of the second switching circuit 132 into a current so as to generate a second current; the third switching circuit 134 provided in the subsequent stage of the first transconductance element 131 and performing a demodulation operation at a chopper clock frequency; and the output stage 135 coupled to this third switching circuit 134.

(40) With such a configuration, an output voltage signal from the integrating circuit 16 is fed back to the signal amplifier circuit 13 via the third transconductance element 17. That is, with regard to a current sum of the first current I1, the second current I2, and the third current I3, feedback is performed on a DC component included in a sum of the first current and the second current via the third transconductance element 17 which converts an output voltage from the integrating circuit 16 into a current to generate the third current, so that the sum including the third current becomes zero (I1+I2+I3=0).

(41) Further, in the present embodiment, a current sensor may be constituted of the above-mentioned hall electromotive force signal detection circuit.

(42) (Feedback Circuit for Suppressing Occurrence of Ripple)

(43) The following describes the hall electromotive force signal detection circuit according to the present embodiment with reference to FIG. 7. In FIG. 7, between the output signal Vout of the signal amplifier circuit 13 which amplifies a hall electromotive force signal and the circuit node in which the current I1 and the current I2 are added in the signal amplifier circuit 13, a feedback circuit is prepared.

(44) This feedback circuit is constituted of the difference calculation circuit 15, the integrating circuit 16, and the third transconductance element 17. The current I3 output from this third transconductance element 17 acts to cancel a component Ios of a DC offset current included in a current I1+I2=Gm, 1.Math.Vhall+Gm, 2.Math.Vfb, represented by Expression 7.

(45) Note that, in FIG. 7, the current I3 is a differential signal. In view of this, in regard to reference signs I3+ and I3− in FIG. 7, the following relationship is assumed: I3=(I3+)−(I3−).

(46) Expression 7: DC Offset Current Ios Causing Ripple-Shaped Noise
Ios=Gm,1.Math.Vos(Hall)+Gm,1.Math.Vos(Gm,1)+Gm,2.Math.Vos(Gm,2)  [Math. 7]

(47) The DC offset current Ios, represented by Expression 7, is a DC offset current resulted from the voltage to current conversion in which an offset voltage of the hall element, offset voltages in the transistor differential pair (Gm, 1) 131, and the transistor differential pair (Gm, 2) 133 are converted to an current signal by use of the transistor differential pair. When this DC offset current Ios is modulated at a frequency of a chopper clock in the third switching circuit 134, ripple-shaped noise (FIG. 9) occurs in the output voltage signal Vout of the signal amplifier circuit 13. In view of this, when feedback is performed by the feedback current I3 so that the DC component Ios contained in (I1+I2) is added with 13 and the resulting sum becomes zero, it is possible to eliminate the occurrence of the ripple-shaped noise.

(48) (Difference Calculation Circuit)

(49) For the purpose of detecting a component of a chopper clock frequency from the ripple-shaped noise in the signal amplifier output signal Vout with high accuracy, the above-mentioned feedback performs time discretization (sampling) on the signal amplifier output signal Vout at a timing just before the chopper clock changes.

(50) That is, Vout(ϕ1) is detected by sampling at a timing just before a chopper clock phase changes from ϕ1 to ϕ2, Vout(ϕ2) is detected by sampling at a timing just before the chopper clock phase changes from ϕ2 to ϕ1, and a difference signal Vout(ϕ1)−Vout(ϕ2) between Vout(ϕ1) and Vout(ϕ2) is calculated as a discrete-time signal. Thus, it is the function of the difference calculation circuit 15 in the present embodiment to perform a calculation of the time variation of Vout between two timing separated at a certain time period (calculation corresponding to time derivatives).

(51) (Integrating Circuit in Subsequent Stage of Difference Calculation Circuit)

(52) In the example in FIG. 7 of the hall electromotive force signal detecting apparatus of the present embodiment, the integrating circuit 16 is placed in a subsequent stage of the difference calculation circuit 15. This integrating circuit 16 performs time integration (lowpass filter) on an amplitude component of the ripple-shaped noise detected by the difference calculation circuit 15, i.e., a DC component which is the source of the ripple-shaped noise, to remove various noise components from an output signal from the difference calculation circuit 15.

(53) As described later, in the hall electromotive force signal detecting apparatus of the present embodiment, since the difference calculation circuit 15 is a circuit for performing time discretization (sampling), a switched capacitor circuit and a digital circuit can be used for the integrating circuit 16, and, as a result, various desirable features can be realized.

(54) (Hall Electromotive Force Signal Detection Circuit According to Present Embodiment)

(55) As for the circuit configurations which suppress the occurrence of ripple-shaped noise in the output of the signal amplifier circuit 13 by feedback means, these circuit configurations are described in Non Patent Document 4 and Patent Document 5 which are mentioned before. Although, each of these documents deals with a circuit of capacitive coupling using capacitors and a circuit to invert its signal polarity with switch circuit as a circuit measure for detecting a DC component in the ripple-shaped noise, there is no description in these documents about the concept of a difference calculation circuit which is a characteristic configuration of the present embodiment.

(56) It is explained in the following that the difference calculation circuit, which is the characteristic configuration of the present embodiment, makes it possible to achieve high accuracy of feedback that suppresses the occurrence of ripple-shaped noise in an output of a signal amplifier circuit. Particularly, the difference calculation circuit 15, which is the characteristic configuration of the present embodiment, can be a suitable circuit configuration in the applications such as current sensor designed to detect a switching current of an inverter, where a frequency bandwidth of a target magnetic field signal to be detected is relatively wider than the chopper clock frequency.

(57) FIGS. 8A to 8C illustrate a state where Vout(ϕ1) and Vout(ϕ2) are detected by sampling in a case where there is no time variation in the target magnetic field to be detected by a magnetic sensor using a hall element or the time variation is slow enough. Even in this case, if a slew rate of an output stage (Gm, out) 135 of the signal amplifier for the rising voltage is unbalanced with a slew rate thereof for the falling voltage, an unbalance arises in the waveform of the ripple-shaped noise between the rising period and the falling period.

(58) Under these circumstances, in the case of Non Patent Document 4 and Patent Document 5, the unbalance between the period of rising voltage and the period of falling voltage in the ripple-shaped noise causes an error in feedback to suppress the occurrence of the ripple-shaped noise. As the chopper clock frequency is increased to a higher frequency, such unbalance becomes more significant.

(59) In contrast to this, in the difference calculation circuit, which is the characteristic configuration of the present embodiment, sampling is performed at a timing just before the chopper clock changes. In view of this, as far as the ripple-shaped noise settles into a constant value within the half of the chopper clock period, the difference calculation circuit is not affected by such unbalance between the rising period and the falling period.

(60) FIGS. 9A to 9C illustrate waveforms of the signal amplifier circuit Vout in a case where time variation is fast in the target magnetic field B to be detected by the magnetic sensor using a hall element. The situation illustrated in FIGS. 9A to 9C occurs when the band width of the signal frequency of the target magnetic field B to be detected is relatively wider than the chopper clock frequency, as in the case of a current sensor designed to detect a switching current of an inverter.

(61) In such a case, a signal Vsig(B) corresponding to the time variation of the target magnetic field B to be detected is mixed into sampled Vout(ϕ1) and Vout(ϕ2) (Expression 8). Notwithstanding, the circuit configuration of the hall electromotive force signal detection circuit according to the present embodiment is a circuit configuration which can minimize the influence of Vsig (B).

(62) In order to describe this feature of the present embodiment, the following deals with a case where a value of Vout(ϕ1) sampled in chopper clock phase ϕ1 at a time n is represented to be Vout(ϕ1)(n), similarly, a value of Vout(ϕ2) sampled in chopper clock phase ϕ2 at a time n is represented to be Vout(ϕ2)(n), and a difference signal Vout(ϕ1)(n)−Vout(ϕ2)(n) therebetween is integrated for N times with respect to the time n. Here, in a case where the target magnetic field B to be detected is a magnetic field induced by an inverter current that drives a motor, the signal Vsig(B) exhibits a sinusoidal wave form of which cycle is the same as the cycle of the inverter driving current of the motor. Accordingly, if an integration times N herein is set to be a sufficiently large number, it becomes possible to detect a ripple component (a DC offset component as a source of ripple) with high accuracy while eliminating the influence of Vsig(B), as understood from Expression 9.

(63) Further, it is a well-known fact that switched capacitor circuits and digital circuits are suitable circuit configurations for the purpose of realizing integrating circuits and narrow-band filters.

(64) $\begin{array}{cc}\left[\mathrm{Math}.8\right]& \end{array}$$\begin{array}{cc}\mathrm{Ripple}\mathrm{Detection}\mathrm{When}\mathrm{Time}\mathrm{Variation}\mathrm{of}\mathrm{Target}\mathrm{Magnetic}\mathrm{Signal}B\mathrm{to}\mathrm{be}\mathrm{Detected}\mathrm{is}\mathrm{Fast}& \end{array}$$\begin{array}{cc}\begin{array}{c}\mathrm{Vout}\left(\mathrm{\varphi 1}\right)-\mathrm{Vout}\left(\mathrm{\varphi 2}\right)=\\ \left\{\mathrm{Ripple}\mathrm{Component}\right\}+\mathrm{Vsig}\left(B\right)\end{array}& \mathrm{Expression}8\end{array}$$\begin{array}{cc}\left[\mathrm{Math}.9\right]& \end{array}$$\begin{array}{cc}\mathrm{Elimination}\mathrm{of}\mathrm{Influence}\mathrm{of}\mathrm{Vsig}\left(B\right)\mathrm{on}\mathrm{Ripple}\mathrm{by}\mathrm{Integration}\mathrm{of}\left\{\mathrm{Vout}\left(\mathrm{\varphi 1}\right)-\mathrm{Vout}\left(\mathrm{\varphi 2}\right)\right\}& \end{array}$$\begin{array}{cc}\begin{array}{c}\underset{n=1}{\overset{N}{.Math.}}\left\{\mathrm{Vout}\left(\mathrm{\varphi 1}\right)\left(n\right)-\mathrm{Vout}\left(\mathrm{\varphi 2}\right)\left(n\right)\right\}=\\ N\times \left\{\mathrm{Ripple}\mathrm{Component}\right\}\end{array}& \mathrm{Expression}9\end{array}$

(65) The difference calculation circuit, which is the characteristic configuration of the present embodiment, has the following two advantages because digital circuits can be utilized in the subsequent stages of the difference calculation circuit.

(66) The first advantage when the digital circuit is used for the circuit placed in the subsequent stage of the difference calculation circuit 15 is the reduction of an initial pull-in time of the feedback loop that suppresses the occurrence of ripple-shaped noise in the output of the signal amplifier circuit 13. As described above, this feedback loop is a feedback loop with a very narrow bandwidth, and therefore, a longtime is generally required for the initial pull-in time, where the initial pull-in time means the time which is required for the feedback loop to converge and settle the ripple-shaped noise converged to zero after the initial operation of the hall electromotive force signal detection circuit is started after power-on. Here, if a digital circuit is used for the circuit in the subsequent stage of the difference calculation circuit 15, it is easy to implement, in the digital circuit, an adaptive algorithm in which the time constant of the feedback loop may be switched between the initial period before the initial pull-in operation is completed and the steady operation period after the initial pull-in operation is completed, thereby making it possible to realize the reduction of the initial pull-in time.

(67) The second advantage obtained when a digital circuit is used for the circuit placed in the subsequent stage of the difference calculation circuit 15 is the realization of robustness of the feedback loop. The current sensor used for detecting a switching current of an inverter is used under an environment with strong disturbance noise such as electromagnetic induction noise and electrostatic induction noise which are generated at the time of the switching of the inverter. Because of this, in the current sensor used for detecting a switching current of an inverter, the disturbance noise is input into the feedback loop that suppresses the occurrence of ripple-shaped noise in the output of the signal amplifier circuit 13. However, in a case where a digital circuit is used for the circuit in the subsequent stage of the difference calculation circuit, it is possible to implement algorithms that are insusceptible to such disturbance noise in the digital circuit, thereby making it possible to realize the robustness of the feedback loop.

(68) (Example of Difference Calculation Circuit and Integrating Circuit Using Switched Capacitor Circuits)

(69) FIG. 10 is a circuit configuration diagram in which the difference calculation circuit and the integrating circuit in the hall electromotive force signal detection circuit according to the present embodiment are implemented with switched capacitor circuits. The difference calculation circuit 15 is constituted of an operational amplifier 15a, capacitors C1, diff and C2, diff, and a switch, and calculates a voltage difference between Vout(ϕ1) and Vout(ϕ2) to be sampled sequentially in the capacitor C1, diff at an input side, so as to output Vdiff (see Expression 10).

(70) Further, the integrating circuit 16 is constituted of an operational amplifier 16a, capacitors C1, int and C2, int, and a switch. Vint is calculated by converting Vdiff sampled in the capacitor C1, int at the input side into a charge (C1, int*Vdiff) and transferring the charge to the capacitor C2, int to perform integral calculation (see Expression 11).

(71) Note that the difference calculation circuit 15 and the integrating circuit 16 are switched capacitor circuits.

(72) The difference calculation circuit 15, which is the characteristic configuration of the present embodiment, has a circuit configuration known as Peak-To-Peak circuit, and calculates Vdiff=(C1, diff/C2, diff)×(1 Vout(ϕ1)−Vout(ϕ2)) according to the transfer function Hdiff(z) of the difference calculation circuit, as represented by Expression 10.

(73) Herein, Peak-To-Peak circuit is taken as an example of the difference calculation circuit to make explanation, but there are various configurations of the difference calculation circuits usable herein, as well as the Peak-To-Peak circuit.

(74) $\begin{array}{cc}\left[\mathrm{Math}.10\right]& \end{array}$$\begin{array}{cc}\mathrm{Transfer}\mathrm{Function}\mathrm{of}\mathrm{Time}\mathrm{Discretization}\begin{array}{c}\mathrm{Differential}\mathrm{Circuit}\mathrm{Constituted}\\ \mathrm{of}\mathrm{Switched}\mathrm{Capacitor}\mathrm{Circuits}\end{array}& \end{array}$$\begin{array}{cc}\mathrm{Hdiff}\left(z\right)=\left(\frac{C1,\mathrm{diff}}{\mathrm{C2},\mathrm{diff}}\right)\left(1-z^{-1}\right)& \mathrm{Expression}10\end{array}$

(75) The output signal Vdiff of the difference calculation circuit 15 in FIG. 10 is integrated by the integrating circuit 16 constituted of the switched capacitor circuits, to obtain voltage signal Vint. In the example of the circuit configuration as illustrated in FIG. 10, the transfer function Hint(z) of the integrating circuit is represented by Expression 11.

(76) $\begin{array}{cc}\left[\mathrm{Math}.11\right]& \end{array}$$\begin{array}{cc}\mathrm{Transfer}\mathrm{Function}\mathrm{of}\mathrm{Integrating}\mathrm{Circuit}\mathrm{Constituted}\mathrm{of}\mathrm{Switched}\mathrm{Capacitor}\mathrm{Circuits}& \end{array}$$\begin{array}{cc}H\mathrm{int}\left(z\right)=\left(\frac{C1,\mathrm{int}}{C2,\mathrm{int}}\right)\left(\frac{z^{-1}}{1-z^{-1}}\right)& \mathrm{Expression}11\end{array}$

(77) (Circuit Configuration Using AD Converter, Integrator by Digital Circuit, and DA Converter)

(78) FIG. 11 is a circuit configuration diagram in which the difference calculation circuit and the integrating circuit in the hall electromotive force signal detection circuit according to the present embodiment are implemented with an AD converter, an integrator by use of digital circuits, and a DA converter. In the figure, a reference sign 136 indicates an M-bit AD converter, a reference sign 138 indicates a DA converter, a reference sign 138a indicates an N-bit register, and a reference sign 138b indicates an N-bit DA converter.

(79) A difference calculation circuit 15D is the M-bit AD converter 136, an integrating circuit 16D is constituted of a digital integrator 137, and the DA converter 138 constituted of the N-bit register 138a and the N-bit DA converter 138b.

(80) According to the circuit configuration herein, the difference calculation circuit 15D in the feedback circuit according to the present embodiment is implemented with the AD converter 136, the integrating circuit 16D therein is implemented with a digital circuit constituted of the digital integrator 137 and the DA converter 138, and the output signal of the integrating circuit 16D is converted into an analog signal Vint by use of the DA converter 138b. That is, the difference calculation circuit 15D is constituted of the AD converter 136, the integrating circuit 16D is constituted as the digital circuits 137 and 138, and the voltage fed back to the third transistor differential pair (Gm, 3) 17 is generated by the DA converter 138b.

(81) (Example Using Difference Calculation Circuit Illustrated in FIG. 10 and Integrating Circuit Including ΔΣ-Modulation AD Converter and DA Converter)

(82) FIG. 12 is a circuit configuration diagram illustrating an example using the difference calculation circuit in the hall electromotive force signal detection circuit according to the present embodiment, and an integrating circuit including a ΔΣ-type AD converter and a DA converter. A difference calculation circuit 150 has the same circuit configuration as the difference calculation circuit 15 illustrated in FIG. 10. Note that a reference sign 150a indicates an operational amplifier. Further, an integrating circuit 160 is constituted of an ΔΣ-modulation AD converter 140 and an integrating circuit 16D as illustrated in FIG. 11, the integrating circuit 16D is constituted of a digital integrator 137 and a DA converter 138. The ΔΣ-modulation AD converter 140 is constituted of an integrating circuit 16 as illustrated in FIG. 10, a comparator 142 coupled to an operational amplifier 141 of this integrating circuit 16, a digital decimation filter 143 coupled to this comparator 142, and a one-bit DA converter 144 for feeding back the output of the comparator 142 to the operational amplifier 141 constituting the integrating circuit.

(83) In FIG. 12, similarly to the exemplary circuit configuration of FIG. 10, the operation of time-derivative is performed to get an analog signal Vdiff by the difference calculation circuit (Peak-To-Peak circuit) implemented with switched capacitor circuit on Vout which is the output of the signal amplifier 13. The integrating circuit into which the analog signal Vdiff is input performs AD conversion of the signal Vdiff at an input stage of the integrating circuit, so as to perform integral calculation by digital signal processing.

(84) In FIG. 12, 1st order ΔΣ modulator 140 is used as an AD converter for performing AD conversion of the analog signal Vdiff. A signal that is one-bit quantized by the comparator 142 in this ΔΣ modulator 140 is processed by the decimation filter 143 implemented as digital filter, and the digital signal ADC (Vdiff) of signed M-bit width is obtained as the digitized signal Vdiff. This signed M-bit signal is integrated by the digital-circuit integrator 137, and thus a signal of signed N-bit width is obtained. This signed N-bit signal is stored in the register 138a, and an analog voltage Vint is obtained by use of the N-bit DA converter 138b.

(85) As illustrated in FIG. 12, if an appropriate AD converter and an appropriate DA converter are used, it is possible to constitute the feedback circuit of the present embodiment so as to include digital circuits.

(86) In the feedback circuit of the present embodiment, it is necessary to keep track of the time variation of the offset voltage of the hall element and the offset voltages of the transistor differential pairs. However, the time variation of the offset voltages that should be tracked herein is very slow, and therefore, an AD converter with a high-speed operation is not required for the AD converter. Consequently, as in the case of the exemplary 1st order ΔΣ modulator illustrated in FIG. 12, it is possible to use a low-order ΔΣ modulator with a small circuit scale.

(87) (Example Using Difference Calculation Circuit including Double-Integral AD Converter Including Integrating Circuit Illustrated in FIG. 10 and Integrating Circuit Including DA Converter)

(88) As described above, the feedback loop that suppresses the occurrence of ripples is intended to cancel a DC offset, and therefore becomes a loop with extremely narrow bandwidth. In view of this, it is also possible to use an AD converter known as double-integral type, as the AD converter. The double-integral AD converter is a type that is generally used in low-speed and high-accuracy measurement such as digital multimeter, and in the present embodiment, it is one of extremely preferable types of AD conversion as a type of the AD converter constituting the above-mentioned feedback.

(89) FIG. 13 is a circuit configuration diagram illustrating an example of the hall electromotive force signal detection circuit according to the present embodiment by use of an difference calculation circuit constituted of a double-integral AD converter and a DA converter. In the figure, a reference sign 151 indicates a double-integral AD converter, a reference sign 151a indicates an operational amplifier, a reference sign 151b indicates an integration reset switch, a reference sign 151c indicates a comparator, a reference sign 151d indicates a control circuit, and a reference sign 151e indicates a counter.

(90) The double-integral AD converter 151 has the circuit configuration including the difference calculation circuit 15 shown in FIG. 10, and is constituted of the comparator 151c coupled to the operational amplifier 151a, the control circuit 151d coupled to the comparator 151c, and the counter 151e coupled to the control circuit 151d. Further, an integrating circuit 16D has a circuit configuration similar to the integrating circuit illustrated in FIG. 11, and is constituted of a digital integrator 137 and a DA converter 138. The DA converter 138 is constituted of an N-bit register 138a and an N-bit DA converter 138b coupled to this N-bit register 138a.

(91) In FIG. 13, since it is possible to integrate a difference signal between Vout(ϕ1) and Vout(ϕ2), a differential operation is performed in an AD conversion operation by use of the double-integral AD converter, obtaining ADC (Vdiff) as a digitized signal.

(92) An AD conversion operation of the double-integral AD converter 151 will be described below, with reference to FIG. 14. After AD conversion is started, the integration reset switch 151b is released in the integrator, so as to integrate Vout(ϕ1)−Vout(ϕ2) for predetermined N1 times. Then, an input selector switch control signal changes an input voltage to the integrator to +Vadc or to −Vadc according to the polarity of the output voltage of the operational amplifier 151a of the integrator, the output voltage being detected by the comparator 151c. And the integration operation of the integrator is started again. Here, the polarity of the output voltage of the integrator is monitored by the comparator 151c, and integration is performed for N2 times so that the output voltage of the integrator becomes zero. The number of counts N2 of the counter 151e obtained through the control circuit 151d is the AD conversion result of the double integral technique. That is, ADC (Vdiff)=N2 is obtained. The transfer function of the AD conversion using this double-integral AD converter 151 is represented by Expression 12 where Vout(ϕ1) and Vout(ϕ2) sampled at an i time are assumed Vout(ϕ1)(i) and Vout(ϕ2)(i), respectively.

(93) 0$\begin{array}{cc}\left[\mathrm{Math}.12\right]& \end{array}$$\begin{array}{cc}\begin{array}{c}\mathrm{AD}\mathrm{Conversion}\mathrm{by}\mathrm{Double}-\\ \mathrm{integral}\mathrm{AD}\mathrm{Converter}\end{array}& \end{array}$$\begin{array}{cc}\underset{i=1}{\overset{N1}{.Math.}}\left[\mathrm{Vout}\left(\mathrm{\varphi 1}\right)\left(i\right)-\mathrm{Vout}\left(\mathrm{\varphi 2}\right)\left(i\right)\right\}=N2\times \left(\pm \mathrm{Vadc}\right)& \mathrm{Expression}12\end{array}$

(94) The AD conversion result N2 obtained by the double-integral AD converter 151 is the result obtained by Performing AD conversion on Vout(ϕ1)−Vout(ϕ2). This digital signal N2 is integrated by the digital integrator 137, and then converted into an analog signal Vint by use of the DA converter 138b.

(95) Here, in the case of the double-integral AD converter 151, the bandwidth of the above-mentioned feedback can be controlled by variably controlling the integration count N1. That is, in an initial pull-in operation, the value of N1 is set to be a small value so as to reduce the pull-in time of the feedback, while the value of N1 is increased in the steady operation after the initial pull-in operation is completed, thereby making it possible to realize the robustness in which the feedback loop does not malfunction by disturbance noise.

(96) FIG. 15 is a circuit configuration diagram illustrating an example of a feedback circuit different from the feedback circuit of the hall electromotive force signal detecting apparatus according to the present embodiment as illustrated in FIG. 7. Note that a reference sign 18 indicates a fourth transconductance element. The feedback circuit configuration illustrated in FIG. 15 does not perform feedback from the output signal Vout of the signal amplifier circuit 13, but feedback from the input node of the output stage (Gm, out) 135.

(97) That is, it is also possible to provide the fourth transconductance element 18 between the output of the third switching circuit 134 and the difference calculation circuit 15 so as to perform feedback. An advantage of this feedback circuit configuration is that the feedback circuit for cancelling ripples is insusceptible to the fluctuation of the load seen from the output in FIG. 15. However, in the current sensor, the subsequent stage of FIG. 15 is an output buffer circuit prepared separately, and therefore, such load fluctuation is unlikely to occur. A disadvantage of the feedback circuit configuration of FIG. 15 is that the fourth transconductance element (transistor differential pair, Gm, 4) is additionally required.

(98) As stated above, the hall electromotive force signal detection circuit according to the present embodiment includes a feedback circuit for canceling a DC offset component to cause ripple-shaped noise in the output voltage signal of a signal amplifier circuit. In view of this, it is possible to realize highly accurate magnetic field detection by dynamic offset cancellation means (a spinning current method and a chopper amplifier) for modulating an offset voltage of a hall element and an offset voltage of a signal amplifier circuit, by use of a chopper clock. Further, in comparison with a circuit configuration (e.g., see Patent Document 4) in which filters for reducing ripple-shaped noise are additionally placed, it is possible to achieve fast response as a magnetic sensor, and further, there is an advantage that no noise increase occurs due to the filters thus additionally placed. Further, the above-mentioned hall electromotive force signal detection circuit of the present embodiment is usable as a current sensor.

REFERENCE SIGNS LIST

(99) 1, 11: Hall Element 2, 12: First Switching Circuit 3, 13: Signal Amplifier Circuit 4, 14: Chopper Clock Generation Circuit 15: Difference Calculation Circuit in Discrete-time (Time Discretization Difference Circuit) 15a, 16a: Operational Amplifier 16: Integrating Circuit 16a: Operational Amplifier 17: Third Transconductance Element 18: Fourth Transconductance Element 31, 131: First Transconductance Element 32, 132: Second Switching Circuit 33, 133: Second Transconductance Element 34, 134: Third Switching Circuit 35, 135: Output Stage of Signal Amplifier Circuit 36: Operational Amplifier 136: M-bit AD Converter 138: DA Converter 138a: N-bit Register 138b: N-bit DA Converter 150: Time Discretization Difference Circuit 150a, 151a: Operational Amplifier 151: Double-integral AD Converter 151b: Integration Reset Switch 151c: Comparator 151d: Control Circuit 151e: Counter