Power switching cell with normally conducting field-effect transistors

Abstract

A power switching cell with normally on field-effect transistors comprises a current switch receiving the control input signal over an activation input and a power transistor for switching a high voltage VDD applied to its drain, to its source that is connected to the output port of the cell. The control of the gate of the power transistor whose source is floating, according to the input signal, is provided by a self-biasing circuit connected between its gate and source. The current switch is connected between the self-biasing circuit and a zero or negative reference voltage. The self-biasing circuit comprises a transistor whose source or drain is connected to the gate or source of the power transistor. The gate of this transistor is biased by a resistor connected between its gate and source, and between the current switch and the source. The transistors are HEMT transistors using GaN or AsGa technology.

Claims

1. A power switching cell comprising: an input port capable of receiving a switching control signal which is referenced to a general ground of the cell, constituting a non-isolated control of the cell; a normally on field-effect power transistor having a drain capable of receiving a positive supply voltage that is defined with respect to a ground at zero reference potential in order to apply it to an output port, and a source connected to the output port; a self-biasing circuit for biasing a gate of the power transistor; and a current switch electrically connected between the self-biasing circuit and a negative or zero reference potential, a switching control input of which is connected to the input port, and configured so that, on activation by said switching control signal, said current switch electrically connects the negative or zero reference potential to the self-biasing circuit, wherein the self-biasing circuit comprises: a normally on field-effect transistor having a drain connected to the source of the power transistor and a source connected to the gate of the power transistor; a self-biasing resistor for biasing a gate of the transistor of the self-biasing circuit, which resistor is connected between the gate and the source of said self-biasing transistor; and in series between the current switch and the source of said self-biasing transistor.

2. The switching cell as claimed in claim 1, comprising an adjustable current source connected in series between said current switch and the negative or zero reference voltage.

3. The switching cell as claimed in claim 1 wherein the current switch comprises at least one field-effect transistor that is electrically connected between the self-biasing circuit and the negative or zero reference potential.

4. The switching cell as claimed in claim 3, wherein the current switch uses one or more normally on field-effect transistor(s).

5. The switching cell as claimed in claim 1, wherein activation of the current switch by the input signal switches the self-biasing transistor and the power transistor to an OFF state, that is at a turn-off limit, of the self-biasing transistor and the power transistor and deactivation of the current switch switches the self-biasing transistor and the power transistor to an ON state.

6. The switching cell as claimed in claim 1, wherein at least one of the connections in the following list comprises an additional resistor a connection between the gate of the power transistor and the self-biasing resistor; a connection between the drain of the self-biasing transistor and the source of the power transistor; a connection between the gate of the self-biasing transistor and the self-biasing resistor; a connection between the self-biasing resistor and the source of the self-biasing transistor; a connection between the control input of the current switch and the input port is resistive; a connection between the current switch and the self-biasing resistor.

7. The switching cell as claimed in claim 1, wherein the self-biasing transistor and the power transistor are HEMT field-effect transistors.

8. The switching cell as claimed in claim 7, wherein the HEMT field-effect transistors are produced using a technology chosen from the following list: GaN, GaAs.

9. An electronic device comprising n power switching cells as claimed in claim 1, the n cells being arranged in parallel, n being an integer that is greater than 1, with their output ports connected to a shared output port of the device, wherein each cell comprises a single protection diode arranged in series between the source of the power switching transistor of the cell and the shared output port.

10. The electronic device as claimed in claim 9, wherein each cell receives a respective positive supply voltage as output, wherein the cell that receives the lowest positive supply voltage is formed by the single protection diode that is directly connected between the positive supply voltage to be switched and the output of the cell.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features and advantages of the invention are described in the following detailed description, given by way of indication and with reference to the appended drawings in which:

(2) FIG. 1, already described, illustrates a basic structure of a power switching cell of the prior art using a self-biasing resistor for biasing the gate of the power transistor;

(3) the three FIGS. 2, 3 and 4 show the drain-source current and voltage curves of the power transistor, obtained by simulating such a cell, for three values of the self-biasing resistor;

(4) FIG. 5 illustrates an improved power switching cell structure according to the invention;

(5) FIG. 6 illustrates possible ways to stabilize the response of the cell by adding additional resistors to the structure of FIG. 2;

(6) FIG. 7 shows the forms of the drain-source current and voltage of the power transistor that are obtained by simulating a cell according to the invention;

(7) FIG. 8 shows the forms of the drain-source current and voltage of the power transistor that are obtained by simulating a cell according to an improved version of the invention;

(8) FIGS. 9 and 10 show the current and voltage curves at the input of a cell according to the invention; and

(9) FIGS. 11 and 12 show the corresponding voltage V.sub.out(t) and current I.sub.out(t) curves at the output P.sub.out of a cell according to the invention;

(10) FIG. 13 illustrates an application of the cell according to the invention in an electronic device using multiple power switching cells in parallel.

DETAILED DESCRIPTION OF THE INVENTION

(11) A basic structure of a cell according to the invention is illustrated in FIG. 5. For the sake of simplicity, the elements common to the cell of the prior art that is illustrated in FIGS. 1 to 4 and to the cell of the invention illustrated in FIGS. 5 to 13 bear the same references. The self-biasing and power transistors of the cell are normally on (ON state) field-effect transistors, even if this is not necessarily specified for the purpose of not overburdening the disclosure.

(12) The basic structure of a cell according to the invention illustrated in FIG. 5 shares the current switch formed by the input transistor T.sub.1 and the power transistor T.sub.2 that switches the high voltage V.sub.dd with the cell of the prior art illustrated in FIG. 1.

(13) The self-biasing resistor R.sub.2 for biasing the gate of the power transistor of the cell of FIG. 1 is replaced, in the cell according to the invention, by a self-biasing circuit P for biasing the gate comprising:

(14) a transistor T.sub.3 that is a normally on field-effect transistor, connected as follows: its drain d.sub.3 is connected to the source s.sub.2 of the power transistor T.sub.2 and hence to the output pad Out of the cell; its source s.sub.3 is connected to the gate g.sub.2; its gate g.sub.3 is connected to the resistor R.sub.3; and

(15) a self-biasing resistor R.sub.3 for biasing the gate g.sub.3 of the transistor T.sub.3, connected between this gate g.sub.3 and the source s.sub.3 of the transistor T.sub.3, and in series with the drain of the first transistor T.sub.1.

(16) The resistor R.sub.1 on the drain of the transistor T.sub.1, present in the cell of the prior art, is not shown here. It is optional.

(17) The assembly formed by the self-biasing circuit P and the power transistor T.sub.2 constitutes the load of the input transistor T.sub.1, which load is thus placed in series between the drain d.sub.1 of the transistor T.sub.1 and the positive supply voltage V.sub.DD.

(18) It should be noted that in this structure, the transistor T.sub.3 is like the transistor T.sub.2; it is a floating-source transistor in the sense that its source s.sub.3 is not referenced to a fixed potential: it follows the gate voltage of the power transistor T.sub.2.

(19) It should also be noted that although in the example the current switch is formed from one transistor T.sub.1, it could comprise multiples thereof, for example in order to form a differential pair.

(20) The operation of a cell according to the invention will now be explained by supposing a purely resistive output load denoted by R.sub.L.

(21) The cell has two stable states, the ON and OFF states: the cell is said to be in the ON state when the transistors T.sub.2 and T.sub.3 are on (ON state), and the structure delivers power to the load; the cell is said to be in the OFF state when the transistors T.sub.2 and T.sub.3 are at the turn-off limit (OFF state), and the load is isolated from the main power supply.

(22) The transistors T.sub.3 and T.sub.2 are switched to the ON or OFF state according to the control signal V.sub.IN applied as input In to the cell, and which controls the ON or OFF state of the transistor T.sub.1.

(23) As detailed below, the transistor T.sub.1 is a current switch. It is activated in order to switch a current toward the load formed by the self-biasing circuit P and the power transistor, and to switch the cell to the OFF state. The current switched by T.sub.1 is small in comparison to the current switched by the main transistor. Thus, although the transistor T.sub.1 may be chosen to be of the same technology and the same type as the transistors T.sub.2 and T.sub.3, i.e. normally on HEMT field-effect transistors, it could also be of a different technology (e.g. MOS) or conduction type. Hereinafter, and in particular in the exemplary simulations which are explained, the three transistors have been chosen to be of the same technology, HEMT, and to be normally on, thus advantageously allowing said circuit to be produced on monolithic chips (MMICs) in order to benefit from their advantages in terms of integration and decrease in parasitic wiring elements.

(24) Operation in OFF State

(25) When the transistor T.sub.1 is in the ON state (e.g. V.sub.IN=Vss=0 volt), the transistors T.sub.2 and T.sub.3 self-bias supposing a cell with elements judiciously chosen in order to allow the correct operation thereof so that both are in a state close to pinch-off (turn-off limit).

(26) Supposing a simple ideal model for the transistors T.sub.2 and T.sub.3 of the form:
Ids.sub.i=Gm.sub.i.Math.(Vgs.sub.iVp).

(27) (where Ids.sub.i, Gm.sub.i, and Vgs.sub.i are the usual notations for the drain-source current, the transconductance and the gate-source voltage of a transistor T.sub.i (i=1 or 2), respectively. Vp is the pinch-off voltage, which is the same for both transistors, and depends on the technology).

(28) Then it is shown that the gate-source voltage of the transistor T.sub.2 in the OFF state, denoted by Vgs.sub.2.sub._.sub.OFF, est given by the following equation EQ1:

(29) ${\mathrm{Vgs}}_{2\_\mathrm{OFF}}=\left[\frac{R_L.Math.{\mathrm{Gm}}_2-1-\mathrm{Vss}}{R_L.Math.{\mathrm{Gm}}_2+1}-\frac{{\mathrm{Gm}}_3.Math.\left(R_3+R_L\right)}{\left(R_L.Math.{\mathrm{Gm}}_2+1\right).Math.\left(R_3.Math.{\mathrm{Gm}}_3+1\right)}\right].Math.\mathrm{Vp}$

(30) This shows that the value of the gate-source voltage of T.sub.2 in its near pinch-off state may be adjusted to a value very close to Vp through a judicious choice of elements and voltage values, and in particular through an appropriate choice of values of R.sub.3 and Vss. The drain current in the OFF state of the transistor T.sub.2 may thus be limited to very low values.

(31) By referencing the source of T.sub.1 to ground (Vss=0 volt), it may be shown that with an optimal choice of elements of the cell, the drain current in the OFF state of the transistor T.sub.2 is substantially smaller than that obtained in the case of a cell of the prior art, presented in the introduction. Thus, replacing only the self-biasing resistor R.sub.2 of the cell of the prior art with the proposed self-biasing circuit is already advantageous in itself.

(32) By referencing the source of the transistor T.sub.1 to a more negative voltage Vss (and no longer to ground), for example to 6.5 volts, this makes it possible to more closely approach the gate-source voltage in the OFF state of the transistor T.sub.2 Vgs.sub.2.sub._.sub.OFF, hence to further decrease the drain current in the OFF state of the transistor T.sub.2, and therefore to further improve the efficiency of the cell. This solution is therefore advantageous, as will be shown below with reference to FIGS. 8 to 12.

(33) As mentioned above, the transistor T.sub.1 is a current switch. The current I switched by the transistor T.sub.1 controls the operating point of the transistor T.sub.3 of the self-biasing circuit P: this current I effectively fixes the gate-source voltage Vgs.sub.3, Vgs.sub.3=I.Math.R.sub.3, and the drain-source current Ids.sub.3, Ids.sub.3=I, of the transistor T.sub.3. A determined drain-source voltage value Vds.sub.3 of the transistor T.sub.3 corresponds to this operating point. In terms of construction, the drain-source voltage of the transistor T.sub.3 is equal to the gate-source voltage Vgs.sub.2 of the transistor T.sub.2. Thus, the transistor T.sub.1, switched to the ON state, makes it possible for the gate-source voltage of the power switching transistor T.sub.2 to be current-controlled in the OFF state (Vgs.sub.2.sub._.sub.OFF).

(34) This is indirect control, since the current I, switched by the transistor T.sub.1, is in fact delivered by the structure of the cell. The values of the current I and of the voltage Vgs.sub.2.sub._.sub.OFF are thus not directly adjustable. They are adjusted indirectly, through appropriate sizing of the structure of the cell and, in particular, through an appropriate choice of values of the resistor R.sub.3 and of the voltage Vss, as shown by the equation EQ1.

(35) It should be noted that provision may be made to connect an adjustable current source (transistor, current mirror, etc.) in series between the current switch formed by the transistor T.sub.1 and ground Vss (cf. FIG. 5, current source SC represented in dotted lines). The current I delivered by the current source SC and switched by the transistor T.sub.1 is then directly adjustable to an appropriate value, which allows a voltage Vgs.sub.2.sub._.sub.OFF that is very close to Vp to be obtained, thereby allowing electrical losses from the cell in the OFF state to be optimally limited.

(36) Operation in ON State

(37) When the transistor T.sub.1 is in the OFF state (e.g. V.sub.IN=Vp+Vss) (i.e. it no longer conducts current toward the load formed from the self-biasing circuit and the power transistor), the transistor T.sub.3 is switched to the ON state. In this state it is equivalent, at its output, to a resistor Rds.sub.3.sub._.sub.ON connected between the gate (g.sub.2) and the source (s.sub.2) of the power transistor T.sub.2, of very low value. The transistor T.sub.2 is also in the ON state.

(38) OFF.fwdarw.ON Switching

(39) So that the transistor T.sub.2 may rapidly switch from the OFF state to the ON state, it is necessary, at the moment when the transistor T.sub.2 starts to switch, for the impedance presented at the input of T.sub.2 to be low in order to favor rapid switching thereof. Stated otherwise, the transistor T.sub.3, at its output, must be equivalent to a low-value resistor. This is the case when the transistor T.sub.3 is in the on state. However, in the transient switching phase, T.sub.3 also switches from the near-off state to the on state. It then presents a resistance to T.sub.2 that varies from a high value to a low value. However, in practice, the transistor T.sub.3 has a much smaller spread than T.sub.2 as does not have to conduct large currents. Its input capacitance c.sub.in3 is therefore much lower than the input capacitance c.sub.in2 Of T.sub.2 and thus it is able to switch very rapidly. Its equivalent output resistance therefore very rapidly equals its low resistance in the on state, thereby also allowing T.sub.2 to switch very rapidly.

(40) The switching time of the transistor T.sub.2 from the OFF state to the ON state is given by the formula: t.sub.ON.fwdarw.OFF=R.sub.eq(T3).Math.c.sub.in2, where R.sub.eq(T3) denotes the equivalent resistance of the transistor T.sub.3 and is a mean value: when T.sub.3 is in the OFF state, its equivalent resistance is high. When T.sub.3 switches to the ON state, its equivalent resistance becomes increasingly low until reaching a value that is very low and, in practice, much lower than the optimum value of the resistor R.sub.2 which is defined for the cell structure of the prior art (FIG. 1).

(41) Thus, all of the effects favorably contribute to the same end.

(42) It should be noted that the cell according to the invention requires no particular circuitry for managing temporal shifts in switching the various transistors, which would be difficult to achieve at the target switching speeds.

(43) It should also be noted that the substantial current draw generated by the rapid charging of the input capacitance of T.sub.2 passes between the drain and the source of T.sub.3 and therefore determines its size: a transistor T.sub.3 with too small a spread would not be able to deliver enough current and would lead to switching being slowed down. A transistor T.sub.3 with too large a spread could allow current to pass in the transient phase, but would have too high an input capacitance and would therefore switch more slowly. In practice, in the proposed exemplary circuit, the transistor T.sub.3 has a total gate spread that is eight times smaller than that of the transistor T.sub.2. It is therefore capable of conducting eight times less current, but has an input capacitance that is eight times lower.

(44) The cell of the invention therefore offers much higher efficiency and has many advantages.

(45) This is apparent in the curves of FIGS. 7 to 12 that are obtained via simulation by using, for the common elements, the same simulation data as the cell of the prior art illustrated in FIG. 1. In particular, the signal V.sub.IN has a duty cycle of 50% at a chopping frequency of 100 MHz. The pinch-off voltage V.sub.p of the transistors is of the order of 3.5 volts. The transistor T.sub.3 is chosen to be identical to the transistor T.sub.1, and the resistor R.sub.3 has a value of 35 ohms.

(46) These simulations have been carried out for the case in which Vss is chosen to be zero (FIG. 7), or negative (FIGS. 8 to 12).

(47) The drain-source voltage Vds2 and current Ids2 curves of the transistor T2 of FIGS. 7 and 8 illustrate the case in which the reference voltage Vss is zero and the case in which it is negative, respectively.

(48) Case in which Vss=0 V

(49) FIG. 7 illustrates the simulation of the cell when the voltage Vss corresponds to the reference potential of the electrical ground (0 volts).

(50) It shows that a drain-source current of the order of 370 milliamps and a switching time t.sub.ON.fwdarw.OFF of less than 1 nanosecond is obtained in the OFF state of the transistor T.sub.2. The drain-source voltage V.sub.ds2 in the OFF state is of the order of 45 volts. The total efficiency calculated for this cell under the simulation conditions is thus 84%.

(51) When the cell is in the OFF state, rather than having zero volts at the output Out of the cell, a non-zero voltage is found, due to T.sub.2 not being completely pinched off (it is at the turn-off limit).

(52) Case in which Vss is Negative

(53) FIG. 8 illustrates the case in which the source s.sub.1 of the input transistor is biased to a potential Vss that is more negative than electrical ground, to 6.5 volts in the example. As illustrated in FIG. 2, the voltage V.sub.DD switched at output is defined with respect to a ground at zero reference potential, GND. The input signal V.sub.IN is defined with respect to the reference potential Vss, so as to control switching to the ON state or OFF state, respectively, of the transistor T.sub.1 in an appropriate manner.

(54) In the example it varies between 5.5 volts (high level) and 10 volts (low level). The gate-source voltage of the transistor T.sub.1 thus varies between +1 V, switching to an ON state, and 3.5 volts, switching to an OFF state.

(55) By fixing Vss at a more negative potential, preferably in the vicinity of 2Vp (in the example Vp is of the order of 3.5 volts), then when the cell is in the OFF state Vss contributes to improving the pinch-off of T.sub.2 in the OFF state, as is apparent from the equation EQ1 of Vgs.sub.2.sub._.sub.OFF given above. The electrical losses in the OFF state of the cell are thereby further decreased; the total efficiency of the cell is therefore improved.

(56) This is indeed what FIG. 8 shows: the current Ids.sub.2 in the OFF state is lower still than under the zero-Vss conditions of FIG. 7: it passes from 370 milliamps to about 60 milliamps. An efficiency of the cell that is equal to 90% is obtained, with an output power of 72 watts at the chopping frequency of 100 megahertz, which is very high performance and a marked improvement with respect to the efficiency of at best 77% obtained with the cell of the prior art (FIG. 1) for a comparable output power (75 watts).

(57) In practice, fixing the bias voltage Vss of the source of the transistor T.sub.1 at a zero voltage, or a more negative voltage, often close to 2Vp, may depend on the expected performance for a given application and/or the practical possibilities of having a negative reference voltage.

(58) FIGS. 9 to 12 show the forms of the input and output currents and voltages of the cell according to the invention of FIG. 5, obtained under the same simulation conditions as the cell of the prior art but taking a reference voltage Vss that is equal to 6.5 volts.

(59) They show various favourable operational aspects of the cell according to the invention, in particular:

(60) obtaining a squarewave output voltage V.sub.OUT whose width and repetition are controlled by the input voltage V.sub.IN with switching edges that are faster than those of the input voltage, allowing the constraints on the generation or shaping of the input signal to be relaxed;

(61) the change in state of the cell that is obtained for a very small variation, of the order of a few millivolts, in the input voltage V.sub.IN in the vicinity of a trigger threshold; high powers may thus be switched, many tens of watts in the example, at high frequency with minimal control energy, a few milliwatts in practice.

(62) FIG. 9 illustrates the input voltage curve V.sub.IN of the input signal applied to the gate g.sub.1 of the transistor T.sub.1. The input voltage V.sub.IN varies between a low level of 10 volts and a high level of 5.5 volts in order to make the transistor T.sub.1 switch between the OFF and ON states, with a time of variation between these two levels of the order of 3 to 4 nanoseconds. The voltage Vgs.sub.1 of the transistor T.sub.1 thus varies between 3.5 volts and +1 volts.

(63) FIG. 10 shows the input current curve I.sub.IN in the input capacitance of the transistor T.sub.1. It shows the current draw in the input capacitance of the transistor T.sub.1 when it starts to switch from the OFF state to the ON state, at the instant marked by the reference d in FIG. 9, causing the change in state of the cell from ON to OFF.

(64) FIG. 11 shows the voltage V.sub.OUT at the output node of the cell. Stated otherwise, it is the voltage measured across the source s.sub.2 of the power transistor T.sub.2: it takes a squarewave form, varying between a level close to V.sub.DD, when the power transistor T.sub.2 is in the ON state (equivalent to a short circuit); and close to zero volts when the power transistor T.sub.2 is in the OFF state. The switching edges are fast, of the order of 1 to 2 nanoseconds or even less than a nanosecond: the variations in the output signal are faster than those of the input signal V.sub.IN.

(65) FIG. 12 shows the output current I.sub.OUT drawn by the load (recall that the load is purely resistive in the example of the simulation); this current takes the form of a squarewave that follows the output voltage.

(66) Thus, the cell according to the invention is more efficient and has numerous advantages with respect to the cell according to the prior art.

(67) Its operation may still be adjusted by adding resistors to certain connections of the cell with a view to making these connections more resistive. These (optional) resistors allow fine adjustments to be made in practice, with a view to improving the efficiency of the cell according to the operating conditions of use. These resistors mainly improve the stability margin of the transistors and limit the effects of overvoltages or bounces caused by parasitic inductances of the structure, which are detrimental to efficiency.

(68) FIG. 6 thus shows various resistors that could be added to the cell structure according to the invention. In particular:

(69) the connection between the gate g.sub.2 of the power transistor T.sub.2 and the self-biasing resistor R.sub.3 may comprise a resistor r.sub.1;

(70) the connection between the self-biasing resistor R.sub.3 and the source s.sub.3 of the transistor T.sub.3 may comprise a resistor r.sub.2;

(71) the connection between the drain d.sub.3 of the second transistor T.sub.3 and the source s.sub.2 of the power transistor T.sub.2 may comprise a resistor r.sub.3;

(72) the connection between the self-biasing resistor R.sub.3 and the gate g.sub.3 of the second transistor T.sub.3 may comprise a resistor r.sub.4 connected between this gate g.sub.3 and the resistor R.sub.3;

(73) the connection between the input port In and the gate g.sub.1 of the input transistor T.sub.1 (g.sub.1 control input of the current switch T.sub.1) may comprise a resistor r.sub.5.

(74) the connection between the drain d.sub.1 of the input transistor T.sub.1 and the resistor R.sub.3 may comprise a resistor r.sub.6;

(75) The value of each of these resistors r.sub.1 to r.sub.6 is determined in practice by simulating the operating conditions for a given application. Depending on the case, at the end of the simulation zero, one, multiple or all of these resistors will be determined to have a non-zero value.

(76) The switching cell described above may be used alone or with other cells of the same type. FIG. 13 thus illustrates the case of an electronic device in which multiple cells according to the invention are used in parallel, with their output ports all connected to a common output port. Each cell then additionally comprises a protection diode at the output.

(77) In the example illustrated, an electronic device thus comprises n cells in parallel, C.sub.1, C.sub.2, . . . C.sub.n. Each cell C.sub.i is controlled by a control signal VIN.sub.i specific thereto in order to switch a different voltage VDD.sub.i, where the index i is equal to 1, . . . n.

(78) The n cells are connected at output to one and the same output node Out.sub.E which is connected to a load embodied in this instance by a resistor R.sub.L. The protection diode D.sub.i of each cell C.sub.i is connected between an output node Out.sub.i of the cell (corresponding to the source s.sub.2 of the power transistor T.sub.2 of the cell) and the output node of the device, Out.sub.E.

(79) In such an assembly, if just one of the cells out of then cells is in the ON state, for example C.sub.2, and all of the other cells are in the OFF state, it is the voltage VDD.sub.2 switched by the cell in the ON state that is across the output node Out.sub.E: Vout.sub.E=VDD.sub.2.

(80) As all of the other cells are in the OFF state, the voltage across the output node of these cells is zero or close thereto (close to Vp): the protection diode of each of these OFF cells is therefore reverse biased, each having a negative voltage that is substantially equal to VDD.sub.2 across their terminals.

(81) If two (or more) cells are now on, for example the cells C.sub.2 and C.sub.n, where VDD.sub.2>VDD.sub.n, then as output it is still the highest voltage, VDD.sub.2 in the example, that is at the output, and the protection diode D.sub.n of the cell C.sub.n is reverse biased (its voltage is VDD.sub.nVDD.sub.2<0).

(82) This example illustrates that if the cell associated with the lowest voltage to be switched, VDD.sub.n in the example, is in the ON state, the voltage across the output node of the device will be equal to VDD.sub.n only if no other cell is in the ON state.

(83) In a variant, provision may be made for this cell C.sub.n that receives the lowest positive supply voltage to be switched VDD.sub.n to be formed by the single protection diode. This protection diode will then be directly connected between the positive supply voltage to be switched and the output of the cell.

(84) The cell C.sub.n may essentially consist of the protection diode D.sub.n which will then be directly connected between the voltage VDD.sub.n and the output node of the device. The diode Dn will then be on only if all of the other cells C.sub.1 to C.sub.n-1 are in the OFF state.

(85) As the cells are capable of switching high voltages, this assembly of n cells (or variant thereof) allows, for example, a digital-analog power converter as described in detail in the aforementioned application WO2012/072503 to be produced using simple logic.

(86) The invention described above thus proposes an especially efficient power switching cell with non-isolated control and a structure that remains compact and inexpensive: there is no complex signal shaping circuitry nor any switching time shift management; the additional transistor T.sub.3 is not a transistor having to switch power; the switching of the transistor T.sub.3, used as a variable resistor for the power transistor and the power transistor T.sub.2, is ensured using a current switch controlled by the input signal of the cell. This switch may be a transistor, as illustrated, and may be associated with an adjustable current source.

(87) This cell may be used alone or in multiple in numerous high-frequency power switching applications, but also, and a fortiori, for lower frequency applications.