SPECTRUM ANALYZER AND METHOD OF CONTROLLING THE SAME

Abstract

A spectrum analyzer having a memory function to adopt a digital-data-based frequency sweep scheme while achieving performance comparable to performance of a high-speed FFT spectrum analyzer, and a method of controlling the spectrum analyzer, in which the spectrum analyzer includes: an ADC for converting a BWP signal, which is at least one analog unit frequency band signal, into a digital data sample at a predetermined sample rate according to a span set by a user; a digital sweep part for sweeping the data sample passed through the ADC while digitally decimating the data sample through a decimation processing block having a two-stage cascaded structure, and processing the swept data sample to increase a frequency sweep speed; and a control unit for controlling the digital sweep part according to various items input, set, and selected by the user to perform spectrum analysis and output a spectrum analysis result.

Claims

1. A method of controlling a spectrum analyzer, the method comprising: (a) fixing a trace point (TP) determined in relation to a multiplication (TP.sub.1*TP.sub.2) of primary and secondary digital frequency sweep counts (TP.sub.1 and TP.sub.2) to a preset value when a span, which is a measurement target frequency bandwidth, a center frequency (f.sub.c), a resolution bandwidth (RBW), and a video bandwidth (VBW) are set; (b) calculating a number (N.sub.bwp) of bandwidth parts (BWP), which is a unit frequency bandwidth at every RF frequency sweep in an RF processing part, by N.sub.BWP = ceil(span/40 MHz); (c) calculating N.sub.d1 and N.sub.d2, which are first and second decimation rates, for each of the BWPs, and configuring an RBW filter and a VBW filter; (d) capturing Ns output samples of an ADC in a first input buffer at a synchronization time interval; (e) performing primary digital sweep on the samples stored in the first input buffer by an amount corresponding to a first frequency step, and decimating the samples through first CIC filtering using a first decimation rate (N.sub.d1); (f) capturing the samples decimated through the first CIC filtering in a second input buffer, performing secondary digital sweep on the samples stored in the second input buffer by an amount corresponding to a second frequency step, and decimating the samples through second CIC filtering using a second decimation rate (N.sub.d2); and (g) repeatedly performing the primary and secondary digital frequency sweeps and decimation processing until processing for all the BWPs is finished.

2. The method of claim 1, wherein TP ≤ TP.sub.1*TP.sub.2.

3. The method of claim 2, wherein the first frequency step is set to bin*TP.sub.2, where bin=span/TP, and the second frequency step is set to bin.

4. The method of claim 3, wherein the capturing is performed until a predetermined number (N.sub.s) of samples are filled in the first input buffer, and when a time interval ends during the capturing, the capturing is held and continuously performed at a next time interval.

5. The method of claim 3, wherein, for an output of the second CIC filtering, output samples of the second CIC filtering are repeatedly processed by sequentially passing through the RBW filter, an envelope detector, a third CIC filter, the VBW filter, and a detector until processing for all TP.sub.2 is finished.

6. The method of claim 5, wherein h[n]' , which is a coefficient of the RBW filter, is determined by h[n]' = h[n] .sub.* w[n]', the RBW filter is configured based on a window function of $w[n]=a_0-a_1\cos \left(\frac{2\pi n}{N}\right)+$ $a_2\cos \left(\frac{4\pi n}{N}\right)-a_3\cos \left(\frac{6\pi n}{N}\right),$ where a.sub.0=0.3635819, a.sub.1 =0.4891775, a.sub.2=0.1365995, and a.sub.3=0.0106411, a final window function is determined by w[n]' = w[n].sup.α (where α is a constant for obtaining a bandwidth of the RBW filter), H[n], which is a frequency domain value of the RBW filter, and a length of the filter are determined by a RBW sampling rate and the RBW, and h[n], which is a time domain value, is obtained through inverse fast Fourier transform (IFFT).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG. 1 is a block diagram showing a spectrum analyzer according to the present invention.

[0031] FIG. 2 is a flowchart for describing a method of controlling a spectrum analyzer according the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, a spectrum analyzer and a method of controlling the same according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0033] FIG. 1 is a block diagram showing a spectrum analyzer according to the present invention. As shown in FIG. 1, a spectrum analyzer according to the present invention may digitally operate based on a cascaded integrator comb (CIC) filter having a two-stage cascaded structure by taking only advantages of analog spectrum analysis and digital FFT spectrum analysis.

[0034] In detail, the spectrum analyzer according to the present invention may include: an input user interface (UI) 200 for receiving, from a user, a desired measurement item and various set values required for measuring the measurement item among items shown in Table 1, for example, a span, a resolution bandwidth (RBW), and a video bandwidth (VBW); an output UI 400 for displaying a measurement result to allow the user to recognize the measurement result; an RF processing part (not shown) for sweeping and outputting an input RF signal corresponding to at least one unit frequency band (bandwidth part; hereinafter abbreviated as “BWP”), for example, 40 MHz according to the span set by the user; an analog-to-digital converter (ADC) 100 for converting each analog BWP signal, which is subject to RF sweep and output through the RF processing part, into a digital data sample at a predetermined sample rate, for example, a rate of 122.88 Msps; a digital sweep part DS for sweeping the data sample passed through the ADC 100 while digitally decimating the data sample through a decimation processing block having a two-stage cascaded structure, and processing the swept data sample to increase a frequency sweep speed; and a control unit 300 for controlling the RF processing part and the digital sweep part DS according to various items input, set, and selected by the user through the input UI 200 to perform spectrum analysis and display (output) a result of the spectrum analysis through the output UI 400.

[0035] In the above configuration, the RF processing part, the ADC 100, the control unit 300, and the digital sweep part DS may be configured together in the same main body, and the input UI 200 and the output UI 400 may be implemented as a terminal having a touch screen display panel, for example, a mobile terminal such as a smartphone, a notebook PC, or a tablet PC, which is separate from the main body of the spectrum analyzer, to transmit and receive UI data to and from the main body of the analyzer through short-range wireless communication such as Wi-Fi.

[0036] The digital sweep part DS may be implemented as a field programmable gate array (FPGA). In this case, the control unit 300 may be attached to the FPGA, or may be implemented as a CPU separate from the FPGA. A control method (algorithm) shown in FIG. 2 may be mounted in the control unit 300 in the form of firmware.

[0037] In detail, the digital sweep part DS may include: a gate unit 110 which functions to analyze a spectrum in synchronization with a desired signal section, for example, a down-link (DL) section or an up-link (UL) section of a 5G time division duplexing (TDD) signal; first and second decimation processing blocks 120 and 130 respectively including first and second input buffers 122 and 132 connected in the two-stage cascaded structure to store data used while sweeping frequencies, first and second direct digital synthesizers (DDS) 124 and 134 configured by a numerically-controlled oscillator (NCO) to function as a local oscillator (LO) for generating a conversion frequency which is required for frequency sweep, and first and second CIC filters 126 and 136 for reducing an amount of processing target data by performing decimation required for efficient data processing which is suitable for the RBW set by the user; an RBW filter 140 and a VBW filter 170 for performing RBW filtering and VBW filtering functions set by the user, respectively; an envelope detector 150 for extracting a waveform of an output signal by squaring a complex In-phase/Quadrature-phase (I/Q) value, which is an output of the RBW filter 140, and obtaining a square root of the squared I/Q value; a third CIC filter 160 for performing decimation or interpolation suitable for an RBW-to-VBW ratio (RBW/VBW) set by the user; and a detector 180 for extracting four VBW output values of a maximum value (max), a minimum value (min), a sum, and a sample for an output of the VBW filter 170.

[0038] Meanwhile, signal synchronization at the gate unit 110 may be performed by using various signals such as an internal frame synchronization signal, a GPS signal, 1-pulse-per-second (1PPS) signal, or a 5G new radio (NR) sync signal block (SSB) signal.

[0039] A decimation rate (N.sub.d1) of the first CIC filter and a decimation rate (N.sub.d2) of the second CIC filter may be multiplied to obtain a total decimation rate (N.sub.d=N.sub.d1 *N.sub.d2).

TABLE-US-00003 RB W Target Fr (RBWx8) CIC N.sub.d (=N.sub.d1*N.sub.d2) CIC#1 (N.sub.d1) CIC#1 Fr CIC#2 (N.sub.d2) CIC#2 Fr ⅟RBW Note 10 M 80 M 2^0 2^0 122.88 M 2^0 122.88 M 12.288 2x I/Q cal. consi dered 3 M 24 M 2^2 2^2 30.72 M 2^0 30.72 M 10.24 1 M 8 M 2^4 2^4 7.68 M 2^0 7.68 M 7.68 300 k 2.4 M 2^5 2^5 3.84 M 2^0 3.84 M 12.8 100 k 800 k 2^7 2^5 3.84 M 2^2 960 k 9.6 CIC# 2 activ ated 30 k 240 k 2^9 2^5 3.84 M 2^4 240 k 8 10 k 80 k 2^10 2^5 3.84 M 2^5 120 k 12 3 k 24 k 2^12 2^6 1.92 M 2^6 30 k 10 1 k 8 k 2^14 2^7 960 k 2^7 7.5 k 7.5 300 2.4 k 2^15 2^8 480 k 2^7 3.7 k 12.3333 SPA N limit ed 100 800 2^17 2^9 240 k 2^8 937.5 9.375 30 240 2^19 2^10 120 k 2^9 234.375 7.8125 10 80 2^20 2^10 120 k 2^10 117.1875 11.7188 3 24 2^22 2^11 60 k 2^11 29.2969 9.7656 1 8 2^24 2^12 30 k 2^12 7.3242 7.3242

[0040] The first input buffer 122 and the second input buffer 132 may be implemented as DDR memories. The data stored in the first and second input buffers 122 and 132 may be reused without receiving additional data during the digital frequency sweep, so that a frequency sweep time may be reduced by the decimation rate of the first CIC filter 126 (1/N.sub.d1). The maximum number of stored samples in the first input buffer 122 may correspond to, for example, the number of output samples of the ADC 100 for 2 seconds (122.88 Ms*2), and the maximum number of stored samples in the second input buffer 132 may correspond to, for example, the number of output samples of the first CIC filter for 2 seconds (3.84 Ms*2).

[0041] Meanwhile, the decimation rates (N.sub.d1 and N.sub.d2) of the first and second CIC filters 126 and 136 and the total decimation rate (N.sub.d=N.sub.d1*N.sub.d2), which is the multiplication of the decimation rates (N.sub.d1 and N.sub.d2), to support various RBWs for ADC output data having a sample rate of F.sub.s = 122.88 MHz may be determined as shown in Table 3 below.

Table 3

[0042] The results of Table 3 may be determined such that the total number of calculations for one frequency sweep is minimized as shown in Mathematical formula 2 below.

[00004]$\begin{array}{l}{C}_1=N_S\ast TP=k\ast N_{d1}\ast N_{d2}\ast TP\\ C_2=k\ast \left(N_{d1}+N_{d2}\ast T{p}_2\right)\ast T{P}_1\\ =k\ast \left(N_{d1}/T{P}_2+N_{d2}\right)\ast T\text{}P\\ TP=T{P}_1\ast T{P}_2,N_S=k\ast \text{}{N}_{d1}\ast N_{d2}\\ \end{array}$

[0043] In Mathematical formula 2, C.sub.1 denotes a calculation amount when a decimation processing block having a single-stage structure is provided, and C.sub.2 denotes a calculation amount when a decimation processing block having a two-stage cascaded structure is provided as shown in FIG. 1. In addition, TP.sub.x (trace point), that is, TP.sub.1 and TP.sub.2 (TP<TP.sub.1*TP.sub.2) denote frequency sweep counts of the first and second decimation processing blocks 120 and 130, respectively, and Ns denotes the number of processing samples.

[0044] Therefore, calculation efficiency of the spectrum analyzer according to the present invention may be determined as shown in Mathematical formula 3 below, so that a time required for the frequency sweep can be significantly reduced.

[00005]$C_1/C_2~N_{d1}$

[0045] In more detail, due to characteristics of the swept spectrum analyzer, input data is required for each sweep point, and an identical calculation process has to be repeatedly performed at all sweep points until all input data is processed. However, in the present invention, the input buffer is used to reuse the sample stored in the second decimation processing block 130 at all sweep points, so that no input/output time of the first decimation processing block 120 is required to obtain a new sample. As a result, the frequency sweep time can be reduced by the decimation rate (N.sub.d1) of the first decimation processing block 120. For example, since RBW/VBW = 1 Hz in the case of the lower item in Table 2, a frequency sweep time through a conventional analog swept spectrum analyzer is 4000 [sec], whereas a frequency sweep time according to the present invention can be reduced by 4000[sec]/4096, that is, reduced to within 1 [sec].

[0046] Meanwhile, since DL and UL signal frequencies of a frequency division duplexing (FDD) communication signal are separated from each other, and the frequencies are constant, a starting point of a signal is meaningless to the swept spectrum analyzer. However, in order to support analysis of a TDD communication signal such as a 5G signal, as described above, a gated spectrum analysis scheme in which a signal spectrum is calculated only in a predetermined time interval such as the DL or the UL has to be applied.

[0047] In addition, in order to support a wider span than an instantaneous frequency supported by the ADC 100, the RF sweep is required in the RF processing part. As described above, after one RF sweep frequency bandwidth, which is the BWP, is defmed, a span bandwidth has to be divided into BWPs, and the BWPs has to be repeatedly processed. ADC samples for one BWP may be digitally batch-processed in the digital sweep part DS which is implemented as the FPGA.

[0048] FIG. 2 is a flowchart for describing a method of controlling a spectrum analyzer according the present invention. The method may be performed by the control unit 300.

[0049] First, in step S10, a TP determined in relation to a multiplication of frequency sweep counts of the first and second decimation processing blocks 120 and 130 may be fixed to a preset value, for example, 1001. The TP may be determined in relation to a horizontal resolution of a display screen. In this case, the TP may be greater than or equal to TP.sub.1*TP.sub.2, and when the TP is equal to TP.sub.1*TP.sub.2, TP.sub.1 and TP.sub.2 are both divisors of TP.

[0050] Next, in step S20, by using the set value in step S10, the number (N.sub.bwp) of BWPs, which has a unit frequency bandwidth, for example, a bandwidth of 40 MHz at every RF frequency sweep in the RF processing part, may be calculated by Mathematical formula 4 below.

[00006]${\text{N}}_{\text{BWP}}=\text{ceil}(\text{span}/40\text{MHz)}$

[0051] Then, in step S30, N.sub.d1 and N.sub.d2, which are the decimation rates of the first and second decimation processing blocks 120 and 130, may be calculated for each of the BWPs, and the RBW filter 140 and the VBW filter 170 may be configured, in which N.sub.d1 and N.sub.d2 may be calculated by Table 3 above. In this case, individual BWPs may have mutually different RBWs and VBWs, and N.sub.d1 and N.sub.d2 are determined accordingly.

[0052] When initialization is completed through the above steps, the control unit 300 may activate the FPGA constituting the digital sweep part DS over a data stabilization time according to the RF frequency sweep.

[0053] In detail, the control unit 300 may capture Ns output samples of the ADC 100, which operates at a predetermined sampling rate, for example, 122.88 Msps, in the first input buffer 122, which is implemented as, for example, a DDR memory, at a time interval in which synchronization is set by the gate unit 110 (step S40). When a time interval ends during the capturing, the capturing may be held and continuously performed at a next time interval. In this way, the capturing may be completed when a predetermined number (N.sub.s) of samples are filled in the first input buffer 122, in which the maximum number of stored samples in the first input buffer 122 may correspond to, for example, the number of samples for 2 seconds (122.88 Ms*2).

[0054] Next, a frequency step may be set to a predetermined unit, for example, bin*TP.sub.2, where bin=span/TP, and the first DDS 124 may sweep the samples stored in the first input buffer 122 by an amount corresponding to each frequency step and output the swept samples to the first CIC filter 126. Thereafter, the first CIC filter 126 may decimate input samples by using a first decimation rate (N.sub.d1) calculated in step S30, so that the number of output samples of the first CIC filter 126 can be reduced to Ns/N.sub.d1.

[0055] Then, the samples output from the first CIC filter 126 may be captured in the second input buffer 132 of the second decimation processing block 130 (step S50), so that a required storage space of the second input buffer 132 can be reduced to Ns/N.sub.d1. The maximum number of stored samples in the second input buffer 132 may correspond to, for example, the number of output samples of the first CIC filter 126 for 2 seconds (3.84 Ms*2).

[0056] Next, the frequency step may be set to a predetermined unit, for example, bin, the second DDS 134 may sweep the samples stored in the second input buffer 132 by an amount corresponding to each frequency step and output the swept samples to the second CIC filter 136, and the second CIC filter 136 may decimate input samples by using a second decimation rate (N.sub.d2) calculated in step S30 (step S60). Accordingly, the number of output samples of the second CIC filter 136 can be reduced to N.sub.s/(N.sub.d1*N.sub.d2).

[0057] Then, in step S70, for an output of the second CIC filter 136, output samples of the second CIC filter 136 may be processed by sequentially passing through the RBW filter 140, the envelope detector 150, the third CIC filter 160, the VBW filter 170, and the detector 180. Subsequently, in step S80, it is determined whether processing for all TP.sub.2 is finished.

[0058] As a result of the determination in step S80, step S60 and subsequent steps thereof may be repeatedly performed when the processing for all TP.sub.2 is not finished, whereas the process may proceed to step S90 to determine whether processing for all TP is finished when the processing for all TP.sub.2 is finished.

[0059] As a result of the determination in step S90, step S50 and subsequent steps thereof may be repeatedly performed when the processing for all TP is not finished, whereas the process may proceed to step S100 to determine whether processing for all the BWPs is finished when the processing for all TP is finished.

[0060] As a result of the determination in step S100, step S30 and subsequent steps thereof may be repeatedly performed when the processing for all the BWPs is not finished, whereas the process may proceed to step S110 to finally output a processing result of the detector 180 and terminate a program when the processing for all the BWPs is finished.

[0061] Meanwhile, in step S70, the RBW filter 140 has to be able to process exactly by an amount corresponding to the RBW for an arbitrary sampling rate. Accordingly, the RBW filter 140 may be configured based on a Blackman-Harris window function as shown in Mathematical formula 5 below.

[00007]$w[n]=a_0-a_1\cos \left(\frac{2\pi \text{}n}{N}\right)+a_2\cos \left(\frac{4\pi \text{}n}{N}\right)-a_3\cos \left(\frac{6\pi \text{}n}{N}\right),$

where a.sub.0 = 0.3635819, a.sub.1 = 0.4891775, a.sub.2 = 0.1365995, and a.sub.3 = 0.0106411

[0062] A final window function may be determined by Mathematical formula 6 below.

[00008]$\text{w}[\text{n}]\prime =\text{w}[\text{n}]{}^{\text{α}}$

[0063] In Mathematical formula 6, α denotes a constant for obtaining a bandwidth of the RBW filter, and an optimal value has to be found through Mathematical formula 6. Thereafter, H[n], which is a frequency domain value of the RBW filter, and a length of the filter may be determined by a RBW sampling rate and the RBW, and h[n], which is a time domain value, may be obtained through inverse fast Fourier transform (IFFT). In addition, h [n]', which is a final coefficient of the RBW filter, may be obtained by Mathematical formula 7 below.

[00009]$h[n]\prime =h[n]\ast w[n]\prime$

[0064] Finally, the configuration of the RBW filter is completed by appropriately determining α such that a final bandwidth of the RBW filter satisfies a standard of -3 dBc.

[0065] Although the spectrum analyzer and the method of controlling the same according to the exemplary embodiments of the present invention have been described in detail with reference to the accompanying drawings, the description is provided for illustrative purposes only, and various changes or modifications can be made without departing from the scope of the technical idea of the present invention. Therefore, it is to be understood that the scope of the present invention is defined by the appended claims. For example, although the decimation block has been described as having the two-stage cascaded structure in the above embodiments, the decimation block may have a cascaded structure with three or more stages.

[0066] In addition, since terms such as ‘part’ and ‘block’ are arbitrarily selected for convenience of logical or functional explanation, the terms should not be construed as limiting the scope of the present invention, and each functional configuration may be described as being integrated into larger units or divided into smaller units.