INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS

Abstract

An integrated circuit according to an embodiment includes: first through third basic tiles, the second basic tile being located between the first basic tile and the third basic tile, each of the basic tiles including a first logic block configured to perform a logical operation and a first switch block, the first switch block including a first switch circuit, the first switch circuit including: two-terminal switch elements arranged in a matrix form; input terminals, each of the input terminals being connected to one of terminals of each of the two-terminal switch elements aligned in the same column; and output terminals, each of the output terminals being connected to the other one of the terminals of each of the two-terminal switch elements aligned in the same row.

Claims

1. An integrated circuit comprising: first through third basic tiles, the second basic tile being located between the first basic tile and the third basic tile, each of the basic tiles including a first logic block configured to perform a logical operation and a first switch block, the first switch block including a first switch circuit, the first switch circuit including: two-terminal switch elements arranged in a matrix form; input terminals, each of the input terminals being connected to one of terminals of each of the two-terminal switch elements aligned in the same column; and output terminals, each of the output terminals being connected to the other one of the terminals of each of the two-terminal switch elements aligned in the same row; a first wiring line connecting the first switch circuit of the first basic tile to the first logic block of the first basic tile; a second wiring line connecting the first switch circuit of the first basic tile to the first switch circuit of the second basic tile; a third wiring line directly connecting the first switch circuit of the first basic tile to the first switch circuit of the third basic tile; a fourth wiring line connecting the first switch circuit of the second basic tile to the first logic block of the second basic tile; a fifth wiring line connecting the first switch circuit of the second basic tile to the first switch circuit of the third basic tile; and a sixth wiring line connecting the first switch circuit of the third basic tile to the first logic block of the third basic tile, wherein the third wiring line is connected to one of the input terminals of the first switch circuit of the second basic tile.

2. The integrated circuit according to claim , further comprising: a fourth basic tile located between the second basic tile and the third basic tile, the fourth basic tile including a second logic block configured to perform a logical operation and a second switch block, the second switch block including a second switch circuit, the second switch circuit including: two-terminal switch elements arranged in a matrix; input terminals, each of the input terminals being connected to one of terminals of each of the two-terminal switch elements aligned in the same column; and output terminals, each of the output terminals being connected to the other one of the terminals of each of the two-terminal switch elements aligned in the same row; a seventh wiring line connecting the second switch circuit of the fourth basic tile to the second logic block of the fourth basic tile; an eighth wiring line connecting the second switch circuit of the fourth basic tile to the first switch circuit of the second basic tile; and a ninth wiring line connecting the second switch circuit of the fourth basic tile to the first switch circuit of the third basic tile, wherein the third wiring line is connected to one of the input terminals of the second switch circuit of the fourth basic tile.

3. The integrated circuit according to claim 1, wherein the two-terminal switch elements are gate oxide film breakdown anti-fuse elements.

4. The integrated circuit according to claim 1, wherein the two-terminal switch elements are resistive change elements.

5. An integrated circuit comprising: a basic tile including a logic block configured to perform a logical operation and a switch block, the switch block including a switch circuit, the switch circuit including: two-terminal switch elements arranged in a matrix form; input terminals, each of the input terminals being connected to one of terminals of each of the two-terminal switch elements aligned in the same column; and output terminals, each of the output terminals being connected to the other one of the terminals of each of the two-terminal switch elements aligned in the same row; and a wiring line connecting the switch circuit and the logic block.

6. The integrated circuit according to claim 5, wherein the two-terminal switch elements are gate oxide film breakdown anti-fuse elements.

7. The integrated circuit according to claim 5, wherein the two-terminal switch elements are resistive change elements.

8. An electronic apparatus comprising: the integrated circuit according to claim 1; a memory storing a program; and a processor configured to perform processing on the integrated circuit in accordance with the program stored in the memory.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1 is a block diagram showing the configuration of an FPGA.

[0006] FIG. 2 is a block diagram showing an example configuration of a logical block.

[0007] FIG. 3A is a diagram showing an example of a hard macro.

[0008] FIG. 3B is a diagram showing another example of a hard macro.

[0009] FIG. 4 is a diagram showing an example of a basic tile.

[0010] FIG. 5 is a diagram showing an example of a multiplexer.

[0011] FIG. 6 is a diagram showing another example of a multiplexer.

[0012] FIG. 7 is a diagram showing an FPGA in which three basic tiles are transversely aligned.

[0013] FIG. 8 is a diagram for explaining a signal delay in the FPGA shown in FIG. 7.

[0014] FIG. 9 is a diagram showing an example of a switch block that solves a signal delay.

[0015] FIG. 10 is a diagram showing an FPGA that uses the switch block shown in FIG. 9.

[0016] FIGS. 11 and 12 are diagrams for explaining the problem with the FPGA shown in FIG. 10.

[0017] FIG. 13 is a circuit diagram showing a basic tile of an integrated circuit according to a first embodiment.

[0018] FIG. 14 is a diagram showing the cross-point switch circuit included in a switch block of the first embodiment.

[0019] FIG. 15 is a circuit diagram showing an example of a cross-point switch circuit.

[0020] FIG. 16 is a circuit diagram showing a switch circuit including write circuits.

[0021] FIG. 17 is a diagram for explaining writing in the switch circuit shown in FIG. 16.

[0022] FIG. 18 is a circuit diagram showing an integrated circuit according to a first embodiment.

[0023] FIG. 19 is a diagram for explaining the effects of the integrated circuit shown in FIG. 18.

[0024] FIG. 20 is a circuit diagram showing a integrated circuit according to a first modification of the first embodiment.

[0025] FIG. 21 is a circuit diagram showing a integrated circuit according to a second modification of the first embodiment.

[0026] FIG. 22 is a circuit diagram showing a integrated circuit according to a third modification of the first embodiment.

[0027] FIG. 23 is a block diagram showing an electronic apparatus according to a second embodiment.

DETAILED DESCRIPTION

[0028] An integrated circuit according to an embodiment includes: first through third basic tiles, the second basic tile being located between the first basic tile and the third basic tile, each of the basic tiles including a first logic block configured to perform a logical operation and a first switch block, the first switch block including a first switch circuit, the first switch circuit including: two-terminal switch elements arranged in a matrix form; input terminals, each of the input terminals being connected to one of terminals of each of the two-terminal switch elements aligned in the same column; and output terminals, each of the output terminals being connected to the other one of the terminals of each of the two-terminal switch elements aligned in the same row; a first wiring line connecting the first switch circuit of the first basic tile to the first logic block of the first basic tile; a second wiring line connecting the first switch circuit of the first basic tile to the first switch circuit of the second basic tile; a third wiring line directly connecting the first switch circuit of the first basic tile to the first switch circuit of the third basic tile; a fourth wiring line connecting the first switch circuit of the second basic tile to the first logic block of the second basic tile; a fifth wiring line connecting the first switch circuit of the second basic tile to the first switch circuit of the third basic tile; and a sixth wiring line connecting the first switch circuit of the third basic tile to the first logic block of the third basic tile, wherein the third wiring line is connected to one of the input terminals of the first switch circuit of the second basic tile.

[0029] Before embodiments of the present invention are described, the course of events before the present inventor achieved the present invention will be described below.

[0030] First, the configuration of a typical FPGA is described. As shown in FIG. 1, an FPGA 100 normally includes basic tiles 110 arranged in an array. Each basic tile 110 is connected to adjacent basic tiles 110 by wiring lines. Each basic tile 110 includes a logic block (hereinafter also referred to as LB) 120 and a switch block (hereinafter also referred to as SB) 130. Each logic block 120 is a block that performs a logical operation, and its basic configuration is formed with a look-up table including a truth table. Each switch block 130 controls the connection/disconnection of a wiring line connected to an adjacent basic tile 110 and enables transmission of a signal in any direction.

[0031] Also, each switch block 130 connects to each corresponding logic block 120. The logic blocks 120 and the switch blocks 130 can perform connection control in accordance with the data stored in the respective configuration memories.

[0032] As shown in FIG. 2, each logic block 120 includes a look-up table circuit 122 (hereinafter also referred to as the LUT circuit 122) and memories 124, for example. The LUT circuit 122 outputs information stored in a memory 124, in accordance with an input. It is possible to implement any appropriate function in the LUT circuit 122 by rewriting the information stored in the memory 124.

[0033] In addition to that, the logic block 120 may include flip flop circuits 126a and 126b, and a hard macro 128. The flip-flop circuit 126a is connected to an output terminal of the LUT circuit 122, and the flip-flop circuit 126b is connected directly to an input terminal of the logic block 120. Here, the hard macro 128 is a group of circuits that are designed in advance. For example, as shown in FIG. 3A, an example of the hard macro 128 is a half adder 128a including an AND gate 129a and an XOR (exclusive OR) gate 129b. Another example of the hard macro 128 is a full adder 128b including half adders 128a.sub.1 and 128a.sub.2, and an OR gate 129c, as shown in FIG. 3B.

[0034] Each switch block 130 includes multiplexer circuits (hereinafter also referred to as MUX circuits), for example. Each MUX circuit has a function to select one of the inputs connected thereto, and connect the selected input to an output. The switch block 130 includes the same number of MUX circuits as the number of the output terminals of the switch block 130. Also, the MUX circuits in the switch block 130 are connected to the output terminals of the logic block 120, to connect the output terminals of the logic block 120 to wiring lines. Inputting to the logic block 120 is achieved by inputting one or all of the output terminals of the MUX circuits to the logic block 120.

[0035] FIG. 4 shows an example of a switch block 130. This switch block 130 includes eight MUX circuits 131.sub.1 through 131.sub.8. The MUX circuits 131.sub.1 through 131.sub.8 each includes input terminals and one output terminal.

[0036] The input terminals of the MUX circuit 131.sub.1 are connected to a wiring line group 137 through which signals from the output terminals of the logic block 120 in the same basic tile are transferred, a wiring line 135.sub.S1 through which a signal input from the lower side is transferred, a wiring line 135.sub.N2 through which a signal input from the upper side is transferred, and a wiring line 135.sub.W2 through which a signal input from the left side is transferred, and the output terminal is connected to a wiring line 136.sub.E1 through which a signal to be transferred to the right side is output.

[0037] The input terminals of the MUX circuit 131.sub.2 are connected to the wiring line group 137 through which signals from the output terminals of the logic block 120 in the same basic tile are transferred, a wiring line 135.sub.S2 through which a signal input from the lower side is transferred, a wiring line 135.sub.N1 through which a signal input from the upper side is transferred, and a wiring line 135.sub.W1 through which a signal input from the left side is transferred, and the output terminal is connected to a wiring line 136.sub.E2 through which a signal to be transferred to the right side is output.

[0038] The input terminals of the MUX circuit 131.sub.3 are connected to the wiring line group 137 through which signals from the output terminals of the logic block 120 in the same basic tile are transferred, a wiring line 135.sub.S2 through which a signal input from the lower side is transferred, a wiring line 135.sub.E1 through which a signal input from the right side is transferred, and the wiring line 135.sub.W2 through which a signal input from the left side is transferred, and the output terminal is connected to a wiring line 136.sub.N1 through which a signal to be transferred to the upper side is output.

[0039] The input terminals of the MUX circuit 131.sub.4 are connected to the wiring line group 137 through which signals from the output terminals of the logic block 120 in the same basic tile are transferred, the wiring line 135.sub.S1 through which a signal input from the lower side is transferred, a wiring line 135.sub.E2 through which a signal input from the right side is transferred, and the wiring line 135.sub.W1 through which a signal input from the left side is transferred, and the output terminal is connected to a wiring line 136.sub.N2 through which a signal to be transferred to the upper side is output.

[0040] The input terminals of the MUX circuit 131.sub.5 are connected to the wiring line group 137 through which signals from the output terminals of the logic block 120 in the same basic tile are transferred, the wiring line 135.sub.E2 through which a signal input from the right side is transferred, the wiring line 135.sub.N1 through which a signal input from the upper side is transferred, and the wiring line 135.sub.S2 through which a signal input from the lower side is transferred, and the output terminal is connected to a wiring line 136.sub.W1 through which a signal to be transferred to the left side is output, and a wiring line 138 extending to an input terminal of the logic block 120.

[0041] The input terminals of the MUX circuit 131.sub.6 are connected to the wiring line group 137 through which signals from the output terminals of the logic block 120 in the same basic tile are transferred, the wiring line 135.sub.E1 through which a signal input from the right side is transferred, the wiring line 135.sub.N2 through which a signal input from the upper side is transferred, and the wiring line 135.sub.S1 through which a signal input from the lower side is transferred, and the output terminal is connected to a wiring line 136.sub.W2 through which a signal to be transferred to the left side is output, and the wiring line 138 extending to an input terminal of the logic block 120.

[0042] The input terminals of the MUX circuit 131.sub.7 are connected to the wiring line group 137 through which signals from the output terminals of the logic block 120 in the same basic tile are transferred, the wiring line 135.sub.E2 through which a signal input from the right side is transferred, the wiring line 135.sub.N2 through which a signal input from the upper side is transferred, and the wiring line 135.sub.W1 through which a signal input from the left side is transferred, and the output terminal is connected to a wiring line 136.sub.S1 through which a signal to be transferred to the lower side is output, and the wiring line 138 extending to an input terminal of the logic block 120.

[0043] The input terminals of the MUX circuit 131.sub.8 are connected to the wiring line group 137 through which signals from the output terminals of the logic block 120 in the same basic tile are transferred, the wiring line 135.sub.E1 through which a signal input from the right side is transferred, the wiring line 135.sub.N1 through which a signal input from the upper side is transferred, and the wiring line 135.sub.W2 through which a signal input from the left side is transferred, and the output terminal is connected to a wiring line 136.sub.S2 through which a signal to be transferred to the lower side is output, and the wiring line 138 extending to an input terminal of the logic block 120. Each of these MUX circuits 131 is formed with a CMOS circuit shown in FIG. 5, for example. The MUX circuit 131 shown in FIG. 5 includes four stages of select circuits 142.sub.1 through 142.sub.4, and eight inverters 145.sub.1 through 145.sub.8. Each select circuit 142.sub.i (i=1, 2, 3, 4) includes a memory M.sub.i, three inverters 144a.sub.i, 144b.sub.i, and 144c.sub.i, and 2.sup.4-i transfer gates 146.sub.ij (j=1, . . . , 2.sup.4-i. Each inverter 145.sub.i (i=1, . . . , 8) receives an input signal In.sub.i at the input terminal.

[0044] Each memory M.sub.i (i=1, . . . , 4) stores data 0 or data 1. Such data is stored into each memory M.sub.i from outside when the FPGA is used. The input terminals of the inverters 144a.sub.i and inverters 144c.sub.i (i=1, . . . , 4) are connected to the respective memories M. The input terminals of the inverters 144b.sub.i (i=1, . . . , 4) are connected to the output terminals of the inverters 144a.sub.i.

[0045] Each transfer gate 146.sub.ij (i=1, . . . , 4, j=1, . . . , 2.sup.4-i) includes a p-channel MOS transistor and an n-channel MOS transistor connected in parallel.

[0046] In the select circuit 142.sub.1, the gate of the p-channel MOS transistor of each of the transfer gates 146.sub.11, 146.sub.13, 146.sub.15, and 146.sub.17 is connected to the output terminal of the inverter 144c.sub.1, and the gate of the n-channel MOS transistor is connected to the output terminal of the inverter 144b.sub.1. Also, in the select circuit 142.sub.1, the gate of the p-channel MOS transistor of each of the transfer gates 146.sub.12, 146.sub.14, 146.sub.16, and 146.sub.18 is connected to the output terminal of the inverter 144b.sub.1, and the gate of the n-channel MOS transistor is connected to the output terminal of the inverter 144c.sub.1. The input terminals of the respective transfer gates 146.sub.1j (j=1, . . . , 8) are connected to the output terminals of the inverters 145.sub.j.

[0047] In the select circuit 142.sub.2, the gate of the p-channel MOS transistor of each of the transfer gates 146.sub.21 and 146.sub.23 is connected to the output terminal of the inverter 144c.sub.2, and the gate of the n-channel MOS transistor is connected to the output terminal of the inverter 144b.sub.2. Also, in the select circuit 142.sub.2, the gate of the p-channel MOS transistor of each of the transfer gates 146.sub.22 and 146.sub.24 is connected to the output terminal of the inverter 144b.sub.2, and the gate of the n-channel MOS transistor is connected to the output terminal of the inverter 144c.sub.2. The input terminals of the respective transfer gates 146.sub.2j (j=1, . . . , 4) are connected to the output terminals of the transfer gates 146.sub.12j-1 through 146.sub.12j.

[0048] In the select circuit 142.sub.3, the gate of the p-channel MOS transistor of the transfer gate 146.sub.31 is connected to the output terminal of the inverter 144c.sub.3, and the gate of the n-channel MOS transistor is connected to the output terminal of the inverter 144b.sub.3. Also, in the select circuit 142.sub.3, the gate of the p-channel MOS transistor of the transfer gate 146.sub.32 is connected to the output terminal of the inverter 144b.sub.3, and the gate of the n-channel MOS transistor is connected to the output terminal of the inverter 144c.sub.3. The input terminals of the respective transfer gates 146.sub.3j (j=1, 2) are connected to the output terminals of the transfer gates 146.sub.22j-1 through 146.sub.22j.

[0049] In the select circuit 142.sub.4, the gate of the p-channel MOS transistor of the transfer gate 146.sub.41 is connected to the output terminal of the inverter 144c.sub.4, and the gate of the n-channel MOS transistor is connected to the output terminal of the inverter 144b.sub.4. The input terminal of the transfer gate 146.sub.41 is connected to the output terminals of the transfer gates 146.sub.31 and 146.sub.32, and a signal Out is output from the output terminal of the transfer gate 146.sub.41.

[0050] FIG. 6 shows another example of a MUX circuit 131. This MUX circuit 131 has the same configuration as the MUX circuit shown in FIG. 5, except that the transfer gates 146.sub.ij (i=1, . . . , 4, j=1, . . . , 2.sup.4-i) are replaced with n-channel MOS transistors 148.sub.ij.

[0051] FIG. 7 shows an FPGA in which three basic tiles 110.sub.1, 110.sub.2, and 110.sub.3 are transversely aligned in this order. Each basic tile 110.sub.i (i=1, 2, 3) includes a logic block 120.sub.i and a switch block 130.sub.i. Each switch block 130.sub.i (i=1, 2, 3) has the same configuration as the switch block 130 shown in FIG. 4.

[0052] A case where a signal is sent from the logic block 120.sub.1 to the logic block 120.sub.3 in this FPGA is now described. There are several possible paths for sending this signal. However, the shortest route of any of the paths passes through the MUX circuits surrounded by dashed lines in the switch blocks 130.sub.1, 130.sub.2, and 130.sub.3, as indicated by the bold line in FIG. 8. Every time the signal passes through a MUX circuit, a circuit operating delay is added. As shown in this example in FIG. 8, a connection to the next logic block but one does not cause so long a delay. However, in a case where logic blocks at a long distance from each other, such as two logic blocks between which several tens of switch blocks exist, are connected, a long delay is caused.

[0053] To counter the problem of the delay, there has been a known technique of connecting to a basic tile located at a long distance without passing through any CMOS circuit (any MUX circuit in FIG. 8) in the switch blocks of the adjacent basic tiles (U.S. Pat. No. 5,914,616). According to this technique, a basic tile shown in FIG. 9 is prepared. This basic tile includes wiring lines 150 and 152 that enter MUX circuits 131b and 131d in the switch block 130 but do not pass through MUX circuits 131a and 131c to be connected to adjacent basic tiles, and wiring lines 154 and 156 that enter the MUX circuits 131a and 131c but do not pass through the MUX circuits 131b and 131d to be connected to adjacent basic tiles. FIG. 10 shows an FPGA in which such wiring lines are provided in each basic tile 110.sub.i (i=1, 2, 3). In FIG. 10, the above wiring lines are denoted by reference numeral B1. In this FPGA, the shortest path from the logic block 120.sub.1 to the logic block 120.sub.3 is the path indicated by the bold line in FIG. 11. That is, this shortest path passes through the MUX circuits A1 and A3 surrounded by dashed lines, but does not pass through the other MUX circuits. Accordingly, in a case where wiring lines that connect logic blocks at a long distance from each other (these wiring lines will be hereinafter referred to as long-distance wiring lines) are provided, delays become shorter than those in a case where any long-distance wiring lines are not prepared.

[0054] However, not all the paths between logic blocks necessarily have destinations at the ends of long-distance wiring lines. Therefore, an FPGA is designed so that a connection can be established from a long-distance wiring line to a short-distance wiring line, or a connection can established from a switch block through which a long-distance wiring line passes to another long-distance wiring line. However, the area of a MUX circuit or the like greatly increases with an increase in the number of input terminals. Therefore, in a case where MUX circuits are used, connection destinations are normally limited. As can be seen from the circuit shown in FIG. 9, connections other than at the ends are limited to directions perpendicular to the long-distance wiring lines 150 and 152. Any desired wiring lines with limited connection destinations can be provided as above, but the paths might become longer due to the decrease in the degree of freedom in wiring. As shown in FIG. 12, (24) basic tiles 110.sub.11 through 110.sub.24 are arranged in a matrix, and a signal is sent from the logic block 120.sub.21 of the basic tile 110.sub.21 to the logic block 120.sub.24 of the basic tile 110.sub.24, for example. In this case, the path connecting the logic block 120.sub.21 of the basic tile 110.sub.21 to the logic block 120.sub.24 via the switch block 130.sub.22 of the basic tile 110.sub.22, the switch block 130.sub.23 of the basic tile 110.sub.23, and the switch block 130.sub.24 of the basic tile 110.sub.24 is normally the shortest. However, if a signal from above the basic tile 110.sub.13 is input to the switch block 130.sub.23 of the basic tile 110.sub.23 through a path 160, another path 162 is used. This path 162 is connected from the logic block 120.sub.21 of the basic tile 110.sub.21 to the logic block 120.sub.24 of the basic tile 110.sub.74 via the switch block 130.sub.22 of the basic tile 110.sub.22, the switch block 130.sub.12 of the basic tile 110.sub.12, the switch block 130.sub.13 of the basic tile 110.sub.13, and the switch block 130.sub.14 of the basic tile 110.sub.14. Therefore, the path 162 extends for a longer distance than in a case where the switch block 130.sub.23 of the basic tile 110.sub.23 is not used. This will increase not only the delay but also unnecessary paths. As a result, the hardware resources might be consumed, or the number of wiring lines used might be increased.

[0055] In view of this, the inventor has made intensive studies, and discovered an integrated circuit that can reduce or prevent the signal delay even when a signal is transmitted via a large number of switch blocks. This integrated circuit will be described below as an embodiment.

[0056] The following is a description of embodiments, with reference to the accompanying drawings.

First Embodiment

[0057] FIG. 13 shows an integrated circuit according to a first embodiment. The integrated circuit of the first embodiment is an FPGA, and includes basic tiles 110 arranged in a matrix as in the case illustrated in FIG. 1. However, only one basic tile is shown in FIG. 13. This basic tile 110 is connected to adjacent basic tiles (now shown) by wiring lines. Each basic tile 110 includes a logic block 120 and a switch block 130.

[0058] The switch block 130 of the first embodiment includes a switch circuit 130A.

[0059] This switch circuit 130A includes a switch circuit 130B shown in FIG. 14, and inverters 170 that are connected to the input wiring lines and the output wiring lines of the switch circuit 130B, and shape a signal waveform. In a case where there is no need to shape a signal waveform, the inverters 170 may not be prepared.

[0060] The switch circuit 130A receives all the signals 180a through 180e that are input to the switch block 130, and signals 185a through 185h that are transferred through all the long-distance wiring lines passing through the switch block 130.

[0061] The switch circuit 130B shown in FIG. 14 includes switch element circuits 140 arranged in a matrix. The switch element circuits 140 aligned in the same row are connected to one output wiring line (output terminal). For example, in FIG. 14, the switch element circuits 140 aligned in the (2i-1)th row (i=1, . . . , 6) from the top are connected to a row wiring line 135.sub.2i-1 through which a signal is output to the left, and the switch element circuits 140 aligned in the 2ith row are connected to a row wiring line 135.sub.2i through which a signal is output to the right. The switch element circuits 140 aligned in the (2j-1)th column (j=1, . . . , 5) from the left are connected to a column wiring line 133.sub.2j-1, and the switch element circuits 140 aligned in the 2jth column are connected to a column wiring line 133.sub.2j. That is, the switch element circuits 140 are provided in the cross regions between wiring lines 133.sub.1 through 133.sub.10 and row wiring lines 135.sub.1 through 135.sub.12. Each switch element circuit 140 determines the existence/nonexistence of a connection between the corresponding wiring line among the column wiring lines 133.sub.1 through 133.sub.10 and the corresponding wiring line among the row wiring lines 135.sub.1 through 135.sub.12. It should be noted that the switch element circuits 140 aligned in the first row from the top and the switch element circuits 140 aligned in the second row have the same functions as those of the MUX circuits 131.sub.1 through 131.sub.8 and 131 shown in FIGS. 4 through 6, for example.

[0062] In this manner, all the inputs to the switch circuit 130B shown in FIG. 14 can be connected to all the outputs. A switch circuit that includes switch elements circuits arranged in the cross regions between a set of wiring lines and another set of wiring lines, and has all the inputs connectable to all the outputs as above is called a cross-point switch circuit.

[0063] In this embodiment, each switch element circuit 140 has a two-terminal switch element.

[0064] A two-terminal switch element occupies a smaller area than a MUX circuit, and accordingly, the area occupied by the entire integrated circuit can be made smaller. Each two-terminal switch element may be a variable resistance element such as a magnetic tunnel junction (MTJ) element, a resistive random-access memory (ReRAM) element, an oxidation-reduction resistive change element, an ion-conduction resistive change element, or a phase-change element, or an anti-fuse element such as a gate oxide film breakdown transistor. In this manner, an increase in the area can be prevented.

[0065] A ReRAM element (resistive change element) has a structure in which a resistive change layer is interposed between two electrodes. As a voltage is applied between the two electrodes, the electrical resistance of the resistive change layer interposed between the two electrodes changes. A gate oxide film breakdown anti-fuse element is a MOS transistor having a gate oxide film. At least the source or the drain of the anti-fuse element serves as a first terminal, and the gate serves as a second terminal.

[0066] FIG. 15 shows a specific example of a switch circuit 1303 in which two-terminal switch elements are used as switch element circuits 140. The switch circuit 130B of this specific example includes two-terminal switch elements (hereinafter also referred to simply as switch elements) 10.sub.11 through 10.sub.22 arranged in a (22) matrix, inverters 22.sub.1 and 22.sub.2, cutoff transistors 26.sub.1 and 26.sub.2, inverters 28.sub.1 and 28.sub.2, and wiring lines 34.sub.1, 34.sub.2, 35.sub.1, and 35.sub.2.

[0067] The wiring lines 34.sub.1 and 34.sub.2 intersect with the wiring lines 35.sub.1 and 35.sub.2. The two-terminal switch elements 10.sub.11 through 10.sub.22 are disposed in the cross regions between the wiring lines 34.sub.1 and 34.sub.2 and the wiring lines 35.sub.1 and 35.sub.2. The first terminal of each two-terminal switch element 10, (i, j=1, 2) is connected to the wiring line 34.sub.j, and the second terminal is connected to the wiring line 35.sub.i.

[0068] Each inverter 22.sub.j (j=1, 2) receives an input signal In.sub.j at the input terminal, and the output terminal thereof is connected to the wiring line 34.sub.j. As for each cutoff transistor 26.sub.i (i=1, 2), one of the source and the drain is connected to the wiring line 35.sub.i, the other one of the source and the drain is connected to the input terminal of the inverter 28.sub.i, and the gate is subjected to a control voltage V.sub.i. An output signal Out.sub.i is output from the output terminal of each inverter 28.sub.i (i=1, 2).

[0069] In the switch circuit 130B shown in FIG. 15, only one switch element of the two-terminal switch elements aligned in the same row can be put into a low-resistance state.

[0070] When input signals In.sub.1 and In.sub.2 are input to the switch circuit 130B having the above configuration, signals corresponding to the resistance states of the switch elements 10.sub.11 through 10.sub.22 are output as output signals Out.sub.1 and Out.sub.2.

[0071] In a case where gate oxide film breakdown anti-fuse elements are used as the switch elements 10.sub.ij (i, j=1, 2), if the write voltage of the switch elements 10.sub.ij (i, j=1, 2) is higher than the breakdown voltage of the gate oxide films of the anti-fuse elements, the cutoff transistors 26.sub.1 and 26.sub.2 are preferably used for protecting the gate oxide films of the anti-fuse elements on which writing is not being performed. The cutoff transistors 26.sub.1 and 26.sub.2 are also used for protecting the inverters 28.sub.1 and 28.sub.2.

[0072] FIG. 16 shows a switch circuit 1308 including write circuits that perform writing on switch elements. The switch circuit 130B shown in FIG. 16 is the same as the switch circuit 130B shown in FIG. 15, except that resistive change elements are used as switch elements arranged in a (44) matrix, cutoff transistors 24.sub.j are newly provided between the wiring lines 34.sub.j (j=1, . . . , 4) and the inverters 22.sub.j, and p-channel MOS transistors 20.sub.1 through 20.sub.4 and n-channel MOS transistors 25.sub.1 through 25.sub.4 constituting the write circuits are further provided.

[0073] One of the source and the drain (the drain, for example) of each of the transistors 20.sub.i (i=1, . . . , 4) is connected to the corresponding wiring line 35.sub.i, the other one of the source and the drain (the source, for example) is subjected to a write voltage VR.sub.i, and the gate receives a row select signal Rselect. One of the source and the drain (the drain, for example) of each of the transistors 25.sub.j (j=1, . . . , 4) is connected to the corresponding wiring line 34.sub.j, the other one of the source and the drain (the source, for example) is subjected to a voltage VC.sub.j, and the gate receives a column select signal Cselect.sub.j. Each row select signal Rselect.sub.i (i=1, . . . , 4) and each column select signal Cselect.sub.j (j=1, . . . , 4) are sent from a row select driver 260 and a column select driver 270, respectively. The write voltage VR.sub.i (i=1, . . . , 4) is a power source selected by a row write power source select circuit 280, and the write voltage VC.sub.j (j=1, . . . , 4) is a power source selected by a column write power source select circuit 290. The write inhibition voltage Vinhibit that will be described later is also given by the row write power source select circuit 280 or the column write power source select circuit 290.

[0074] Referring now to FIG. 17, a method of performing writing on the switch circuit 130B having the above described configuration is described. FIG. 17 is a diagram for explaining a method of performing writing on the switch element 10.sub.11 indicated by a dashed-line circle.

[0075] The writing described herein is an example case where writing is performed on the switch element 10.sub.11. A voltage to put the transistor 20.sub.1 into an on-state, such as Vss, is applied as the row select signal Rselect.sub.1, and a voltage to put the transistor 25.sub.1 into an on-state, such as Vdd, is applied as the column select signal Cselect.sub.1. The write voltage VR.sub.1 is then applied to the source of the transistor 20.sub.1 in an on-state, and the voltage VC.sub.1 is applied to the source of the transistor 25.sub.1 in an on-state. This voltage VC.sub.1 is such a voltage that the voltage (=VR.sub.1VC.sub.1) to be applied between the two terminals of the switch element 10.sub.11 becomes higher than the threshold voltage for performing writing on the switch element 10.sub.11. That is, the threshold voltage is lower than VR.sub.1VC.sub.1. With this, writing on the switch element 10.sub.11 can be performed. A write inhibition voltage Vinhibit is applied to the two terminals of each of the other switch elements, to prevent wrong writing on any switch element other than the switch element on which writing is to be performed. Here, the write inhibition voltage Vinhibit satisfies the following conditions:

[0076] threshold voltage>VR.sub.1Vinhibit, and

[0077] threshold voltage>VinhibitVC.sub.1.

[0078] Since these voltages leak from the inverters 22.sub.1 through 22.sub.4 on the input side, the transistors 24.sub.1 through 24.sub.4 are necessary. At a time of writing, these transistors 24.sub.1 through 24.sub.4 are put into an off-state, and thus, are disconnected from the inverters 22.sub.1 through 22.sub.4. There is no possibility of the voltages leaking from the inverters 28.sub.1 through 28.sub.4 on the output side, because the gates of the transistors forming these inverters are connected to the wiring lines 35.sub.1 through 35.sub.4. However, in a case where the write voltages VR.sub.1 through VR.sub.4 are higher than the gate breakdown voltages of the transistors forming the above inverters, the inverters 22.sub.1 through 22.sub.4 break due to write operations.

[0079] To counter this, the cutoff transistors 26.sub.i (i=1, 2, 3, 4) are provided between the wiring lines 35.sub.i and the inverters 28.sub.i, as shown in FIG. 16. If the potential difference between the signal Vbst.sub.2 applied to the gate and the write voltage VR.sub.i (i=1, 2, 3, 4) is smaller than the gate breakdown voltage in each cutoff transistor 26.sub.i, breaking of the gate of the cutoff transistor 26.sub.i can be prevented. Further, where Vth represents the threshold voltage of each cutoff transistor 26.sub.i (i=1, 2, 3, 4), only a voltage Vbst.sub.2Vth is applied to the inverter 28.sub.i at a maximum. Therefore, if Vbst.sub.2 is lower than the gate breakdown voltage of the transistor forming the inverter 28 (i=1, 2, 3, 4), breaking of the inverter 28.sub.i (i=1, 2, 3, 4) can also be prevented.

[0080] As described above, in the integrated circuit of the first embodiment, each switch block 130 includes a cross-point switch circuit 130A. As shown in FIG. 13, this switch circuit 130A receives all the signals 180a through 180e that are input to the switch block 130, and signals 185a through 185h that are transferred through all the long-distance wiring lines passing through the switch block 130. Also, all inputs from the logic block 120 are input to this switch circuit 130A, and the same number of outputs as the number of inputs to the logic block 120 are provided separately from wiring lines. In this manner, a connection to the logic block 120 is established. All the signals 180a through 180e input to the switch block 130 are output in any desired direction, such as a rightward direction, a leftward direction, an upward direction, or a downward direction, via the switch circuit 130A. The signals 185a through 185h transferred through all the long-distance wiring lines passing through the switch block 130 are input to the switch circuit 130A, and are output via other wiring lines in the same direction as the inputs to the switch block 130. That is, signals that are input to the switch block 130 can be output in any desired direction. Thus, the degree of freedom in designing the wiring lines connecting the basic tiles can be increased, and signal delays between logic blocks can be reduced or prevented.

[0081] Referring now to FIGS. 18 and 19, the above effects are described in detail. FIG. 18 shows an integrated circuit in which basic tiles that are the same as the basic tile shown in FIG. 13 are arranged in a (24) matrix. In each basic tile 110.sub.ij (i=1, 2, j=1, . . . 4), the switch block 130 can output the signals input thereto in any desired direction, as in the case described above with reference to FIG. 13. Thus, the degree of freedom in designing the wiring lines connecting the basic tiles can be increased.

[0082] FIG. 19 is a diagram for explaining that it is possible to reduce or prevent signal delays between logic blocks in the integrated circuit shown in FIG. 18. Referring to FIG. 19, a case where a signal is sent from the logic block 120.sub.21 of the basic tile 110.sub.21 to the logic block 120.sub.24 of the basic tile 110.sub.24 is described. As indicated by a path 210, a signal that is input from above the basic tile 110.sub.13 and passes through the switch block 130.sub.13 of the basic tile 110.sub.13 is input to the switch block 130.sub.23 of the basic tile 110.sub.23. In this case, the switch block 130.sub.23 cannot be used to access the target logic block 120.sub.24 to be connected, and the path takes a detour in a conventional integrated circuit, as described above with reference to FIG. 12.

[0083] In this embodiment, on the other hand, each switch block includes a cross-point switch circuit 130A, and a signal that is input to the switch block 130 can be output from any desired output terminal of the switch circuit 130A. Therefore, as shown in FIG. 19, a path 230 is formed to send a signal from the logic block 120.sub.21 of the basic tile 110.sub.21 to the logic block 120.sub.24 via the switch block 130.sub.21, the switch block 130.sub.22 of the basic tile 110.sub.22, the switch block 130.sub.23 of the basic tile 110.sub.23, and the switch block 130.sub.24 of the basic tile 110.sub.24. That is, as shown in FIG. 19, it is possible to connect to the switch block 130.sub.22 before reaching the switch block 130.sub.23 in the long-distance wiring line, and switch to another long-distance wiring line in the same direction. In this manner, the wiring path does not need to take a detour, and a delay in the path is reduced. Also, the wiring line 230, which is not used in the above described case, can be used, and the number of wiring lines to be used can be reduced. Although only one long-distance wiring line is shown in each direction in FIG. 19, more than one long-distance wiring line may exist in each direction, and, in such a case, the same effects as above can be achieved.

[0084] In an integrated circuit of a first modification shown in FIG. 20, a signal is sent through the switch blocks 130.sub.11 through 130.sub.22 in a direction perpendicular to the direction in which the signal is input. Even if the path is bent unlike the path shown in FIG. 19, the same effects can be achieved, as long as the relation of connection is the same as that shown in FIG. 19. FIG. 20 is a circuit diagram showing an integrated circuit according to a modification of the first embodiment.

[0085] In FIGS. 18 and 19, a long-distance wiring line connects the basic tiles 110.sub.21 and 110.sub.24, with the two basic tiles 110.sub.22 and 110.sub.23 being interposed in between. However, as in an integrated circuit of a second modification shown in FIG. 21, a long-distance wiring line may be designed to connect basic tiles between which three or more basic tiles are interposed. Alternatively, as in an integrated circuit of a third modification shown in FIG. 22, long-distance wiring lines may coexist with wiring lines that connect adjacent switch blocks.

[0086] As described so far, according to the first embodiments and the modifications thereof, it is possible to provide an integrated circuit that can reduce or prevent signal delays between logic blocks.

Second Embodiment

[0087] FIG. 23 shows an electronic apparatus according to a second embodiment. The electronic apparatus of the second embodiment includes a circuit 300 including the integrated circuit of any of the first embodiment and the modifications thereof, a microprocessor (hereinafter also referred to as micro-processing unit (MPU)) 320, a memory 340, and an interface (I/F) 360. These components are connected to one another via a bus line 380.

[0088] The MPU 320 operates in accordance with a program. The program for the MPU 320 to operate is stored beforehand into the memory 340. The memory 340 is also used as a work memory for the MPU 320 to operate. The I/F 360 communicates with an external device, under the control of the MPU 320.

[0089] The second embodiment can achieve the same effects as those of the first embodiment and the modifications thereof.

[0090] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.