Apparatus and methods for power amplifiers with positive envelope feedback

Abstract

Apparatus and methods for power amplifiers with positive envelope feedback are provided herein. In certain implementations, a power amplifier system includes a power amplification stage that amplifies a radio frequency signal, at least one envelope detector that generates one or more detection signals indicating an output signal envelope of the power amplification stage, and a wideband feedback circuit that provides positive envelope feedback to a bias of the power amplification stage based on the one or more detection signals. The power amplifier system further includes a supply modulator that controls a voltage level of a supply voltage of the power amplification stage based on the one or more detection signals such that the supply voltage is modulated with the output signal envelope through positive envelope feedback.

Claims

1. A mobile device comprising: a transceiver configured to generate a radio frequency input signal; a front end system including a power amplifier configured to amplify the radio frequency input signal to generate a radio frequency output signal, an output envelope detector configured to generate a detection signal based on detecting an envelope of the radio frequency output signal, the front end system further including a feedback circuit configured to bias the power amplifier with positive envelope feedback based on the detection signal, the front end system further including a bias inductor configured to provide the bias signal to a gate of a field-effect transistor of the power amplifier; and a power management system including a supply modulator configured to control a voltage level of a supply voltage of the power amplifier based on the detection signal.

2. The mobile device of claim 1 wherein the feedback circuit further includes a voltage divider configured to receive the detection signal and output the bias signal of the power amplifier.

3. The mobile device of claim 2 wherein the voltage divider includes a first resistor having a first end configured to receive the detection signal and a second end configured to generate the bias signal of the power amplifier.

4. A mobile device comprising: a transceiver configured to generate a radio frequency input signal; a front end system including a power amplifier configured to amplify the radio frequency input signal to generate a radio frequency output signal, an output envelope detector configured to generate a detection signal based on detecting an envelope of the radio frequency output signal, and a feedback circuit configured to bias the power amplifier with positive envelope feedback based on the detection signal, the feedback circuit including a first resistor having a first end configured to receive the detection signal and a second end configured to generate a bias signal of the power amplifier, the feedback circuit further including a voltage source and a second resistor electrically connected between the second end of the first resistor and the voltage source; and a power management system including a supply modulator configured to control a voltage level of a supply voltage of the power amplifier based on the detection signal.

5. The mobile device of claim 4 wherein the voltage source is configured to control a quiescent current of the power amplifier.

6. The mobile device of claim 4 wherein the front end system further includes a bias inductor configured to provide the bias signal to a gate of a field-effect transistor of the power amplifier.

7. The mobile device of claim 1 wherein the power amplifier includes an input stage and an output stage, the output envelope detector electrically connected to an output of the output stage.

8. The mobile device of claim 7 further comprising an input envelope detector electrically connected to an input of the output stage.

9. The mobile device of claim 7 further comprising an input envelope detector electrically connected to an input of the input stage.

10. The mobile device of claim 1 wherein the output envelope detector is a current mode detector.

11. A method of radio frequency signal amplification in a mobile device, the method comprising: generating a radio frequency input signal using a transceiver; amplifying the radio frequency input signal to generate a radio frequency output signal using a power amplifier; generating a detection signal based on detecting an envelope of the radio frequency output signal using an output envelope detector; biasing the power amplifier with positive envelope feedback based on the detection signal, the biasing of the power amplifier with positive envelope feedback including providing the detection signal to a voltage divider, and outputting a bias signal from the voltage divider; and based on the detection signal, controlling a voltage level of a supply voltage of the power amplifier using a supply modulator.

12. The method of claim 11 wherein the biasing the power amplifier further comprises providing the bias signal to a gate of a field-effect transistor of the power amplifier using a bias inductor.

13. A method of radio frequency signal amplification in a mobile device, the method comprising: generating a radio frequency input signal using a transceiver; amplifying the radio frequency input signal to generate a radio frequency output signal using a power amplifier; generating a detection signal based on detecting an envelope of the radio frequency output signal using an output envelope detector; biasing the power amplifier with positive envelope feedback based on the detection signal, the biasing the power amplifier with positive envelope feedback including providing a bias signal to a gate of a field-effect transistor of the power amplifier using a bias inductor; and based on the detection signal, controlling a voltage level of a supply voltage of the power amplifier using a supply modulator.

14. The method of claim 13 wherein biasing the power amplifier with positive envelope feedback includes providing the detection signal to a voltage divider, and outputting the bias signal from the voltage divider.

15. A power amplifier system comprising: a power amplifier configured to amplify a radio frequency input signal to generate a radio frequency output signal; an output envelope detector configured to generate a detection signal based on detecting an envelope of the radio frequency output signal; a feedback circuit configured to bias the power amplifier with positive envelope feedback based on the detection signal, the feedback circuit including a bias inductor configured to provide the bias signal to a gate of a field-effect transistor of the power amplifier; and a supply modulator configured to control a voltage level of a supply voltage of the power amplifier based on the detection signal.

16. The power amplifier system of claim 15 wherein the feedback circuit further includes a voltage divider configured to receive the detection signal and output the bias signal of the power amplifier.

17. The power amplifier system of claim 16 wherein the voltage divider includes a first resistor having a first end configured to receive the detection signal and a second end configured to generate a bias signal of the power amplifier.

18. A power amplifier system comprising: a power amplifier configured to amplify a radio frequency input signal to generate a radio frequency output signal; an output envelope detector configured to generate a detection signal based on detecting an envelope of the radio frequency output signal; a feedback circuit configured to bias the power amplifier with positive envelope feedback based on the detection signal, the feedback circuit including a first resistor having a first end configured to receive the detection signal and a second end configured to generate a bias signal of the power amplifier, the feedback circuit further including a voltage source and a second resistor electrically connected between the second end of the first resistor and the voltage source; and a supply modulator configured to control a voltage level of a supply voltage of the power amplifier based on the detection signal.

19. The power amplifier system of claim 18 wherein the voltage source is configured to control a quiescent current of the power amplifier.

20. The power amplifier system of claim 18 further comprising a bias inductor configured to provide the bias signal to a gate of a field-effect transistor of the power amplifier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of one embodiment of a mobile device.

(2) FIG. 2 is a schematic diagram of one embodiment of a power amplifier system.

(3) FIG. 3A is a schematic diagram of a power amplifier system with positive envelope feedback according to one embodiment.

(4) FIG. 3B is a schematic diagram of a power amplifier system with positive envelope feedback according to another embodiment.

(5) FIG. 3C is a schematic diagram of a power amplifier system with positive envelope feedback according to another embodiment.

(6) FIG. 3D is a schematic diagram of a power amplifier system with positive envelope feedback according to another embodiment.

(7) FIG. 3E is a schematic diagram of a power amplifier system with positive envelope feedback according to another embodiment.

(8) FIG. 3F is a schematic diagram of a power amplifier system with positive envelope feedback according to another embodiment.

(9) FIG. 3G is a schematic diagram of a power amplifier system with positive envelope feedback according to another embodiment.

(10) FIG. 3H is a schematic diagram of a power amplifier system with positive envelope feedback according to another embodiment.

(11) FIG. 4A is a schematic diagram of a power amplifier system with positive envelope feedback according to another embodiment.

(12) FIG. 4B is a schematic diagram of a power amplifier system with positive envelope feedback according to another embodiment.

(13) FIG. 4C is a schematic diagram of a power amplifier system with positive envelope feedback according to another embodiment.

(14) FIG. 5 is a schematic diagram of a power amplifier system with positive envelope feedback according to another embodiment.

(15) FIG. 6A is a graph showing a first example of power amplifier supply voltage versus time.

(16) FIG. 6B is a graph showing a second example of power amplifier supply voltage versus time.

(17) FIG. 7A is a schematic diagram of one embodiment of a packaged module.

(18) FIG. 7B is a schematic diagram of a cross-section of the packaged module of FIG. 7A taken along the lines 7B-7B.

DETAILED DESCRIPTION OF EMBODIMENTS

(19) The following detailed description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein can be embodied in a multitude of different ways, for example, as defined and covered by the claims. In this description, reference is made to the drawings where like reference numerals can indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings.

(20) A power amplifier can suffer from a trade-off between efficiency and linearity. Additionally, the efficiency and linearity trade-off can vary across a range of power levels of the power amplifier, and can be constrained with respect to available chip area, limitations on current consumption, and/or constraints on implementation complexity.

(21) Moreover, a modulation scheme used for radio frequency (RF) signals amplified by the power amplifier can impact the power amplifier's efficiency and linearity performance.

(22) For example, certain power amplifiers provide amplification to RF signals that are modulated using relatively complex modulation formats, such as high-level quadrature amplitude modulation (QAM), which can exhibit a relatively high peak to average power ratio (PAPR). Thus, although a power amplifier may be transmitting at a particular level of average power, an actual or instantaneous power level of the power amplifier can be several decibels (dBs) higher than the average power level. The instantaneous power level can vary based on an envelope frequency used for the modulated signal.

(23) Apparatus and methods for power amplifiers with positive envelope feedback are provided herein. In certain implementations, a power amplifier system includes a power amplification stage that amplifies a radio frequency signal, at least one envelope detector that generates one or more detection signals indicating an output signal envelope of the power amplification stage, and a wideband feedback circuit that provides positive envelope feedback to a bias of the power amplification stage based on the one or more detection signals. The power amplifier system further includes a supply modulator that controls a voltage level of a supply voltage of the power amplification stage based on the one or more detection signals such that the supply voltage is modulated with the output signal envelope through positive envelope feedback.

(24) Accordingly, the output signal envelope of the power amplifier is used to provide positive envelope feedback that modifies both the bias and the supply voltage of the power amplification stage.

(25) Providing positive envelope feedback in this manner can provide a number of advantages, such as enhanced linearity and/or efficiency. For example, the power amplifier systems herein can operate with superior combined linearity and efficiency over a range of power levels.

(26) Embodiments of power amplifier systems using positive envelope feedback as provided herein operate distinctly and differently from power amplifier systems using negative envelope feedback.

(27) The teachings herein are applicable to a wide variety of power amplifier systems, including power amplifier systems that provide amplification to RF signals associated with complex modulation formats and high PAPR waveforms.

(28) In certain implementations, the power amplifier system is implemented using a single multi-chip module (MCM), which can provide a relatively compact solution. In contrast, certain power amplifier systems that operate with envelope tracking are implemented using a power amplifier module and a separate envelope tracker module.

(29) Moreover, using output signal envelope to provide feedback can also provide a number of advantages relative to implementations using an input signal envelope to control supply voltage. For example, implementing the power amplifier in this manner can reduce complexity relative to configurations using an envelope tracker, which can use relatively complex digital signal processing (DSP) elements and/or complex analog circuitry for envelope shaping and/or phase compensation. Furthermore, using positive envelope feedback provides a number of advantages, including, but not limited to higher combined linearity and efficiency.

(30) FIG. 1 is a schematic diagram of one embodiment of a mobile device 20.

(31) The mobile device 20 includes a baseband system 1, a transceiver 2, a front end system 3, antennas 4, a power management system 5, a memory 6, a user interface 7, and a battery 8.

(32) Although the mobile device 20 illustrates one example of an RF system that can include one or more features of the present disclosure, the teachings herein are applicable to electronic systems implemented in a wide variety of ways.

(33) The mobile device 20 can be used communicate using a wide variety of communications technologies, including, but not limited to, 2G, 3G, 4G (including LTE, LTE-Advanced, and LTE-Advanced Pro), 5G, WLAN (for instance, Wi-Fi), WPAN (for instance, Bluetooth and ZigBee), WMAN (for instance, WiMax), and/or GPS technologies.

(34) The transceiver 2 generates RF signals for transmission and processes incoming RF signals received from the antennas 4. It will be understood that various functionalities associated with the transmission and receiving of RF signals can be achieved by one or more components that are collectively represented in FIG. 1 as the transceiver 2. In one example, separate components (for instance, separate circuits or dies) can be provided for handling certain types of RF signals.

(35) As shown in in FIG. 1, the transceiver 2 is connected to the front end system 3 and to the power management circuit 5 using a serial interface 9. All or part of the illustrated RF components can be controlled by the serial interface 9 to configure the mobile device 20 during initialization and/or while fully operational. In another embodiment, the baseband system 1 is additionally or alternative connected to the serial interface 9 and operates to configure one or more RF components, such as components of the front end system 3 and/or power management system 5.

(36) The front end system 3 aids is conditioning signals transmitted to and/or received from the antennas 4. In the illustrated embodiment, the front end system 3 includes one or more bias control circuits 10 for controlling power amplifier biasing, one or more power amplifiers (PAs) 11, one or more low noise amplifiers (LNAs) 12, one or more filters 13, one or more switches 14, and one or more duplexers 15. However, other implementations are possible.

(37) For example, the front end system 3 can provide a number of functionalities, including, but not limited to, amplifying signals for transmission, amplifying received signals, filtering signals, switching between different bands, switching between different power modes, switching between transmission and receiving modes, duplexing of signals, multiplexing of signals (for instance, diplexing or triplexing), or some combination thereof.

(38) In certain implementations, the mobile device 20 supports carrier aggregation, thereby providing flexibility to increase peak data rates. Carrier aggregation can be used for both Frequency Division Duplexing (FDD) and Time Division Duplexing (TDD), and may be used to aggregate a plurality of carriers or channels. Carrier aggregation includes contiguous aggregation, in which contiguous carriers within the same operating frequency band are aggregated. Carrier aggregation can also be non-contiguous, and can include carriers separated in frequency within a common band or in different bands.

(39) The antennas 4 can include antennas used for a wide variety of types of communications. For example, the antennas 4 can include antennas for transmitting and/or receiving signals associated with a wide variety of frequencies and communications standards.

(40) In certain implementations, the antennas 4 support MIMO communications and/or switched diversity communications. For example, MIMO communications use multiple antennas for communicating multiple data streams over a single radio frequency channel. MIMO communications benefit from higher signal to noise ratio, improved coding, and/or reduced signal interference due to spatial multiplexing differences of the radio environment. Switched diversity refers to communications in which a particular antenna is selected for operation at a particular time. For example, a switch can be used to select a particular antenna from a group of antennas based on a variety of factors, such as an observed bit error rate and/or a signal strength indicator.

(41) The mobile device 20 can operate with beamforming in certain implementations. For example, the front end system 3 can include phase shifters having variable phase controlled by the transceiver 2. Additionally, the phase shifters are controlled to provide beam formation and directivity for transmission and/or reception of signals using the antennas 4. For example, in the context of signal transmission, the phases of the transmit signals provided to the antennas 4 are controlled such that radiated signals from the antennas 4 combine using constructive and destructive interference to generate an aggregate transmit signal exhibiting beam-like qualities with more signal strength propagating in a given direction. In the context of signal reception, the phases are controlled such that more signal energy is received when the signal is arriving to the antennas 4 from a particular direction. In certain implementations, the antennas 4 include one or more arrays of antenna elements to enhance beamforming.

(42) The baseband system 1 is coupled to the user interface 7 to facilitate processing of various user input and output (I/O), such as voice and data. The baseband system 1 provides the transceiver 2 with digital representations of transmit signals, which the transceiver 2 processes to generate RF signals for transmission. The baseband system 1 also processes digital representations of received signals provided by the transceiver 2. As shown in FIG. 1, the baseband system 1 is coupled to the memory 6 of facilitate operation of the mobile device 20.

(43) The memory 6 can be used for a wide variety of purposes, such as storing data and/or instructions to facilitate the operation of the mobile device 20 and/or to provide storage of user information.

(44) The power management system 5 provides a number of power management functions of the mobile device 20. In certain implementations, the power management system 5 includes a power amplifier (PA) supply control circuit that controls the supply voltages of the power amplifiers 11. In the illustrated embodiment, the power management system 5 is configurable using the serial interface 9.

(45) As shown in FIG. 1, the power management system 5 receives a battery voltage from the battery 8. The battery 8 can be any suitable battery for use in the mobile device 20, including, for example, a lithium-ion battery. Although the power management system 5 is illustrated as separate from the front end system 3, in certain implementations all or part (for instance, a PA supply modulator) of the power management system 5 is integrated into the front end system 3.

(46) FIG. 2 is a schematic block diagram of one example of a power amplifier system 30. The illustrated power amplifier system 30 includes a baseband processor 21, an I/Q modulator 22, a power amplifier 23, a directional coupler 24, switches 25, an antenna 26, a mixer 27, and an analog-to-digital converter (ADC) 28.

(47) The baseband signal processor 21 can be used to generate an in-phase (I) signal and a quadrature-phase (Q) signal, which can be used to represent a sinusoidal wave or signal of a desired amplitude, frequency, and phase. For example, the I signal can be used to represent an in-phase component of the sinusoidal wave and the Q signal can be used to represent a quadrature-phase component of the sinusoidal wave, which can be an equivalent representation of the sinusoidal wave. In certain implementations, the I and Q signals can be provided to the I/Q modulator 22 in a digital format. The baseband processor 21 can be any suitable processor configured to process baseband signals. For instance, the baseband processor 21 can include a digital signal processor, a microprocessor, a programmable core, or any combination thereof. Moreover, in some implementations, two or more baseband processors 21 can be included in the power amplifier system 30.

(48) The I/Q modulator 22 can be configured to receive the I and Q signals from the baseband processor 21 and to process the I and Q signals to generate an RF signal. For example, the I/Q modulator 22 can include digital-to-analog converters (DACs) configured to convert the I and Q signals into an analog format, mixers for upconverting the I and Q signals to RF, and a signal combiner for combining the upconverted I and Q signals into an RF signal suitable for amplification by the power amplifier 23. In certain implementations, the I/Q modulator 22 can include one or more filters configured to filter frequency content of signals processed therein.

(49) The power amplifier 23 can receive the RF signal from the I/Q modulator 22, and when enabled can provide an amplified RF signal to the antenna 26 via the switches 25. The directional coupler 24 can be positioned between the output of the power amplifier 23 and the input of the switches 25, thereby allowing an output power measurement of the power amplifier 23 that does not include insertion loss of the switches 25. However, other configurations of power measurement are possible.

(50) In the illustrated configuration, the sensed output signal from the directional coupler 24 is provided to the mixer 27, which multiplies the sensed output signal by a reference signal of a controlled frequency. The mixer 27 operates to generate a downshifted signal by downshifting the sensed output signal's frequency content. The downshifted signal can be provided to the ADC 28, which can convert the downshifted signal to a digital format suitable for processing by the baseband processor 21.

(51) By including a feedback path between the output of the power amplifier 23 and the baseband processor 21, the baseband processor 21 can be configured to dynamically adjust the I and Q signals to optimize the operation of the power amplifier system 30. For example, configuring the power amplifier system 30 in this manner can aid in controlling the PAE and/or linearity of the power amplifier 23. However, other implementations of power control can be used.

(52) The power amplifier system 30 illustrates another example of an RF system that can include a power amplifier implemented in accordance with one or more features of the present disclosure.

(53) FIG. 3A is a schematic diagram of a power amplifier system 40 with positive envelope feedback according to one embodiment. The power amplifier system 40 includes an input stage 31, an output stage 32, an envelope detector 33, a supply modulator 34, a wideband feedback circuit 35, and a signal combiner or adder 36.

(54) The input stage 31 and the output stage 32 provide amplification to an RF input signal RF.sub.IN to generate an RF output signal RF.sub.OUT. The input stage 31 can also be referred to herein as a driver stage, and the output stage 32 can also be referred to herein as a power stage. The input stage 31 and the output stage 32 can be implemented using a wide variety of transistor types and/or amplifier topologies. Although an example using two power amplification stages is shown, the teachings herein are applicable to power amplifiers using more or fewer stages.

(55) As shown in FIG. 3A, the envelope detector 33 is electrically coupled to an output of the output stage 32. Additionally, the envelope detector 33 generates a detection signal indicating an output signal envelope of the output stage 32. In certain implementations, the envelope detector 33 senses an RF signal level or swing at the output of the output stage 32 and generates a baseband signal that changes in relation to the output signal envelope. The envelope detector 33 can be implemented in a wide variety of ways, such as using any suitable envelope detection circuit.

(56) The wideband feedback circuit 35 receives the detection signal, and generates a positive envelope feedback signal for providing positive envelope feedback to a bias of the output stage 32. In certain implementations, the wideband feedback circuit 35 generates a quiescent bias signal for the output stage 32, which is modulated by the output signal envelope.

(57) The wideband feedback circuit 35 can be implemented in a wide variety of ways. In certain implementations, the wideband feedback circuit 35 is implemented using resistive elements that provide positive envelope feedback over a wide range of frequencies. In one embodiment, the wideband feedback circuit 35 includes a voltage shifter that generates a dynamic voltage V.sub.DYN corresponding to a voltage shifted version of the detection signal.

(58) In one embodiment, the loop bandwidth associated with the wideband feedback circuit 35 is much larger than (for example, at least four times) a highest envelope frequency that the power amplifier system 40 is transmitting. Implementing the loop bandwidth in this manner provides dynamic biasing with relatively low distortion. In one example, the power amplifier system 40 transmits a 20 MHz envelope, and the loop bandwidth is at least about 80 MHz. However, other loop bandwidth values are possible, for instance, loop bandwidth values suitable for a particular application and/or implementation.

(59) The signal combiner 36 operates to combine the positive envelope feedback signal from the wideband feedback circuit 35 with the amplified RF signal from the input stage 31. The signal combiner 36 can be implemented in a wide variety of ways. In one embodiment, the signal combiner 36 adds the positive envelope feedback signal to the amplified RF signal from the input stage 31.

(60) The illustrated power amplifier system 40 further includes the supply modulator 34, which controls a voltage level of a supply voltage V.sub.SUP of the output stage 32 based on the detection signal through positive envelope feedback. The supply modulator 34 can be implemented in a wide variety of ways, such as using any suitable envelope modulation circuit.

(61) The wideband feedback circuit 35 dynamically controls the output stage's bias based on the output signal envelope of the output stage 32, and the supply modulator 34 operates to modulate the supply voltage V.sub.SUP with the output signal envelope.

(62) Accordingly, the output signal envelope is used to provide positive envelope feedback that modifies both the bias and the supply voltage of the output stage 32.

(63) Providing positive envelope feedback in this manner can provide a number of advantages, such as enhanced linearity and/or efficiency.

(64) For example, the power amplifier system 40 can operate with enhanced combined linearity and efficiency over a range of power levels. For instance, when the output stage 32 is transmitting at an instantaneous power level that is higher than the average power level, the positive envelope feedback operates to linearize the output stage 32 and/or enhance the output stage's power-added efficiency (PAE).

(65) Accordingly, the power amplifier system 40 can be used to amplify RF signals with complex modulation formats and/or high PAPR. In one embodiment, the RF input signal RF.sub.IN is modulated with a QAM modulation scheme of a level of at least 64. In certain implementations, the RF input signal RF.sub.IN corresponds to a 5G NR waveform.

(66) FIG. 3B is a schematic diagram of a power amplifier system 45 with positive envelope feedback according to another embodiment. The power amplifier system 45 of FIG. 3B is similar to the power amplifier system 40 of FIG. 3A, except that the power amplifier system 45 includes an implementation of a supply modulator 44 that not only receives the detection signal from the envelope detector 33, but also a conditioning signal (CONDITIONING).

(67) The supply modulator 44 uses the conditioning signal to selectively increase a DC voltage (for instance, a voltage level of a DC supply rail relative to a nominal voltage level) of the supply modulator 45 for large output signal envelopes. The increased DC headroom provided by the increase in DC voltage allows the supply voltage V.sub.SUP to follow the output signal envelope (as indicated by the detection signal from the envelope detector 33) with a larger DC headroom even when the output signal envelope is relatively high. Thus, the conditioning signal operates to provide coarse control over the supply voltage V.sub.SUP, while the detection signal from the envelope detector 33 operates to provide fine control over the supply voltage V.sub.SUP.

(68) In certain implementations, the supply modulator 44 selectively increases a DC supply rail of the supply modulator 44 based on a correlation with known signal statistics. The conditioning signal can be generated in a wide variety of ways, including, but not limited to, using an input envelope detector, and inter-stage envelope detector, a processor (for instance, a baseband processor), and/or other suitable circuitry.

(69) FIG. 3C is a schematic diagram of a power amplifier system 50 with positive envelope feedback according to another embodiment. The power amplifier system 50 of FIG. 3C is similar to the power amplifier system 45 of FIG. 3B, except that the power amplifier system 50 of FIG. 3C further includes an input envelope detector 43 for generating the conditioning signal. Although the input envelope detector 43 illustrates one implementation of suitable circuitry for generating the conditioning signal for the supply modulator 44, the conditioning signal can be generated in a wide variety of ways.

(70) FIG. 3D is a schematic diagram of a power amplifier system 55 with positive envelope feedback according to another embodiment. The power amplifier system 55 of FIG. 3D is similar to the power amplifier system 45 of FIG. 3B, except that the power amplifier system 55 of FIG. 3D further includes an inter-stage envelope detector 53 for generating the conditioning signal. The inter-stage envelope detector 53 illustrates another example of suitable circuitry for generating a conditioning signal. However, a conditioning signal for a supply modulator can be generated in a wide variety of ways.

(71) FIG. 3E is a schematic diagram of a power amplifier system 60 with positive envelope feedback according to another embodiment. The power amplifier system 60 of FIG. 3E is similar to the power amplifier system 45 of FIG. 3B, except that the power amplifier system 60 of FIG. 3E further includes a processor 51 for generating the conditioning signal. The processor 51 illustrates another example of suitable circuitry for generating a conditioning signal.

(72) In one embodiment, the processor 51 is a baseband processor (for example, the baseband processor 21 of FIG. 2) that also generates I and Q signals digitally representing the RF input signal RF.sub.IN. In certain implementations, the processor 51 includes an analog-to-digital converter (ADC) used to convert digital conditioning data into an analog conditioning signal suitable for use by the supply modulator 44.

(73) FIG. 3F is a schematic diagram of a power amplifier system 65 with positive envelope feedback according to another embodiment. The power amplifier system 65 of FIG. 3F is similar to the power amplifier system 45 of FIG. 3B, except that the power amplifier system 65 illustrates a specific implementation of a supply modulator 54.

(74) In the illustrated embodiment, the supply modulator 54 includes a battery 61 and a DC-to-DC converter 62. As shown in FIG. 3F, the DC-to-DC converter 62 receives a battery voltage V.sub.BATT from the battery 61, and generates the supply voltage V.sub.SUP by regulating the battery voltage V.sub.BATT based on the conditioning signal and the detection signal. In certain implementations, the conditioning signal provides coarse adjustment to regulation of the DC-to-DC converter 62, and the detection signal provides fine adjustment to the regulation of the DC-to-DC converter 62. The DC-to-DC converter 62 can be implemented in a wide variety of ways, including, but not limited to, using a buck converter, a boost converter, and/or a buck-boost converter.

(75) Although FIG. 3F illustrates one implementation of a supply modulator, the power amplifier systems herein can include supply modulators implemented in a wide variety of ways.

(76) FIG. 3G is a schematic diagram of a power amplifier system 70 with positive envelope feedback according to another embodiment. The power amplifier system 70 of FIG. 3G is similar to the power amplifier system 40 of FIG. 3A, except that the power amplifier system 70 includes an envelope detector 73 that generates a first detection signal for the wideband feedback circuit 35 and a second detection signal for the supply modulator 34.

(77) In certain implementations, different amounts and/or types of conditioning (for example, shaping, delay control, scaling, and/or other conditioning) is provided to the first detection signal relative to the second detection signal, thereby helping to provide detection signals suitable for handling by the wideband feedback circuit 35 and the supply modulator 34.

(78) FIG. 3H is a schematic diagram of a power amplifier system 75 with positive envelope feedback according to another embodiment. The power amplifier system 75 of FIG. 3H is similar to the power amplifier system 40 of FIG. 3A, except that the power amplifier system 75 includes a first envelope detector 33a that generates a first detection signal for the wideband feedback circuit 35 and a second envelope detector 33b that generates a second detection signal for the supply modulator 34.

(79) In certain implementations, the first envelope detector 33a provides different conditioning relative to the second envelope detector 33b. Implementing the detectors in this manner aids in providing detection signals suitable for handling by the wideband feedback circuit 35 and the supply modulator 34. In one embodiment, the first envelope detector 33a and the second envelope detector 33b provide detection at different points along an RF output signal path. For example, the first envelope detector 33a can provide detection before an output matching network while the second envelope detector 33b can provide detection after the output matching network, or vice versa.

(80) FIG. 4A is a schematic diagram of a power amplifier system 110 with positive envelope feedback according to another embodiment. The power amplifier system 110 includes an input stage 31, an output stage 92, a current mode detector 93, a supply modulator 34, a wideband resistive voltage shifter 95, and a bias choke inductor 96.

(81) The power amplifier system 110 of FIG. 4A is similar to the power amplifier system 40 of FIG. 3A, except that the power amplifier system 110 illustrates specific implementations of the output stage, the envelope detector, the wideband feedback circuit, and the signal combiner of FIG. 3A.

(82) The output stage 92 includes a field-effect transistor 101 and a supply choke inductor 102. The field-effect transistor 101 includes a gate that receives the amplified RF signal from the input stage 31 and that is biased by the wideband resistive voltage shifter 95. The field-effect transistor 101 further includes a source electrically connected to ground, and a drain that generates the RF output signal RF.sub.OUT and that receives the supply voltage V.sub.SUP via the supply choke inductor 102. The supply choke inductor 102 aids in powering the output stage 92 with the supply voltage V.sub.SUP, while providing impedance sufficient to block the RF output signal RF.sub.OUT. In one embodiment, the field-effect transistor 101 is fabricated by a silicon on insulator (SOI) processing technology.

(83) Although the illustrated power amplifier system 110 includes two stages, other configurations are possible, including, for example, power amplifiers including one stage or three or more stages. Although the illustrated output stage 92 is implemented using a field-effect transistor, the teachings herein are also applicable to configurations using bipolar transistor configurations or a combination of field-effect and bipolar transistors. Furthermore, other amplifier topologies can be used, including, but not limited to, cascode topologies. For example, a cascode power amplifier stage can include a common source transistor or common emitter transistor in series with one or more cascode transistors.

(84) The current mode detector 93 generates a detection signal based on providing RF to DC conversion gain. For example, the current mode detector 93 can be used to extract the output signal envelope of the output stage 92 based on the amount of drain current of the field-effect transistor 101. Additionally, the current mode detector 93 generates an output voltage that changes in relation to the output signal envelope.

(85) The wideband resistive voltage shifter 95 includes a first resistor 97, a second resistor 98, and a voltage source 99. The voltage source 99 controls a quiescent bias voltage of the gate of the field-effect transistor 101 when the output of the current mode detector 93 is low.

(86) Additionally, the first and second resistors 97, 98 operate as a voltage divider that provides positive envelope feedback to the gate of the field-effect transistor 101 based on the output signal envelope detected by the current mode detector 93. For example, an intermediate node between the first and second resistors 97, 98 is used to generate a positive envelope feedback signal that is provided to an input of output stage 92 via the bias choke inductor 96.

(87) In certain implementations, a resistance of at least one of the first resistor 97 or the second resistor 98 is controllable (for instance, variable or programmable) based on a control signal. For instance, the resistance ratio of the first resistor 97 and the second resistor 98 can be controlled to achieve a desired amount of voltage shifting from the output of the current mode detector 93 to the input of the output stage 92. Although one implementation of a wideband feedback circuit has been shown in FIG. 4A, a wideband feedback circuit can be implemented in other ways.

(88) FIG. 4B is a schematic diagram of a power amplifier system 120 with positive envelope feedback according to another embodiment. The power amplifier system 120 of FIG. 4B is similar to the power amplifier system 110 of FIG. 4A, except that the power amplifier system 120 includes an output matching network 104. In the illustrated embodiment, the current mode detector 93 provides detection before the output matching network 104. An envelope detector can provide detection at a wide variety of positions along an output signal path of a power amplifier.

(89) FIG. 4C is a schematic diagram of a power amplifier system 130 with positive envelope feedback according to another embodiment. The power amplifier system 130 of FIG. 4C is similar to the power amplifier system 110 of FIG. 4A, except that the power amplifier system 130 includes an output matching network 104. In the illustrated embodiment, the current mode detector 93 provides detection after the output matching network 104.

(90) FIG. 5 is a schematic diagram of a power amplifier system 150 with positive envelope feedback according to another embodiment. The power amplifier system 150 of FIG. 5 is similar to the power amplifier system 40 of FIG. 3A, except that the power amplifier system 150 further includes an input stage envelope detector 113, an input stage supply modulator 114, an input stage wideband feedback circuit 115, and an input stage signal combiner 116.

(91) The power amplifier system 150 illustrates one example of a power amplifier system in which positive envelope feedback is used for multiple stages. For example, by providing multiple positive envelope feedback loops, further enhancements in power amplifier linearity and/or efficiency can be achieved.

(92) FIG. 6A is a graph 217 showing a first example of power amplifier supply voltage versus time. The graph 217 illustrates the voltage of an RF output signal 211 from a power amplifier, the RF output signal's envelope 212, and a power amplifier supply voltage 213 versus time. The graph 217 corresponds to one example of waveforms for an implementation in which the power amplifier supply voltage 213 is substantially fixed.

(93) FIG. 6B is a graph 218 showing a second example of power amplifier supply voltage versus time. The graph 218 illustrates the voltage of an RF output signal 211, the RF output signal's envelope 212, and a power amplifier supply voltage 214 versus time. The graph 218 corresponds to one example of waveforms for an implementation in which positive envelope feedback is used to modulate the power amplifier supply voltage 214.

(94) In contrast to the power amplifier supply voltage 213 of FIG. 6A, the power amplifier supply voltage 214 of FIG. 6B changes in relation to the envelope 212 of the RF output signal 211. The power amplifier supply voltage 214 of FIG. 6B illustrates one example of a power amplifier supply voltage modulated by an output envelope 212 of a power amplifier.

(95) FIG. 7A is a schematic diagram of one embodiment of a packaged module 300. FIG. 7B is a schematic diagram of a cross-section of the packaged module 300 of FIG. 7A taken along the lines 7B-7B.

(96) The packaged module 300 includes a power amplifier die 301, a modulator die 302, surface mount components 303, wirebonds 308, a package substrate 320, and encapsulation structure 340.

(97) The packaging substrate 320 is configured to receive a plurality of components, such as the dies 301, 302 and the surface mount components 303. Additionally, the package substrate 320 includes pads 306 formed from conductors disposed therein. As shown in FIGS. 7A and 7B, the dies 301, 302 include pads 304, and the wirebonds 308 have been used to connect the pads 304 of the dies 301, 302 to the pads 306 of the package substrate 301.

(98) The packaged module 300 is implemented in accordance with one or more features of the present disclosure.

(99) For example, in one embodiment, the power amplifier die 301 includes an envelope detector (for instance, the envelope detector 33), a wideband feedback circuit (for instance, the wideband feedback circuit 35), and a power amplification stage (for instance, the output stage 32), and the modulator die 302 includes a supply modulator (for instance, the supply modulator 34). In certain implementations, one or more choke inductors (for instance, the bias choke inductor 96 and/or the supply choke inductor 102) are implemented as surface mount components 303 on the package substrate 320.

(100) In certain implementations, the dies 301, 302 are manufactured using different processing technologies.

(101) The packaged module 300 implements a power amplifier system with positive envelope feedback in a single multi-chip module (MCM), thereby providing a relatively compact solution. In contrast, certain power amplifier systems that operate with envelope tracking are implemented using a power amplifier module and a separate envelope tracker module that provides a power amplifier supply voltage to a pin of the power amplifier module.

(102) As shown in FIG. 7B, the packaged module 300 includes a plurality of contact pads disposed on the side of the packaged module 300 opposite the side used to mount the dies 301, 302. Configuring the packaged module 300 in this manner can aid in connecting the packaged module 300 to a circuit board such as a phone board of a wireless device. The example contact pads 332 can be configured to provide RF signals, bias signals, power low voltage(s) and/or power high voltage(s) to the dies 301, 302 and/or the surface mount components 303. As shown in FIG. 7B, the electrical connections between the contact pads 332 and the dies 301, 302 can be facilitated by connections 333 through the package substrate 320. The connections 333 can represent electrical paths formed through the package substrate 320, such as connections associated with vias and conductors of a multilayer laminated package substrate.

(103) In some embodiments, the packaged module 300 can also include one or more packaging structures to, for example, provide protection and/or facilitate handling of the packaged module 300. Such a packaging structure can include overmold or encapsulation structure 340 formed over the packaging substrate 320 and the components and die(s) disposed thereon.

(104) It will be understood that although the packaged module 300 is described in the context of electrical connections based on wirebonds, one or more features of the present disclosure can also be implemented in other packaging configurations, including, for example, flip-chip configurations.

(105) Applications

(106) Some of the embodiments described above have provided examples in connection with wireless devices or mobile phones. However, the principles and advantages of the embodiments can be used for any other systems or apparatus that have needs for power amplifier systems.

(107) Such power amplifier systems can be implemented in various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, etc. Examples of the electronic devices can also include, but are not limited to, memory chips, memory modules, circuits of optical networks or other communication networks, and disk driver circuits. The consumer electronic products can include, but are not limited to, a mobile phone, a telephone, a television, a computer monitor, a computer, a hand-held computer, a personal digital assistant (PDA), a microwave, a refrigerator, an automobile, a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi-functional peripheral device, a wrist watch, a clock, etc. Further, the electronic devices can include unfinished products.

(108) Conclusion

(109) Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

(110) Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “can,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding, with or without author input or prompting, whether these features, elements and/or states are included or are to be performed in any particular embodiment.

(111) The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times.

(112) The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

(113) While certain embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.