Abstract
An improved switchable capacitor array comprises a plurality of n2 capacitor units, each comprising a capacitor with a capacitance and a switch unit. The capacitor units are electrically connected in series. Equidistantly spaced impedance values can be obtained if the values of the capacitances are chosen properly.
Claims
1. A switchable capacitor array comprising: a plurality of n >=2 capacitors units, each comprising a capacitor with a capacitance c.sub.i and a switch unit, wherein the capacitances c.sub.i have a binary weighting with an offset; the capacitor units are electrically connected in series; and the switch unit of each capacitor unit is electrically connected in parallel to the respective capacitor.
2. The array of claim 1, wherein the plurality of capacitor units providing 2.sup.n switchable capacitance values, and at least one subset of the 2.sup.n switchable capacitance values corresponding to equidistantly spaced reactance values.
3. The array of claim 1, wherein the switch units comprise stacks of switches.
4. The array of claim 1, wherein the switch units comprise switches selected from: FET-switches, CMOS switches, GaAs switches, pHEMT switches, SOI switches, SOS switches and MEMS switches.
5. The array of claim 1, wherein capacitors are MIM capacitors.
6. The array of claim 1, wherein at least two of the capacitor units having substantially similar structure.
7. The array of claim 1, further comprising an additional capacitor with a capacitance c.sub.add electrically connected in parallel to the series connection of capacitor units.
8. The array of claim 1, wherein a capacitor unit has a parallel connection of capacitors.
9. The array of claim 1, wherein the switch units comprise parallel or serial connected uniform unit cells.
10. The array of claim 1, wherein the switch units are arranged in a first layer system and the capacitors are arranged in a second layer system located above or below the first layer system.
11. The array of claim 1, being a tunable capacitor in an RF-Filter circuit.
12. The array of claim 11, wherein the tunable capacitor is connected in series in a signal path of the RF-filter.
13. The array of claim 1, wherein one or all switch units have a bias configuration comprising serial and/or parallel biasing paths with resistive elements adapted to provide a high switch time, a high Q-factor or a preferred trade-off between switch time and Q-factor.
14. The array of claim 13, wherein the array is connected in a front end circuit of a mobile communication device.
15. A mobile communication device, comprising: an impedance matching circuit with a signal path; a plurality of n >=2 capacitors units, each comprising a capacitor with a capacitance c.sub.i and a switch unit, wherein the capacitor units are electrically connected in series, and the capacitances c.sub.i have a binary weighting with an offset; and the switch unit of each capacitor unit is electrically connected in parallel to the respective capacitor.
16. A method for driving a switchable capacitor array, the switchable capacitor array comprising: a plurality of n >=2 capacitors units, each comprising a capacitor with a capacitance c.sub.i and a switch unit, wherein the capacitor units are electrically connected in series, and the capacitances c.sub.i have a binary weighting with an offset; and the switch unit of each capacitor unit is electrically connected in parallel to the respective capacitor, wherein the bits of a n bit word created with a logic circuit determines the switching state of the n capacitor units.
17. The method of claim 16, wherein the most significant bit corresponds to the largest capacitance value or to the smallest capacitance value.
18. The method of claim 16, wherein inverted bits are used to control the switching state of the capacitor units.
Description
(1) The concepts and embodiments of the invention are described in the following schematic figures in which
(2) FIG. 1 shows a series connection of capacitor units,
(3) FIG. 2 shows a series connection of capacitor units connected in parallel to an additional capacitor,
(4) FIG. 3A shows a series connection of at least three capacitor units with one capacitor unit comprising two parallel connected capacitors,
(5) FIG. 3B shows a series connection of capacitor units with two individually switchable capacitors in one unit,
(6) FIG. 3C shows a possible arrangement of switches relative to the capacitors in a capacitor unit,
(7) FIG. 3D shows a possible arrangement with one capacitor unit comprising no switch unit,
(8) FIG. 4 shows a capacitor unit with an embodiment of a switch unit,
(9) FIG. 5 shows a capacitor unit with a plurality of FET elements in the switch unit,
(10) FIG. 6 shows a capacitor unit with stacked switches in the switch unit,
(11) FIG. 7A shows an arrangement of switches and a biasing possibility in a switch unit,
(12) FIG. 7B shows another arrangement of switches and biasing possibility in a switch unit,
(13) FIG. 7C shows another arrangement of switches and biasing possibility in a switch unit,
(14) FIG. 7D shows another arrangement of switches and biasing possibility in a switch unit,
(15) FIG. 7E shows another arrangement of switches and biasing possibility in a switch unit,
(16) FIG. 7F shows another arrangement of switches and biasing possibility in a switch unit,
(17) FIG. 7G shows a general principle of biasing a switch unit,
(18) FIG. 7H shows another general principle of biasing a switch unit,
(19) FIG. 7I shows another general principle of biasing a switch unit,
(20) FIG. 7J shows another general principle of biasing a switch unit,
(21) FIG. 8 shows the possible total capacitances of an n=5 capacitor array,
(22) FIG. 9 shows the possible total capacitances of an n=4 capacitor array with inverted bit control,
(23) FIG. 10 shows the possible total capacitances of an n=5 capacitor array with inverted bit control,
(24) FIG. 11 shows the normalized imaginary part of the impedance values corresponding to the capacitance values shown in FIG. 10,
(25) FIG. 12 shows the equal step size in the impedance domain of the capacitor array corresponding to FIGS. 10 and 11,
(26) FIG. 13 shows the possible total capacitances of an n=5 capacitor array with binary weighting with an offset,
(27) FIG. 14 shows the normalized imaginary part of the impedance values corresponding to the capacitance values shown in FIG. 13,
(28) FIG. 15 shows the corresponding impedance step size of the capacitor array corresponding to FIGS. 13 and 14,
(29) FIG. 16 shows the possible total capacitances of another n=5 capacitor array with another scaling factor F,
(30) FIG. 17 shows the normalized imaginary part of the impedance values corresponding to the capacitance values shown in FIG. 16,
(31) FIG. 18 shows the corresponding steps in impedance value corresponding to the capacitor array of FIGS. 16 and 17,
(32) FIG. 19 shows the possible total capacitance values of an n=5 capacitor array when a thermometer code is used to control capacitors having the same capacitance values,
(33) FIG. 20 shows the normalized imaginary part of the impedance values corresponding to the capacitance values shown in FIG. 19,
(34) FIG. 21 shows the corresponding impedance step size of the capacitor array of FIGS. 19 and 20,
(35) FIG. 22 shows the possible total capacitances of a capacitor array with thermometer coding for the two most significant bits and a binary weighting with an offset with a factor of 2 for the respective other capacitors,
(36) FIG. 23 shows the normalized imaginary part of the impedance values corresponding to the capacitance values shown in FIG. 22,
(37) FIG. 24 shows the corresponding impedance steps of an array of FIGS. 22 and 23,
(38) FIG. 25 shows the possible total capacitance values for an n=5 capacitor array using thermometer coding and scaling factor,
(39) FIG. 26 shows the normalized imaginary part of the impedance values corresponding to the capacitance values shown in FIG. 25,
(40) FIG. 27 shows the corresponding values of the impedance steps of the array of FIGS. 25 and 26,
(41) FIG. 28 shows the results of a simulation calculating the possible capacitance value of an n=3 switchable capacitor array,
(42) FIG. 29 shows the results of the simulation with respect to the corresponding impedance values of the array of FIG. 28,
(43) FIG. 30 shows the results of the simulation with respect to the impedance step size of the array of FIGS. 28 and 29,
(44) FIG. 31 shows the possible capacitance values of an n=3 capacitor array with binary weighting with offset,
(45) FIG. 32 shows the corresponding impedance values of the capacitor array of FIG. 31,
(46) FIG. 33 shows the corresponding impedance step size of the array of FIGS. 31 and 32.
(47) FIG. 1 shows a switchable capacitor array SCA comprising a plurality of n capacitor units CU each comprising a capacitor CAP and a switch unit SU. The order of indices do not alter the switching topology or the concepts of the invention. Without loss of generality, indices start as i=0 and end at i=n1 with a total sum of n capacitor units CU. Especially if only the capacitor having the largest capacitance is activated, the maximum total capacity which may be denoted as C.sub.0 is obtained.
(48) The series connection of capacitor units allows to obtain equidistantly spaced impedance values due to the inverse impedance-capacitance relationship and the inventor's finding that serially connected capacitors can provide 1/m capacitance distribution where 0m2.sup.n1 is the number counting the different switching states.
(49) FIG. 2 shows an embodiment where an additional capacitor with an additional capacity CAP.sub.add is electrically connected in parallel to the cascade of serially connected capacitor units CU. The additional capacitor CAP.sub.add allows to have an offset of the respective capacitance values and of the respective impedance values.
(50) FIG. 3A shows a series connection of capacitor units CU wherein at least one capacitor unit and two capacitors CAP1, CAP2 are connected in parallel. The capacitor unit CU comprises two parallel connected switches to shunt the capacitors. It is further possible that a capacitor unit CU comprises a series connection of two individual capacitors as the capacitor unit's capacitor. Such a series connection within a capacitor unit allows to obtain lower voltages applied to the capacitor unit's capacitor and to obtain smaller but precisely defined capacitance values.
(51) FIG. 3B shows a series connection of capacitor units CU with two individually switchable capacitors connected in series in one unit.
(52) FIG. 3C shows an embodiment of a capacitor unit CU with a first capacitor CAP1 connected in parallel to a first switch unit SU1. The capacitor unit CU further comprises a second capacitor CAP2 connected in parallel to the first capacitor CAP1. A second switch unit SU2 is connected in series to the second capacitor CAP2.
(53) FIG. 3D shows a capacitor unit in which the capacitor, e.g. having a capacitance C.sub.0, has no switch unit. A switchable capacitor array connected in a shunt branch, i.e. connected to a ground potential, could establish a short circuit if all capacitor units have a switch unit and if all switch units are in a closed state. To prevent the possibility of such a short circuit a capacitor unit without a switch unit can be provided.
(54) FIG. 4 shows an embodiment of a capacitor unit where the switch unit comprises two FET switches. The source of one FET is connected to the drain of the other FET. The source and the drain of each FET is connected via a resistive element R.
(55) The gates of the FET are connected to a control line via a resistive element per gate.
(56) FIG. 5 shows an embodiment where a plurality of FETs is connected in series. Especially the bodies of the FETs are connected to each other via a resistive element R.sub.B per FET. Connecting the bodies of the FETs to each other allows to obtain a improved linearity as different voltages compared to the gate voltage are applied to the FET's body.
(57) FIG. 6 shows an embodiment of a capacitor unit CU where the switch unit comprises stacked switches having two FETs each.
(58) FIG. 7A shows a possible arrangement of cascaded switches in a switch unit where the gate and body connections of the individual switches are biased in a configuration to obtain a high Q-factor of the capacitor unit but also a high switch time. The nodes RF1 and RF2 are connected to the respective electrodes of the capacitance element of the capacitor unit. Thus, via nodes RF1 and RF2 an RF signal can be conducted through the switch unit. In the arrangement of FIG. 7A it is preferred that the orientation is chosen such that the impedance to ground at node RF1 lower then the impedance to ground at node RF2.
(59) E.g. in a shunt switch the RF1 side is grounded (very low impedance to GND), and RF2 is used in the electronic circuit (which has a high impedance to GND, once the switch is off).
(60) It is possible, too, that in the case of a series element an antenna can have any impedance (also very high ohmic compared to 50 Ohm) while the antenna side is then called the high-impedance point and the input side of the circuit (preferably matched to 50 Ohm) is called the lowest impedance point where, in that case, RF2 is connected to.
(61) A control signal to control the individual switches can be applied to the gate connection of the switches via a feeding point FP.sub.g. The feeding FP.sub.g is connected via a series connection of resistive elements R.sub.g to the gate connections.
(62) The switches' body can be biased via a further feeding point FP.sub.b. The further feeding point FP.sub.b is connected to the bodies of the switches via a series connection of resistive elements R.sub.b. After each resistive element R.sub.b, the series connection provides a direct connection to the respective body of the respective switch SW.
(63) The drain and the source connections of each individual switch SW are connected via a respective further resistive element R.sub.d.
(64) It is possible that the switch unit is in a shunt arrangement. Then, node RF1 is connected to a ground potential. If the switchable capacitor array is connected in an antenna tuner between points a and b, the lowest loss circuit is obtained once RF1 is connected to the node (a or b) with the lowest impedance to ground. This, in the tuner, is at the input side when a tuned state is obtained.
(65) In the off-state of the switch unit, the off capacictance has the highest Q-factor at node RF2.
(66) FIG. 7B shows another possible arrangement of cascaded switches in a switch unit. The switches' body can be biased via a feeding point FP.sub.b that is connected via a series connection of resistive elements to the respective switches' body. However, in contrast to the arrangement of FIG. 7A, the first resistive element of the series connection of resistive elements has a resistance value R.sub.bc (R.sub.bc and R.sub.gc are called R-body-common and R-gate-common) being different from the resistance values R.sub.b of the series connection.
(67) A control voltage to the gate connections of the switches SW can be applied via a feeding point FP.sub.g. However, in contrast to the arrangement shown in FIG. 7A, the control signal is not applied at the beginning of the series connection of resistive elements R.sub.g but it is applied via a resistive element R.sub.gc directly to a switch not being the first switch of the cascaded switches. Neighboring gate connections of neighboring switches SW are connected via a respective resistive element R.sub.g.
(68) Such an arrangement provides a high Q-factor at a medium switch time.
(69) It may be preferred that node RF1 is connected to the lowest impedance point to ground of the respective circuit. It is possible that the lowest amount of electrical charge needs to be applied to the switches' bodies. Then, it is preferred that the switches' bodies are connected to a low impedance, too.
(70) A higher amount of electrical charge may be conducted to the gate connections. Therefore, the feeding point FP.sub.g is shifted towards the second node RF2. A tradeoff between switch time and Q-factor is obtained and a trend towards a better switching time or towards a higher Q-factor can be selected depending on the place where the gate control signal is applied to the series connection of resistive elements R.sub.g.
(71) A minimum switching time will be obtained when the control signal via the feeding point FP.sub.g is applied in the middle of the cascade.
(72) FIG. 7C shows another possible arrangement of cascaded switches where a control signal to the gate connections of the switches via a feeding point FP.sub.g and a resistive element R.sub.gc2 can be applied distributed via resistive elements R.sub.gc1 to the series connection of resistive elements comprising resistive elements R.sub.g1 and R.sub.g2 being directly connected to the gate connections of the switches.
(73) In such an arrangement, it is possible that node RF1 is connected to the lowest impedance point of the circuit. The lowest amount of charge that needs to be driven is the charge applied to the body connections.
(74) Thus, a higher amount of charge needs to be driven to the gate connections. By the possibility of applying the gate control signal via distributed (parallel) resistive elements R.sub.gc1, R.sub.gc2, a low switching time can be obtained.
(75) FIG. 7D shows an arrangement of cascaded switches. The drain and source and gate and body connections of the switches have a connection similar to the arrangement shown in FIG. 7C. However, the number of switches arranged in the cascade is not restricted. E.g. the number of switches can be between two and 32. It is especially possible to omit the resistive element denoted as R.sub.g2 in FIG. 7C while the resistive elements R.sub.gc1 and R.sub.gc2 have a value equal to half of the resistance of R.sub.g: R.sub.gc1=R.sub.gc2=0.5 R.sub.g.
(76) FIG. 7E shows a possible arrangement of cascades switches in a switch unit where, in contrast to the arrangement shown in FIG. 7D, the control signal to the gate connections of the switches is applied via a resistive element R.sub.gc3 and a parallel connection comprising the resistive elements R.sub.gc1 and R.sub.gc2 directly to the second and second last switch of the cascade. Of course, the resistive elements R.sub.gc1 and R.sub.gc2 can be connected at an arbitrary point to the respective gate connection of the cascade of switches. Then, a compromise between an off-state Q-factor and switch time can be chosen.
(77) FIG. 7F shows another possible arrangement of cascaded switches in a switch unit where, in order to improve switch time, the control signal to the gate connections of the switches is distributed via three resistive elements R.sub.gc1, R.sub.gc2, R.sub.gc3 and via R.sub.gc4.
(78) FIGS. 7G to 7J show general concepts of distributing a control signal via a feeding point FP to blocks of switches SW of the switch unit. The control signal can be inserted into the switch unit at the beginning of the cascade and conducted internally as shown in FIG. 7G. Each unit drawn in the figures can consist of an arbitrary number n of switches.
(79) In order to decrease switching time, the control signal can be applied at the center of the cascade and distributed towards the outer switches (FIG. 7H) or conducted to the respective outer blocks of switches and internally distributed to the inner switches (FIG. 7I).
(80) However, each block of switches can obtain a direct control signal via a control signal network as shown in FIG. 7J.
(81) FIG. 8 shows the possible total capacities C.sub.tot of an n=5 capacitor array with binary weighting and a largest individual capacitance of 16 pF. The values lie on an y=16/m curve. The fact that the capacitance values show a proportional to 1/m behavior allows to obtain equidistantly spaced impedance values according to equation 2.
(82) The individual total capacitances can be seen in the following table:
(83) TABLE-US-00001 switch state capacitor value (pF) 0/00000 inf 1/00001 16.0 2/00010 8.0 3 5.3333 4/00100 4.0 5 3.2 6 2.6667 7 2.2857 8/01000 2.0 9 1.7778 10 1.6 11 1.4545 12 1.3333 13 1.2308 14 1.1429 15 1.0667 16/10000 1.0 17 0.94118 18 0.88889 19 0.84211 20 0.8 21 0.7619 22 0.72727 23 0.69565 24 0.66667 25 0.64 26 0.61538 27 0.59259 28 0.57143 29 0.55172 30 0.53333 31/11111 0.51613
where the digital numbers in the respective left column represent the switching states m of the switching circuits. If all switches are closed (00000), then no capacitor is connected in the signal path and the total capacitance is infinite resulting in an impedance of 0 when using ideal switches.
(84) FIG. 9 shows the possible total capacitance values of a capacitor circuit with n=4 capacitor units. Compared to the array referred to in FIG. 8, the capacitance value increases with increasing index number m as a result of inverting the switching state, i.e. replacing 0 with 1 and 1 with 0.
(85) The index m, thus, is chosen to obtain an ascending or descending capacitance value.
(86) FIG. 10 shows possible total capacities where the capacitors have the capacitances 1.9375 pF, 3.875 pF, 7.75 pF, 15.5 pF, and 31 pF. Thus, a binary weighting is chosen.
(87) FIG. 11 shows the corresponding impedance values of the array of FIG. 10.
(88) FIG. 12 shows the corresponding step size of the impedance values of the array of FIGS. 10 and 11.
(89) FIG. 13 shows the possible total capacitance values of a binary weighted array with an offset. Values of the capacitances are: 2.25 pF, 3.375 pF, 6.75 pF, 13.5 pF, and 27 pF. Thus, the scaling factor F is 0.75. Here, i=4. The resulting maximum voltages are 1.94:2.25=1.159 (i.e. 16%) lower than the maximum voltages of an array using F=1.
(90) FIG. 14 shows the corresponding impedance values of the array of FIG. 13.
(91) FIG. 15 shows the corresponding step size of the impedance values of the array of FIGS. 13 and 14.
(92) FIG. 16 shows the possible total capacitance values of an n=5 capacitor array with capacitance values: 3.641 pF, 7.585 pF, 5.17 pF, 10.34 pF, and 20.68 pF. Two sets of capacitance values corresponding to equally spaced impedance values are obtained which can be used for low power applications and high power applications or low band applications and high band applications. Especially the most significant bit or the smallest capacitor, respectively, can be used as a selection means for high power or low power operation, e.g. in the GSM (GSM=Global System for Mobile communication) system.
(93) The scaling factor F equals 0.35.
(94) FIG. 17 shows the corresponding impedance values of the array of FIG. 16.
(95) FIG. 18 shows the corresponding step size of the impedance values of the array of FIGS. 16 and 17.
(96) FIG. 19 shows possible total capacitances of a capacitor array in which the individual capacitances of the capacitor units are equal, i.e. 5 pF. With such a capacitor array, thermometer coding can be used and obtained redundancy in the array capacitance values can be counteracted by skipping redundant states implemented in an algorithm in a logic circuit. Then, redundant states utilizing redundant capacitors can be reactivated if the failure of one or several capacitors is detected.
(97) However, redundant capacitors can be utilized in high-power applications, too.
(98) FIG. 20 shows the corresponding impedance values of the array of FIG. 19.
(99) FIG. 21 shows the corresponding step size of the impedance values of the array of FIGS. 19 and 20.
(100) FIG. 22 shows the possible total capacitance values of an n=5 capacitor array with the capacitances: 2.875 pF, 2.875 pF, 5.75 pF, 11.5 pF, and 23 pF.
(101) FIG. 23 shows the corresponding impedance values of the array of FIG. 22.
(102) FIG. 24 shows the corresponding step size of the impedance values of the array of FIGS. 22 and 23.
(103) FIG. 25 shows total capacitance values of an n=5 capacitor array with the capacitances: 3.167 pF, 3.167 pF, 4.75 pF, 9.5 pF, and 19 pF.
(104) FIG. 26 shows the corresponding impedance values of the array of FIG. 25.
(105) FIG. 27 shows the corresponding step size of the impedance values of the array of FIGS. 25 and 26.
(106) FIG. 28 shows total capacitance values of an n=3 (the lowest 7) capacitor array with binary weighting.
(107) FIG. 29 shows the corresponding impedance values of the array of FIG. 28.
(108) FIG. 30 shows the corresponding step size of the impedance values of the array of FIGS. 28 and 29.
(109) FIG. 31 shows possible total capacitance values. The fourth and the fifth capacitance values are equal, being the result from the fact that two capacitor units have the same capacitance.
(110) FIG. 32 shows the corresponding impedance values of the array of FIG. 31.
(111) FIG. 33 shows the corresponding step size of the impedance values of the array of FIGS. 31 and 32.
LIST OF REFERENCE SIGNS
(112) CAP: capacitor CAP1, CAP2: first, second capacitor of a capacitor unit CAP.sub.add: additional capacitor C.sub.tot: total capacitance of the switchable capacitor array CU: capacitor unit FET: field-effect transistor FP: feeding point FPb: feeding point for a body bias voltage FPg: feeding point for a gate control signal i: index number of capacitor unit (0in1) m: index number of switching state (0m2.sup.n1) n: number of capacitor units in the switchable capacitor array R: resistive element RB: resistive element connected with the body of a FET RF1: node connecting the switch unit to an RF signal path RF2: node to connect the switch unit to an RF signal path SCA: switchable capacitor array SU: switch unit SU1, SU2: first, second switch unit SW: switch
