SYSTEM AND SIMULATOR FOR THE DISENGAGEABLE SIMULATION OF INSTALLATIONS OR MACHINES WITHIN PROGRAMMABLE LOGIC CONTROLLERS

Abstract

Provided is a system and a simulator for the disengageable simulation of installations or machines within programmable logic controllers, in which control program and simulation program are strictly separate within the same processing environment, wherein the direction of access for the input/output memory area during normal operation and the consistent reversal thereof in the simulation part are ensured, and which involves the simulation program being executed between the program cycles, with a virtual clock being stopped during the simulation. As a result, the test on an unaltered user program in the PLC avoids errors in the startup or test phase through code changes, and a timing response as in the genuine installation, particularly in the event of tests on timers and under race conditions, achieves a higher level of program quality through better test results.

Claims

1. A system for disengageable simulation of installations or machines within a programmable logic controller, comprising: a simulation part and a productive part, wherein a respective simulation sequence in the simulation part is provided between two respective program sequences in the productive part, wherein the programmable logic controller includes a memory for a separate storage of a productive code of a user program and of a simulation code produced by a simulation program, and a virtual clock that is configured for normal operation in the productive part and for stoppage in the simulation part.

2. The system as claimed in claim 1, wherein: the productive part has input information that is readable from the memory and at least one portion of which is processable during a respective program sequence and then writable to the memory as output information, and the simulation part has output information that is readable from the memory and at least one portion of which is processable during a simulation sequence and then writable to the memory as input information.

3. The system as claimed in claim 1, wherein the installation is divided into subregions and appropriate simulation/startup modules are present for the subregions, and in which as yet unfinished subregions of the installation are simulatable by virtue of the applicable simulation/startup modules being provided for individual activation and other, already finished, subregions being provided for direct use.

4. The system as claimed in claim 1, wherein the programmable logic controller has processor cores on which the user program and the simulator are each separately executable.

5. A simulator for a system for disengageable simulation of installations or machines within the programmable logic controller as claimed in claim 1, the simulator integrated in the programmable logic controller such that the simulator is provided for programming in a PLC language of the programmable logic controller and for generation of a control code that is loadable into the programmable logic controller and executable therein.

6. The simulator as claimed in claim 5, comprising a mechanism for preventing execution of the whole simulation code by means of deactivation that needs to be performed only at one point.

Description

BRIEF DESCRIPTION

[0013] Some of the embodiments will be described in detail, with reference to the following Figures, wherein like designations denote like members, wherein:

[0014] FIG. 1 shows an overview depiction to explain embodiments of the invention in terms of engineering system and programmable logic controller,

[0015] FIG. 2 shows a basic depiction to explain embodiments of the invention in terms of separation of productive code and simulation code and also the interchange of information with the data memory, and

[0016] FIG. 3 shows a flowchart to explain embodiments of the invention in terms of the timings in the productive part, in the simulation part and in the virtual clock.

DETAILED DESCRIPTION

[0017] FIG. 1 shows an overview depiction to explain embodiments of the invention in terms of an engineering system ES and programmable logic controller PLC, wherein an application program AP that is present in the engineering system leads to a productive code PC in the programmable logic controller PLC and, separately therefrom, generates a code from a simulation program S in the engineering system ES and, as simulation code SC, is separately likewise loaded into the programmable logic controller PLC.

[0018] The simulation code SC is programmed using a PLC language and is executed by an IO simulator that is advantageously integrated in a programmable logic controller PLC.

[0019] The IO simulator is part of the controller, runs within the same context and can access the internal data memories within the control system.

[0020] To separate the responsibilities, the two parts productive code and simulation code are distinguished from one another. The PLC manages a simulation code exclusively through the IO simulator. The direct or inadvertent execution of simulation code by the PLC is technically prevented. Only the IO simulator is still provided with the special rights cited below such as e.g. modifying input signals.

[0021] FIG. 2 shows a basic depiction to explain embodiments of the invention. To better clarify the differences, the top part of FIG. 2 depicts a programmable logic controller PLC.sub.old with a previous productive code PCold that also includes the previous simulation code SCold.

[0022] By contrast, the bottom part of FIG. 2 depicts a programmable logic controller PLC according to embodiments of the invention with a productive code PC and the separate simulation code SC, wherein the productive code PC reads PL input information from a memory SP and writes PS output information to the memory SP and wherein simulation code SC conversely reads SL at least one portion of the output information from the memory SP and writes SS new input information to the memory SP.

[0023] FIG. 3 shows a flowchart to explain the timings in the productive part PT, in the simulation part ST and in the virtual clock VC in an inventive system.

[0024] In the productive mode, or in the productive part PT, input information is read PL from the memory SP, at least one portion of this input information is processed PV during a respective program sequence and is then written PS to the memory SP as output information.

[0025] The unchanged user program computes the new outputs on the basis of the inputs. During the computation, the virtual clock VC continues to run normally TON, i.e. the timing of the program sequence is unchanged. In a productive mode, no simulation is computed. The control code is executed in real time.

[0026] In the simulation/startup mode, or in the simulation part ST, output information is read SL from the memory SP, at least one portion of this output information is processed SV and is then written SS to the memory SP as input information.

[0027] In the simulation part ST, the simulation modules of the IO simulator, in contrast to the productive part PT, access the IO memory areas. The simulation is computed between the program cycles and therefore does not corrupt the normal operating response. The PLC code is executed on the basis of the virtual clock VC, which functions as a stopwatch and does not progress during the simulation TOFF. Therefore, the timing of the actual program does not change either as a result of the execution of the simulation code. The execution of the simulation modules is deactivatable depending on the scenario (developments/test/production).

[0028] After a sequence of the user program, the virtual clock VC stops and the simulation procedure begins. The simulation computes the new inputs on the basis of the outputs. Thereafter, the cycle begins again with the sequence of the user program and continuation of the normal timing. As a result of the virtual clock, the simulation is computed practically between the cycles, which means that the simulation accuracy is improved, since the timing (cycle times, jitter, etc.) is therefore not corrupted.

[0029] The execution times of the simulation are not relevant to the consideration of program execution time.

[0030] As a result of embodiments of the invention, it is not necessary to remove program parts, since the IO simulator is simply disengaged by the change of mode of operation, removing the lack of clarity in the otherwise required program additions, for example. The disengaging of the IO simulator deactivates all components of the simulation code and hence any unintentional manipulation of the process data. The clock runs constantly.

[0031] Additionally, it is possible to individually activate the use of the simulation and startup modules, so that subregions of the installation can be simulated, while other parts are already complete and are used directly. The simulation modules are also available after startup of the installation for later operation. In this case, the timing response changes as a result of the additional complexity of the simulation of subregions. Stopping the clock is no longer possible in this case, since the time bases of the simulation and of the real installation parts are then different than one another.

[0032] Optionally, user program and simulator can also be executed on separate processor cores of the PLC.

[0033] A corresponding simulator can be sold as a separate product, e.g. with separate licenses for engineering and execution time.

[0034] The IO simulator can be deactivated by a simple mechanism at one point. The system is designed so that when the IO simulator is deactivated, there is the certainty that no further simulation code is executed.

[0035] The execution of the simulation code is separate from the execution of the productive code, which means that there is no possibility of confusion.

[0036] Although the present invention has been disclosed in the form of preferred embodiments and variations thereon, it will be understood that numerous additional modifications and variations could be made thereto without departing from the scope of the invention.

[0037] For the sake of clarity, it is to be understood that the use of a or an throughout this application does not exclude a plurality, and comprising does not exclude other steps or elements.