SIGNAL DETECTOR

Abstract

A signal, in particular radio-frequency signal, detector (10), such as a detector of wake-up radio type has a first circuit (20) receiving at its input the signal, configured to set the operating point (M) at the output to a predefined DC voltage (Vm_DC) to which a variable part (Vm) which is dependent on the signal from the input is added. A second circuit (30) is connected at its input to the output of the first circuit (20) and configured to amplify the variable part (Vm) of the signal, this second circuit has a chain of at least two logic inverters (32) in a cascade and operating below the threshold.

Claims

1. A signal detector comprising: a first circuit receiving at its input the signal, configured to set the operating point at the output to a predefined DC voltage to which a variable part which is dependent on the signal from the input is added, and a second circuit connected at its input to the output of the first circuit (20) and configured to amplify the variable part of the signal, this second circuit comprising a chain of at least two logic inverters are positioned in a cascade and operate below the threshold.

2. The signal detector according to claim 1, the first circuit comprising a bridge of MOS transistors in series which are connected by a midpoint forming the output of the first circuit, the input of the first circuit corresponding to the gate of one of the transistors.

3. The signal detector according to claim 2, the MOS transistors of the bridge operating below the threshold.

4. The signal detector according to claim 2, the bridge of MOS transistors comprising a pull-up transistor and a pull-down transistor, the signal being applied to the gate of the pull-up transistor and a control voltage being applied to the gate of the pull-down transistor.

5. The signal detector according to claim 2, the MOS transistors of the bridge being of NMOS type.

6. The signal detector according to claim 1, the first and/or second circuit being supplied with voltages Vdd and Vss such that |VddVss| is between 0 V and 0.6 V.

7. The signal detector according to claim 6, the voltage Vdd being between 0 V and 300 mV and/or the voltage Vss being between 300 mV and 0 V.

8. The signal detector according to claim 1, a first part of the chain of inverters being configured to work without saturation, and a second part of the chain of inverters following the first being configured to work in saturation mode so that the signal at the output of each inverter of the second substantially reaches the values Vdd and Vss.

9. The signal detector according to claim 1, the second circuit being connected at the output of one inverter of the chain to an artificial neuron.

10. The signal detector according to claim 9, the artificial neuron being of leaky integrate-and-fire type.

11. A method for generating electrical pulses in order to supply a spiking neural network (SNN) with the signal detector of claim 8, wherein the signal being modulated.

12. The signal detector according to claim 1, which is a radiocommunication receiver.

13. The signal detector according to claim 1, the second circuit being an artificial neuron of axon hillock type and comprising: a feedback capacitor connected between the input and the output of the second circuit, and a feedback transistor controlled by the output voltage of the second circuit at the gate, and one terminal of which is connected to the input of the second circuit.

14. The signal detector according to claim 13, comprising a membrane capacitor being the input capacitor of the first inverter of said chain.

15. A method for generating electrical pulses in order to provide a received signal strength indicator RSSI with the signal detector of claim 12, wherein the signal being a continuous wave CW.

16. The method as claimed in claim 15 further comprising estimating the distance at which the transmission source is located in networks of communicating objects with the signal detector.

17. A telecommunications node comprising the detector according to claim 1, a main transceiver and a control unit, the detector being configured to send, upon detecting the signal, a switching signal to the control unit, the latter being configured to activate, upon receiving the switching signal, the main transceiver.

18. A method for detecting a signal having a frequency between 1 Hz and 1 THz using the detector according to claim 1, comprising detecting the signal by means of the detector and generating a digital signal at the output of the detector.

19. The method according to claim 18, the radio-frequency signal being modulated according to one of the following modulation schemes: amplitude-shift keying, on-off keying, pulse-position modulation and pulse-width modulation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The invention may be better understood upon reading the following description of non-limiting exemplary implementations thereof, and upon examining the appended drawing, in which:

[0040] FIG. 1 is a diagram illustrating the detector according to the invention, used as a wake-up radio receiver in a telecommunications system;

[0041] FIG. 2 is a block diagram of the detector according to the invention;

[0042] FIG. 3 schematically shows an exemplary first detector circuit according to the invention, in the steady state;

[0043] FIG. 4 schematically shows an exemplary first detector circuit according to the invention, in the small-signal state;

[0044] FIG. 5 schematically shows an exemplary first detector circuit according to the invention, in the large-signal state;

[0045] FIG. 6 schematically shows an equivalent circuit of the circuit of the example of FIG. 5;

[0046] FIG. 7 schematically shows a transfer characteristic of a CMOS inverter below the threshold;

[0047] FIG. 8 schematically shows a circuit of a CMOS inverter;

[0048] FIG. 9 schematically shows an exemplary detector circuit according to the invention;

[0049] FIG. 10 illustrates the curve of the signal at the input of the cascade of inverters which is shown in FIG. 9 as well as the curve of the signal obtained at the output of each inverter;

[0050] FIG. 11 illustrates the waveform of the signal at the output of the detector of FIG. 9 for various amplitudes of the signal at the input of the detector;

[0051] FIG. 12 is similar to FIG. 9, with the second circuit connected to an artificial neuron;

[0052] FIG. 13 is analogous to FIG. 9, with the second circuit converted into an artificial neuron;

[0053] FIG. 14 shows exemplary curves of signals relating to the circuit of FIG. 13; and

[0054] FIG. 15 is a graph showing the frequency of the electrical pulses which are obtained at the output of the circuit of FIG. 13, depending on the power of the signal at the input.

DETAILED DESCRIPTION

[0055] FIG. 1a) schematically illustrates an exemplary detector 10 according to the invention implemented in a telecommunications node 1 forming part of a network of wireless sensors. In addition to the detector 10, the telecommunications node 1 comprises a main transceiver 12 and a control unit 14, for example a microcontroller. The detector 10 is connected at its input to an antenna 18, notably an RF antenna, and at its output to the control unit 14, which communicates with the main transceiver 12.

[0056] The timing diagrams of FIG. 1b) illustrate the power of the signals as a function of time. The detector 10 is continuously monitoring the radio channel, unlike the main transceiver 12. Upon receiving an RF signal 17 sent by another telecommunications node 2, the detector 10 sends a switching signal 11 to the control unit 14, which activates the main transceiver 12 by means of an activation signal 15. Once activated, the transceiver 12 acknowledges receipt of the signal 17 and enters into communication with the node 2 for exchanging data. Thus, the detector 10 acts as a wake-up radio by waking up the main transceiver 12.

[0057] The detector 10 may also be used as a demodulator of the received RF signal, making it possible to continuously recover the information attached to the carrier of the RF signal and thus fulfil the function of a radiocommunication receiver operating in extremely low power consumption conditions (gain of 100,000), all the performance qualities remaining otherwise the same.

[0058] As shown in FIG. 2, the detector 10 according to the invention comprises a first circuit 20 and a second circuit 30 which is connected at the output of the first circuit 20.

[0059] The first circuit 20 possesses two inputs: an input e1 to which the RF signal to be detected is applied and an input e2 to which a control voltage is applied. The purpose of the first circuit 20 is to set the operating point at the output to a predefined DC voltage to which a variable part which is dependent on the signal from the input e1 is added. The structure and the operation of the first circuit 20 will be described in detail below.

[0060] The waveform of the signal at the output S of the second circuit 30 depends on the architecture of the latter and on the waveform of the RF signal at the input, that is to say on the use which is made of the detector 10, as will be explained below. The signal at the output of the second circuit is either in binary form after demodulation of the modulated RF signal applied at the input, or in the form of electrical pulses, the frequency of which is proportional to the power of the RF signal applied at the input in CW (continuous wave) mode.

[0061] FIG. 3 schematically shows an exemplary embodiment of the first circuit 20, depicting the currents flowing in the steady state. The first circuit 20 comprises a bridge of NMOS transistors which are connected at a midpoint M: a pull-up transistor M1 and a pull-down transistor M0.

[0062] The drain of the transistor M1 is connected to the supply voltage Vdd, its source to the midpoint M and its gate defines the input e1. In the steady state, no RF signal is applied to the gate of the transistor M1. Thus, everything proceeds as if this gate was connected to ground. The drain of the transistor M0 is connected to the midpoint M, its source to the supply voltage Vss and its gate defines the input e2 to which a control voltage Vc is applied. Thus, the transistor M0 operates as a constant current source I0 making it possible to adjust the quiescent DC voltage of the point M.

[0063] The fan-out of the first circuit 20 is modelled by a capacitor Cm at the input of the second circuit 30.

[0064] The potential at the point M, labelled Vm, is adjusted so that the gate-source voltage V.sub.gs1 of M1, which is equal to (Vm), is below the threshold voltage Vth of the transistor M1. It should be noted that, if Vss=0 V, this condition is de facto met.

[0065] In these conditions, the following analytical relationships are obtained, I1 being the drain current of M1, V0 the thermal stress, n the ideality coefficient, k the Boltzmann constant, T the ambient temperature and q the electric charge of an electron:

[00001]$\begin{array}{cc}I1={\mathrm{Is}}_1.Math.e^{{}_{}\frac{\mathrm{Vgs}1}{\mathrm{Vo}}}=e^{{}_{}\frac{-\mathrm{Vm}}{\mathrm{Vo}}}& \left[\mathrm{Math}1\right]\end{array}$$\left(\mathrm{Vo}=\frac{n.Math.k.Math.T}{q}=40\mathrm{mV},n=1.5\right)$$\mathrm{Io}={\mathrm{Is}}_o.Math.e^{{}_{}\frac{\mathrm{Vc}}{\mathrm{Vo}}}\left(\mathrm{constant}\mathrm{current}\mathrm{source}\right)$

[0066] Without an RF signal applied, the voltage Vm in DC terms, labelled Vm_DC, may be deduced from these relationships:

[00002]$\begin{array}{cc}\mathrm{Vm\_DC}=\mathrm{Vo}.Math.\ln \left(\frac{{\mathrm{Is}}_1}{{\mathrm{IS}}_0}\right)-\mathrm{Vc}& \left[\mathrm{Math}2\right]\end{array}$

[0067] It should be noted that this potential Vm_DC may be adjusted using Vc, if the lengths L and widths W of the gates of the transistors M1 and M0, respectively, are otherwise fixed.

[0068] It should also be noted that the transconductance of the transistor M1 is equal to:

[00003]$\begin{array}{cc}\mathrm{Gm}1=\frac{I1}{\mathrm{Vgs}1}=\frac{I1}{\mathrm{Vo}}& \left[\mathrm{Math}3\right]\end{array}$

[0069] The behaviour of the circuit in the small-AC-signal state, in particular the behaviour of the voltage Vm in this state, is illustrated in FIG. 4, a sinusoidal voltage being applied to the gate of M1.

[0070] The transmittance of the circuit Vm/VRF is of the following form, f being the frequency of the RF signal:

[00004]$\begin{array}{cc}\frac{\mathrm{Vm}}{\mathrm{VRF}}=.Math.\frac{1+j.Math.\frac{f}{f_1}}{1+j.Math.\frac{f}{f_2}}& \left[\mathrm{Math}4\right]\end{array}$

[0071] As a first approximation:

[00005]$\begin{array}{cc}{f}_1=\frac{\mathrm{Gm}1}{2.Math..Math.\mathrm{Cm}}\mathrm{and}{f}_2=\frac{\mathrm{Gm}1}{2.Math..Math.\left(C1+\mathrm{Cm}\right)}& \left[\mathrm{Math}5\right]\end{array}$

[0072] At high frequency, and in particular at frequencies where the RF signal is present, the ratio (Vm/VRF) is constant, and proportional to the ratio C1/(Cm+C1), this corresponding to a capacitive divider. It may be seen that: [0073] (i) on the one hand, the amplitude of the voltage Vm is low, but non-zero, and attenuated with respect to that of the RF signal, and [0074] (ii) on the other hand, there is residual voltage variation (set as a first approximation by the capacitive bridge).

[0075] In order to study the behaviour of the first circuit 20 charged by the input capacitor Cm of the second circuit 30, the nonlinearity of the function I.sub.D(V.sub.GS) (drain current as a function of the gate-source voltage) of the pull-up transistor M1 is utilized, in order to calculate the incremental DC value of the detected voltage Vm (in the steady state, after a rise time which follows the application of an RF signal).

[0076] The conversion of the signal V.sub.RF, generated at a frequency f.sub.RF, into an incremental DC voltage Vm, is illustrated in FIG. 5. The value of this increment Vm may range from several hundred V to several mV.

[0077] Starting from the expression of I1(V.sub.GS) of M1:

[00006]$\begin{array}{cc}I1={\mathrm{Is}}_1.Math.e^{{}_{}\frac{\mathrm{Vgs}1}{\mathrm{Vo}}}& \left[\mathrm{Math}6\right]\end{array}$

[0078] Vm being low, the following is obtained:

[00007]$\begin{array}{cc}\mathrm{Vgs}1\mathrm{Vgs}1\mathrm{\_DC}+V_{\mathrm{RF}}& \left[\mathrm{Math}7\right]\end{array}$$\begin{array}{cc}I1={\mathrm{Is}}_1.Math.e^{{}_{}\frac{\left(\mathrm{Vgs}1\mathrm{\_DC}+V_{{}_{}\mathrm{RF}}\right)}{\mathrm{Vo}}}=I1\mathrm{\_DC}.Math.\left[1+\frac{V_{\mathrm{RF}}}{\mathrm{Vo}}+\frac{1}{2}.Math.{\left(\frac{V_{\mathrm{RF}}}{\mathrm{Vo}}\right)}^2\right]& \left[\mathrm{Math}8\right]\end{array}$$V_{\mathrm{RF}}=\mathrm{Vs}.Math.\cos \left(t\right)$

[0079] Furthermore, the current i.sub.m assimilated by the capacitor Cm is equal to:

[00008]$\begin{array}{cc}{i}_m=I1-\mathrm{Io},\mathrm{with}\mathrm{Io}=I1\mathrm{\_DC}& \left[\mathrm{Math}9\right]\end{array}$

[0080] The DC value of the current i.sub.m is deduced therefrom:

[00009]$\begin{array}{cc}{i}_m\mathrm{\_DC}=I1\mathrm{\_DC}.Math.\frac{{\mathrm{Vs}}^{{}_{}2}}{4.Math.{\mathrm{Vo}}^{{}_{}2}}& \left[\mathrm{Math}10\right]\end{array}$

[0081] Thus, when an RF signal is present, an incremental DC current im_DC, which is proportional to the root-mean-square value of the RF voltage, is delivered by the pull-up transistor M1 and directed towards the capacitor Cm. This current im_DC charges the impedance of a capacitive nature Cm present at the point M.

[0082] After a transient time, the voltage Vm at the point M is modified by an incremental value with respect to its value at rest (in the steady state). If the RF signal is applied in CW mode, Vm will maintain this new value.

[0083] The circuit 20 is thus equivalent to the circuit illustrated in FIG. 6. It may be seen that the circuit 20 has a quadratic function with an output impedance equivalent to the capacitor Cm branching off a resistor R0. The transistor M1 being connected as a common drain, R0 is defined by:

[00010]$\begin{array}{cc}{R}_o~\frac{1}{\mathrm{Gm}1}=\frac{\mathrm{Vo}}{I1\mathrm{\_DC}}& \left[\mathrm{Math}11\right]\end{array}$

[0084] Thus, as soon as an RF voltage is applied to the circuit, an incremental voltage Vm is observed, which is written in the time domain in the form:

[00011]$\begin{array}{cc}\mathrm{Vm}=\mathrm{Ro}.Math.\mathrm{im\_DC}.Math.\left(1-e^{{}_{}-\frac{t}{}}\right),\mathrm{with}=R_o.Math.C_m=\left(\frac{1}{2.Math..Math.f1}\right)& \left[\mathrm{Math}12\right]\end{array}$

[0085] This is therefore a most classic case of capacitor charging, with an ultimate value of Vm, after simplification, equal to:

[00012]$\begin{array}{cc}\mathrm{Vm}\left[\mathrm{DC}\mathrm{voltage}\right]=\frac{V_S^{{}_{}2}}{4.Math.V_o}& \left[\mathrm{Math}13\right]\end{array}$

[0086] It should be noted that a variable part of the voltage Vm is superimposed on this voltage increment (cf. behaviour in the small-AC-signal state described above). When there is no longer an RF signal, the pull-down transistor Mo (constant current source) discharges the capacitor Cm, restoring the voltage Vm, after a transient time, to the value Vm_DC which was set in the steady state.

[0087] When the RF signal is modulated, taking into account the small increment Vm with respect to the value Vm_DC, it is useful to amplify this ripple. When the primary objective is to demodulate, the last amplification stages should saturate the signal which is amplified between the values Vdd and Vss. The amplification chain comprises, to this end, a series of inverters connected in a cascade in sufficient numbers.

[0088] A reminder of the transfer characteristic of a CMOS inverter below the threshold is given in FIG. 7, Gmax being the maximum voltage gain which may be obtained. This characteristic is plotted in the conditions: Vdd=200 mV and Vss=0 V. In order to benefit from the maximum voltage gain, the voltage V(in) must be adjusted to an optimum value V(in_opt).

[0089] A reminder of the circuit of a CMOS inverter is given in FIG. 8. This circuit, having A as input and Q as output, consists of a bridge of CMOS transistors which are connected in series and connected by their drains to the output Q. The input A is applied to the gates of the pull-up PMOS and pull-down NMOS transistors.

[0090] FIG. 9 schematically illustrates an exemplary second circuit 30 consisting of six inverters 32 in a cascade. The first three inverters of the chain amplify the ripple Vm without saturation. The last three inverters of the chain are configured to work in saturation mode, so that the signal at the output of each of the last three inverters substantially reaches the values Vdd and Vss. It should be noted that, for a second circuit operating as an open loop, an even number of inverters 32 should be used in a cascade in the chain.

[0091] For optimum operation, it is useful to adjust the voltage Vm of the first inverter 32 to a value close to V(in_opt), so as to fully benefit from the optimum voltage gain of this first inverter 32. Care should, however, be taken, when the control voltage Vc is adjusted, that the output voltage Vout remains at Vss.

[0092] It should be noted that the capacitor Cm corresponds, in the example of FIG. 9, to the input capacitor of the first inverter.

[0093] In the presence of an RF signal, taking into account the previous adjustment, the ripple Vm shown in FIG. 10 is first of all amplified (small-signal operation of the first three inverters), in order to ultimately reach an amplitude such that the last three inverters have a saturated output voltage, that is to say that the latter takes values equal to Vdd and Vss, a feature of the RF signal which is demodulated into baseband form. FIG. 10 shows the various signals V(k) obtained at the output of each inverter of rank k in the chain of inverters in a cascade.

[0094] It should be noted that, for a simulation of the circuit of FIG. 9, with an RF signal at the input having a frequency of 1 GHz and an amplitude Vs of 7 mV, the power consumption is 100 pW. This is a consumption several orders of magnitude lower than those of the prior art (for example, with respect to the circuit described in the publication Huang et al. A 915 MHz ultra-low power wake-up receiver with scalable performance and power consumption). It should be noted that, for the example of FIG. 9, the variation Vm approximately corresponds to the value given by theory.

[0095] FIG. 11 shows the waveform at the output of the circuit of FIG. 9 supplied with Vdd=200 mV and Vss=0 V, and does so for various amplitudes Vs of the RF signal (varying from 20 mV to 100 mV). A correspondence in terms of (theoretical) RF powers is also indicated. The output voltage makes it possible to make a decision on the binary value of the symbols modulating the RF carrier.

[0096] FIG. 12 shows that it is possible to connect the output of one inverter of the chain, in this instance the penultimate inverter, of rank 5, to a generic artificial neuron (for example, of leaky integrate-and-fire type) as illustrated in the figure. This makes it possible to generate electrical pulses which may be put to use to feed a spiking neural network (SNN). It should be noted that the frequency of the pulses produced does not depend on the amplitude of the RF signal.

[0097] The principle that a voltage across the terminals of a capacitor assimilates a current as described above may also be applied by associating with the first circuit 20 any artificial neuron acting as a second circuit 30 having a membrane capacitor. By way of illustration, the circuit presented in FIG. 12 may be directly transformed into an integrate-and-fire artificial neuron (i.e. proposed by Carver Mead since 1989). An example of such a circuit is shown in FIG. 13.

[0098] As illustrated in this figure, two components have been added to the circuit 30 of FIG. 9: a feedback capacitor Cf connected between the input and the output of the second circuit 30 (note that the membrane capacitor in this case consists of the input capacitor Cm of the first inverter 32 of the chain), and a feedback transistor Mf, in this instance of NMOS type, controlled by the output voltage of the second circuit 30 at the gate, the drain of which is connected to the input M of the second circuit and the source to ground.

[0099] This is thus the artificial neuron commonly called an axon hillock (AH) in the literature. It should be noted that the control voltage Vc, which serves to adjust the membrane voltage Vm of the AH neuron in the steady state, is unchanged with respect to the open-loop circuit previously described in FIG. 12.

[0100] When a CW RF signal is applied, the pulse at the output Vout_AH is triggered when the membrane voltage Vm reaches the switching threshold of the first inverter, causing positive feedback which contributes to a rapid increase of the voltage Vm, before the transistor Mf rapidly resets this voltage Vm and subsequently resets the output voltage Vout_AH.

[0101] The simulations illustrated in FIG. 14 present respective time curves of the membrane voltage Vm and of the output of the AH neuron (Vout_AH), for various amplitudes of the RF signal which is applied to the gate of the transistor M1.

[0102] Unlike pulses generated using a generic artificial neuron as described above in relation to FIG. 12, the frequency of the pulses generated in the example of FIG. 13 is dependent on the power of the RF signal. The frequency of the pulses as a function of the RF power is shown in FIG. 15. This curve shows the potential of this circuit to operate in the capacity of an RSSI, with an RF power (in this instance varying from 82 dBm to 62 dBm) coded as pulse frequencies (from50 kHz to 250 kHz). The linear dependency of the frequency of the pulses on the RF power should also be noted.

[0103] The invention is not limited to the exemplary embodiments described above.

[0104] Although the examples illustrated relate more particularly to the radio-frequency field, the detector according to the invention is compatible with the detection of waves in the acoustic or optical, notably infrared, bands.