DYNAMIC MODULATOR BIAS CONTROLLER WITH CONTINUOUS WAVEFORM CHARACTERIZATION VIA TWO OR MORE BIAS POINTS

Abstract

A communication system includes a laser that generates a laser light and a modulator that includes a modulation element configured to modulate the laser light with an input signal based on a bias voltage to produce an output signal. Control circuitry provides the bias voltage to a bias input of the modulation element and is configured to maintain a bias lock on at least two bias points of the modulation element during operation. The control circuitry is programmed to perform a bias lock operation that includes performing an initial voltage sweep on the modulation element and establish initial bias values for the at least two bias points. The circuit also providing a bias waveform to the bias input of the modulation element that varies over time and contains identifiable dither tones, determines harmonic power at the at least two bias points; and varies the bias waveform to determine harmonic power until the harmonic power is minimized to establish a bias lock with locked bias values.

Claims

1. A communication system comprising: a laser that generates a laser light; a modulator that includes a modulation element configured to modulate the laser light with an input signal based on a bias voltage to produce an output signal; control circuitry that provides the bias voltage to a bias input of the modulation element; and a signal splitter that receives the output signal and provides the output signal to an output of the system and to the control circuitry; wherein the control circuitry is configured to maintain a bias lock on at least two bias points of the modulation element during operation and is programmed to perform a bias lock operation that includes: performing an initial voltage sweep on the modulation element by ramping the bias voltage from a minimum value to a maximum and recording results of the initial sweep based on the output signal; establishing initial bias values for the at least two bias points by examining the results; providing a bias waveform to the bias input of the modulation element that varies over time and contains identifiable dither tones; determining harmonic power at the at least two bias points; and varying the bias waveform to determine harmonic power until the harmonic power is minimized to establish a bias lock with locked bias values.

2. The system of claim 1, wherein the control circuitry includes a photodiode, an analog to digital converter (ADC) and a digital signal processor (DSP).

3. The system of claim 2, wherein the signal splitter is connected to the photodiode and provides the output to the photodiode and the photodiode converts the output to an analog signal and provides the analog signal to the ADC.

4. The system of claim 3, wherein the ADC is connected to DSP and converts the analog signal to a digital signal and provides the digital signal to the DSP.

5. The system of claim 4, wherein DSP determines harmonic power of a second harmonic of the two or more bias points when either are quadrature positive (Qp) or a quadrature negative (Qn) bias point.

6. The system of claim 4, wherein DSP determines harmonic power of a third harmonic of the two or more bias points when are either a peak or null bias point.

7. The system of claim 6, further comprising a digital to analog converter (DAC) connected between the DSP and the bias input of the modulation element.

8. The system of claim 1, wherein the control circuitry is further programmed to add a dither signal to the bias signal at each locked bias value.

9. The system of claim 8, wherein the control circuitry is further programmed to reduce an amplitude of the dither signal to reduce signal to noise ratio of the harmonic power.

10. A method of operating a communication system that includes a laser that generates a laser light and a modulator that includes a modulation element configured to modulate the laser light with a data signal and a bias signal to produce an output signal, the method comprising: providing with control circuitry the bias voltage to a bias input of the modulation element; splitting the output signal and providing the output signal to an output of the system and to the control circuitry; maintaining a bias lock on at least two bias points of the modulation element during operation with the control circuitry, wherein maintaining includes: performing an initial voltage sweep on the modulation element by ramping the bias voltage from a minimum value to a maximum and recording results of the initial voltage sweep based on the output signal; establishing initial bias values for the at least two bias point by examining the results; providing a bias locking signal to the bias input of the modulation element that varies sequentially over each of the initial bias values over time; determining harmonic power at the initial bias values; and varying the biasing signal around the initial bias values; and determining harmonic power until the harmonic power is minimized to establish a locked bias signal with locked bias values.

11. The method of claim 10, wherein the control circuitry includes a photodiode, an analog to digital converter (ADC) and a digital signal processor (DSP).

12. The method of claim 11, wherein the signal splitter is connected to the photodiode and provides the output to the photodiode and the photodiode converts the output to an analog signal and provides the analog signal to the ADC.

13. The method of claim 12, wherein the ADC is connected to the DSP and converts the analog signal to a digital signal and provides the digital signal to the DSP.

14. The method of claim 13, wherein DSP determines harmonic power of a second harmonic of the two or more bias points when either are a quadrature positive (Qp) or a quadrature negative (Qn) bias point.

15. The method of claim 14, wherein DSP determines harmonic power of a third harmonic of the two or more bias points when either are a peak or null bias point.

16. The method of claim 10, further comprising adding a dither signal to the bias signal at each locked bias value.

17. The method of claim 16, further comprising: reducing an amplitude of the dither signal to reduce signal to noise ratio of the harmonic power.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 illustrates a block diagram of a low frequency phase detection system according to a non-limiting embodiment; and

[0020] FIG. 2 illustrates a functional block diagram of a high frequency phase detection system according to a non-limiting embodiment;

[0021] FIG. 3 shows certain parameters that are tracked and/or optimized according to embodiments;

[0022] FIG. 4a shows error that can exist based on an initial bias lock sweep;

[0023] attained;

[0024] FIG. 4b after initial bias lock has occurred;

[0025] FIG. 4c shows has dither can be utilized to optimize the lock;

[0026] FIG. 4d shows the normal operation with bias lock; and

[0027] FIG. 5 shows locking with drift.

DETAILED DESCRIPTION

[0028] As noted above, existing systems can track one bias point and, thus, adjust the bias voltage. However, while existing commercial bias controllers are bias locked, they are completely unaware of the other three bias points. To switch from one bias point to another, existing commercial modulator bias controllers must perform a search to find the newly commanded bias point.

[0029] During this search time, which can be considerable in duration, the data stream is corrupted. Additionally, successful locking of the newly commanded bias point is not guaranteed by existing commercial bias controller, which can result in unpredictable system behavior.

[0030] Disclosed herein is system that may overcome the above limitation by simultaneously tracking two or more (and in some cases, all four) bias points, simultaneously and continuously.

[0031] Embodiments can be commanded by application software to operate at any of the four bias points at will, switching rapidly between several points, or infrequently, as required by the application. This can be advantageous, for example, in systems that require frequent switching between multiple bias points. Additionally, one or more embodiments can operate similarly to existing commercial modulator bias controllers, where a single bias point is selected indefinitely.

[0032] FIG. 1 shows a system in the form of an optical transmitter 100 according to one embodiment. FIG. 1 shows the optical transmitter (or system) 100 as a functional block diagram.

[0033] The example optical transmitter 100 shown in FIG. 1 may be shown and described as discrete elements in a block diagram, and may be referred to as system, module, circuitry, or circuit, unless otherwise indicated, the components may be implemented as one of, or a combination of, analog circuitry, digital circuitry, or one or more microprocessors executing software instructions (e.g., predefined routines). In particular, the software instructions may include digital signal processing (DSP) instructions. Unless otherwise indicated, signal lines between components of the optical transmitter 100 may be implemented as discrete analog, digital, or optical signal lines. Some of the processing operations may be expressed in terms of calculations or determinations by the optical transmitter 100. The equivalent of calculating and determining values, or other elements, can be performed by any suitable analog or digital signal processing techniques and are included within the scope of this disclosure. Unless otherwise indicated, control signals may be encoded in either digital or analog form.

[0034] Referring to FIG. 1, one example of an optical transmitter 100 may include an input 102 to receive a data payload, an optical source (e.g., a laser) 104, a modulator 106, and optics 108, and an output 110 to provide an optical signal output. The modulator 106 imposes a modulation scheme on light from the optical source 104 to generate a modulated optical signal. In various examples, the modulator 106 may be an electro-optic modulator, and may include the optical source 104, such as a laser that generates laser light. In particular, the optical source 104 may emit a continuous carrier waveform that is modulated (e.g., in phase, amplitude, and/or frequency) for each symbol of the data payload to encode those symbols on the carrier waveform. The transmitter 100 may also include various optics 108 such as one or more mirrors or lenses to direct the optical signal at the output 110. Herein, the output 110 is referred to as SigOut 110.

[0035] FIG. 2 shows a more detailed version of a modulator 106 according to one embodiment. In combination with the laser, the modulator 106 can be referred to as a high frequency communication system and it receives, for example, a data payload 102 either form the system itself or from an external device that has message that is to be sent with the modulator 106.

[0036] In FIG. 2 circuit connections between elements are shown by different line types as identified by the legend in FIG. 2 to represent different signal types being carried. The configuration of the elements of FIG. 2 may be utilized in any embodiment disclosed herein. This embodiment may utilize a dithering technique in tracking the bias points. In other embodiments, the system may operate without dithering and may include, for example, additional photo diodes/ACD's.

[0037] The modulator 106 can include a modulation element 202 and control circuitry 204. In this example, the control circuitry 204 can includes a digital signal processor 206. The control circuit 204, generally, receives an output of the modulation element 202 and can vary the DC bias provided to the modulation element 202 based on the received output. In this example, the modulation element 202 is an MZ modulator that includes first and second paths 220, 222. The modulation element 202 in FIG. 2 is simplified for ease of explanation and the first path includes both the RF input port 230 and the DC bias input port 232.

[0038] As shown in FIG. 2, the input 102 provides an analog RF input signal (RF_In) to the modulation element 202 at RF input port 230. This RF signal modulates the phase of the light in the first path 220. When the two paths 220, 222 the changes to the signal in the first path 220 will be slightly modified and, thus, interfere with the signal in the second path 222 in a known manner to create and output light signal that carriers the RF_In information. This signal is shown a SigOut 110 in FIG. 2.

[0039] The modulation element 202 receives a bias input at the DC bias input port 232. The value of that bias was typically set based on single bias point. The system herein can track and, thus, switch, between two or more bias points. In one embodiment, all four bias points (as positive quadrature (Qp), negative quadrature (Qn), null (N), and peak (P)) can be tracked. These points are shown FIG. 3 for reference. It is noted that operating at the Qp and Qn point can provide the most linearity. However, there are other times where N and P can be beneficial for carrier suppression, millimeter wave applications, fundamental physics, and a broad array of other application.

[0040] The disclosed system/methods, as more fully disclosed below, can allow for rapidly switching between two or more bias operating points and continuously maintaining bias lock at all operating points. This may be done without having recalibrate or otherwise performing a voltage sweep to establish a lock at the new bias point. Further, embodiments can allow for rapidly switch between 2 or more bias operating points and continuously characterize the modulator's complete response. In addition, embodiments disclosed herein can be intermittently commanded from a single bias operating point directly to another single bias operating point.

[0041] With further reference to FIG. 3, consider that case of modulation element 202 as shown in FIG. 2. For a given voltage range for the DC output (e.g, 5V to 5V) the output signal SigOut 110 will be produced. In an ideal world, the peak would occur at 0V but defects may shift by a distance shown as V.sub.0 in FIG. 3. The will cause the output curve to deviate from a cos wave by V.sub.0 and, thus, is subtracted from Vin in the transfer function of the modulation element 202. The DC power transfer function can thus be represented as:

[00001]$\begin{array}{cc}P\left(V\right)=P_0.Math.\cos \left(\frac{.Math.\left(V-V_0\right)}{V_{-DC}}\right)& \left(1\right)\end{array}$

wherein P.sub.0 equals offset in power, V.sub.0 is the change in bias voltage needed to move the peak to the 0V location, and V.sub.-DC is the distance between Qp and Qn as shown in FIG. 3 and it related to the switching efficiency to the DC port 232

[0042] Assuming that the bias is correct (locked) the modulation element 202 will work as expected and the output signal SigOut 110 can be optimal. To ensure that that two or more of the bias points are being tracked and are locked, the system of FIG. 2 includes control circuitry 204. The circuitry 204 can track the bias points and correct as needed. The correction can be manifested in changes in the DC voltage provided to the DC port 232 of the modulation element 202.

[0043] The system of FIG. 2 can include a signal splitter 240 that receives SigOut 110 and provides two versions of it at its output. The first version is provided to (as shown in FIG. 1) to optics 108 to direct the optical signal at the output 110.

[0044] The second version is provided to the control circuitry 204. In particular, the light signal SigOut 110 is provided to photodiode 208 where the light signal is converted to an electrical signal (e.g., current or voltage). This electrical signal is then converted from analog to digital format by an analog to digital converter 210. This ADC provides a digital representation of the light signal (SigOut 110) to a digital signal processor (DSP) 206. The DSP can include memory and other circuits that allow it track the bias point and to create a digital output that represent a desired DC bias voltage. This digital output can be converted to an analog output by a digital to analog converter (DAC) 212 and then provided as the bias voltage provided to the DC port 232. As shown in FIG. 2 various direct connections are shown between elements. It shall be understood that indirect connections could be made if tuning/scaling is needed.

[0045] Optionally, to allow for ditherless bias control, the system of FIG. 2 can include a second signal splitter 262 that receives the laser signal and provides two versions of it at its output. The first version is provided to the modulation element 202. The second version is provided to the control circuitry 204. In particular, the light signal is provided to a second photodiode 258 where the light signal is converted to an electrical signal (e.g., current or voltage). This electrical signal is then converted from analog to digital format by an analog to second digital converter 260 that is provided to the digital signal processor (DSP) 206. Ditherless bias control operates by maintaining the power ratio between photodiode 258 and 208.

[0046] The DSP 206 can be configured to operate on the information it receives to achieve the desired DC offset voltage at the DC port 232. In short, based upon the digitized photodiode signal (output of photodiode 208) and DSP 206 operations, the waveform output by the DAC 212 is changed to simultaneously maintain lock on two or more (or all four) bias positions.

[0047] The bias control operation consists of an initial voltage sweep, followed by an initial bias lock, followed by continuous bias locking and acceptance of dynamic application commands. The warm-up period is complete and the system is operational following completion of the initial bias lock.

[0048] In more detail and with reference to FIGS. 2-4, The DSP 206 causes the DAC 212 to preform in a voltage sweep. The voltage sweep can sweep the voltage from, for example, 5 to 5V but other ranges can be utilized based on the operating parameters of the modulation element 202. In one embodiment, the output voltage is swept over the maximum permissible range of the modulator's DC port. Based on this initial sweep, the initial values of the values noted in FIG. 3 can be recorded. These values can be determined, for example, by modules within the DSP 206. It is noted, however, the values may not be exact and improvement may be needed. As shown in FIG. 4a, the initially determined values are in waveform 400a and are determined to be the values identified by lines 402, 404, 406 and 408. These values can also be referred to as initial values of V.sub.Qp, V.sub.Qn, V.sub.Null, and V.sub.Peak. These initial values represent the baseline value for the oscillating signals around which the dither signal (oscillations in FIG. 4a) is added and described further below. It shall be noted that an example fast Fourier transform (FFT) at the bias points is shown for explanation. This FFT can be by the FFT based on the output of photodiode. The FFT can be a discreet FFT in one embodiment.

[0049] The DC bias signal 400 is provided that sequentially moves from the 402, 404, 406 and 408. That it, it moves in the order for the initial value of Qp, to the initial value of Qn, to the initial value of the Null to the initial value of Peak. This order could be changed without departing from the disclosure herein.

[0050] Of interest for each bias points are the harmonics produced at each of the points 402, 404, 406 and 408. Of particular interest are the second harmonics for the Qn and Qp (2f.sub.qn and 2f.sub.qp) and the third harmonics for the Null and Peak (3f.sub.n and 3f.sub.p). This selection is based on the small signal Taylor expansion of the modulators cosine transfer function about the linear bias points Qp and Qn (where optimal locking extinguishes the second harmonic), and the quadratic bias points Null and Peak (where optimal locking extinguishes the third harmonic).

[0051] As shown in FIG. 4b, for each bias point a dither tone is added onto the initial bias points. For example, the Qp bias waveform is:

[00002]$V\left(t\right)=V_{\mathrm{Qp}}+A_{\mathrm{Qp}}.Math.\sin \left(2f_{\mathrm{Qp}}t\right)$

wherein V.sub.Qp is the initial bias point, A.sub.Qp is the amplitude of the dither tone and fop is the frequency of the dither tone. Further, for the peak and null bias points, V (t) is similar but a cosine function is used. It should be noted that in all of the bias signals 400, the dither is shown but the skilled artisan will realize that it can be omitted form signals 400.

[0052] Bias locking is accomplished by adjusting the initial bias voltages V_Qp, V_Qn, V_P, and V_N until their associated photo-detected harmonics at frequencies 2f.sub.qn, 2f.sub.qp, 3f.sub.n, 3f.sub.p are minimized. It shall be understood that bias locking is achieved by minimizing the relevant harmonic frequency's power by adjusting the relevant voltage. In one embodiment, bias locking can be accomplished at one operating point only, using one frequency only. In another embodiment, all four are minimized simultaneously. Embodiments minimizing the harmonics of 2 or 3 harmonics are also manifested.

[0053] Initial bias locking has been accomplished when modifying the initial bias values V.sub.QP, V.sub.QN, V.sub.null, and V.sub.peak only increases the harmonic power. This is shown in FIG. 4b. In FIG. 4b the corrected/locked values are shown and identified by reference numerals 402b, 404b, 406b and 408b. It shall be understood that this process can include locating a DAC output value (e.g, DC bias voltage) where increasing and decreasing the DC bias voltage results in increase of the harmonic power.

[0054] Thus, this step can include moving the locations of initially determined values 402, 404, 406 and 408 until the above condition is reached and is indicated by locked bias voltage 400b. For example, if the initial value for the Qp value 402 was 2V, the value could be increased to 2.1V. Then the harmonics could be examined as discussed FIGS. 4a and 4b. Then, the value could be incremented (e.g, to 2.11V) and the harmonics compared. If the harmonics increased, then the next value could be a reduced value (e.g, 2.09V). This value can then be decreased until the harmonics stop decreasing. Then a final check can be made in the same manner until movement of the DC bias in either direction results in an increase in harmonic power. The resultant values can be part of a locked bias signal 400b shown in FIG. 4b.

[0055] Next the lock can be optimized. This can include one or both of reducing noise floor and the amplitude of the dither tones to reduce the SNR. In more detail, such an optimization can include, while maintaining bias locking (e.g, via signal 400c), adjusting parameters t.sub.PD-RECORD of the ADC 210 and the sample rate f.sub.PD-SMPL of the ADC 210 to reduce the noise floor of the spectral trace containing the harmonic tones produced in DSP 206. Effort should be made to ensure the duration of the time-series recording of the photodiode voltage, given by t.sub.PD-RECORD, is an integer multiple (1 to n) of the time series duration of the bias waveform produced by the DAC 212.

[0056] In some embodiments, the system can dynamically adjust record length t.sub.PD-RECORD and ADC sample rate f.sub.PD-SMPL to minimize excess injection of the bias control waveform in to SigOut 110.

[0057] Further, the dither amplitudes A.sub.QP, A.sub.QN, A.sub.null, and A.sub.peak are reduced until the signal-to-noise ratio (SNR) of the respective harmonics equals a target value as shown in FIG. 4c with signal 400c.

[0058] In some embodiments can dynamically adjust dither amplitude (A.sub.Qp, A.sub.Qn, A.sub.N, A.sub.P) to minimize excess injection of the bias control waveform in to SigOut 110.

[0059] As will be appreciated by a skilled artisan, by knowing two of the bias points at all times, the modulator's DC response parameters V_pi-DC and V_0 can be calculated, and the response to a DC voltage sweep can be known. Thus, the applied bias tracking waveform can achieve modulator characterization by tracking only two of the bias points. In FIG. 4d an example shows 3 bias points being tracked with signal 400d, in this case, Qp, Qn, and Peak. Other values could also be tracked instead. Further, if the bias point were to be changed, for example to Null, that value is already known.

[0060] In the system and methods disclosed herein, continuous modulator characterization requires a repeating sequence of 2 or more bias operating points which completes 1 or more times every t.sub.PD-RECORD.

[0061] Intermittent modulator characterization is performed whenever the requirements for continuous characterization are not met. Therefore, intermittent modulator characterization is performed for: (1) command sequences where t.sub.PD-RECORD<t.sub.SEQ and (2) for single bias operating point commands. In all cases, the bias operating point is continuously locked.

[0062] Continuous modulator characterization captures the modulator's entire DC bias response function every t.sub.PD-RECORD. This is done by directly measuring V.sub.-DC and V.sub.0 over the course of one photodiode record, without sweeping the modulator's voltage. V.sub.-DC and V.sub.0 are calculated using the known relationships between two or more locked bias voltages V.sub.QP, V.sub.QN, V.sub.null, and V.sub.peak.

[0063] Intermittent modulator characterization captures the modulator's entire DC bias response function, once every time the bias operating point changes. This is done by directly measuring V.sub.-DC and V.sub.0 over the course of several photodiode records, without sweeping the modulator's voltage. VI-DC and V.sub.0 are calculated using the known relationships between two or more locked bias voltages V.sub.QP, V.sub.QN, V.sub.null, and V.sub.peak.

[0064] From the above discussion, it shall be understood that embodiments herein may be able to maintaining bias lock indefinitely at one of four bias operating point. However, in contrast the prior art, embodiments herein can track two or more operating points simultaneously and thus, can rapidly switch between 2 or more bias operating points and continuously may maintain bias lock at all operating points. This is done without performing a voltage sweep or losing bias lock.

[0065] By tracking at least two of the points (and possibly all four) embodiments disclosed herein can rapidly switch between 2 or more bias operating points and continuously characterize the modulator's complete response. This is done without performing a voltage sweep or losing bias lock.

[0066] Embodiments may be able to be intermittently commanded from a single bias operating point directly to another single bias operating point. The transition from one bias operating point to the other is accomplished without performing a voltage sweep.

[0067] For continuous modulator characterization conditions, the transition from one bias operating point directly to the other is accomplished without losing bias lock. The transition from one bias operating point to the other is accomplished without performing a voltage sweep.

[0068] For intermittent modulator characterization conditions, and for modulators that do not experience V.sub.-DC drift, the transition from one bias operating point directly to the other is accomplished without losing bias lock. The transition from one bias operating point to the other is accomplished without performing a voltage sweep.

[0069] For intermittent modulator characterization conditions, and for modulators that do experience V.sub.-DC drift, the transition from one bias operating point directly to the other introduces a voltage error proportional to the V.sub.-DC drift, which is small, after which bias lock is quickly established, see FIG. 5. The transition from one bias operating point to the other is accomplished without performing a voltage sweep.

[0070] Embodiments may be able to determine the characteristic drift time (t.sub.DRIFT) over which the modulator's bias voltage drifts. This can be accomplished because two or more points are simultaneously tracked and logged in DSP 206.

[0071] As used herein, the term module refers to an application specific integrated circuit (ASIC), an electronic circuit, a computer processor (shared, dedicated, or group) and memory that executes one or more software or firmware programs, a combinational logic circuit, a microcontroller including various inputs and outputs, and/or other suitable components that provide the described functionality. When implemented in software, a module can be embodied in memory as a non-transitory machine-readable storage medium readable by a processing circuit (e.g., a microprocessor) and storing instructions for execution by the processing circuit for performing a method.

[0072] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.