ARCP CONVERTER AND CONTROL THEREOF

Abstract

A power converter system includes an auxiliary resonant commutated pole converter leg, particularly an ARCP half-bridge, having a series connection of a saturable-core inductor and at least one bi-directional auxiliary switch connected to a dc-link neutral point. An ARCP controller is provided to control turn-on of the at least one bi-directional auxiliary switch to provide an auxiliary current flowing through the saturable-core inductor, and a saturation instant detector is provided to detect a saturation instant of the saturable-core inductor due to the auxiliary current exceeding a saturation current after turn-on of the at least one bidirectional auxiliary switch. The ARCP controller is responsive the detector to continue providing the auxiliary current and thereby a boost current for a predetermined boost period after the detected saturation instant of the saturable-core inductor to achieve a desired total boost current.

Claims

1. A power converter system, comprising an auxiliary resonant commutated pole (ARCP) converter leg, particularly an ARCP half-bridge, having a series connection of a saturable-core inductor and at least one bi-directional auxiliary switch connected to a dc-link neutral point, a ARCP controller configured to control turn-on of the at least one bi-directional auxiliary switch to provide an auxiliary current flowing through the saturable-core inductor, and a saturation instant detector configured to detect a saturation instant of the saturable-core inductor due to the auxiliary current exceeding a saturation current after turn-on of the at least one bidirectional auxiliary switch, wherein the ARCP controller is responsive the detector to continue providing the auxiliary current and thereby a boost current for a predetermined boost period after the detected saturation instant of the saturable-core inductor so as to achieve a desired total boost current.

2. The power converter system as claimed in claim 1, wherein the predetermined boost period is calculated based on an inductance of a resonant inductor connected in series with the saturable-core inductor, optionally taking into account a saturated inductance of the saturable-core inductor.

3. The power converter system as claimed in claim 1, wherein the saturable-core inductor comprises a primary winding and a secondary winding, the auxiliary current flowing through the primary winding, and the saturation instant detector is connected to the secondary winding and configured to detect the saturation instant based on a voltage induced in the secondary winding.

4. The power converter system as claimed in claim 1, wherein the saturation instant detector is connected to the dc-link neutral point and configured to detect the saturation instant based on a voltage of the dc-link neutral point.

5. The power converter system as claimed in claim 1, wherein the saturation instant detector comprises an auxiliary current sensing unit to sense a rapid change in the auxiliary current.

6. The power converter system as claimed in claim 5, wherein the auxiliary current sensing unit comprises a Hall sensor or a Rogowski coil.

7. The power converter system as claimed in claim 1, wherein the ARCP converter leg further comprises: a series connection of at least two main switching devices between the positive dc-link potential and the negative dc-link potential to alternatively connect the positive and negative dc-link potential, and a resonant capacitor associated with each of the at least two main switching devices.

8. The power converter system as claimed in claim 1, comprising a plurality of ARCP converter legs.

9. A power converter system, comprising an auxiliary resonant commutated pole (ARCP) converter leg, particularly an ARCP half-bridge, having a series connection of a saturable-core inductor and at least one bi-directional auxiliary switch connected to a dc-link neutral point, a ARCP controller configured to control turn-on of the at least one bi-directional auxiliary switch to provide an auxiliary current flowing through the saturable-core inductor, and a saturation instant detector configured to detect a saturation instant of the saturable-core inductor due to the auxiliary current exceeding a saturation current after turn-on of the at least one bidirectional auxiliary switch, wherein the ARCP controller is responsive the detector to continue providing the auxiliary current and thereby a boost current for a predetermined boost period after the detected saturation instant of the saturable-core inductor so as to achieve a desired total boost current, and wherein the saturation instant detector is connected to the dc-link neutral point and configured to detect the saturation instant based on a voltage of the dc-link neutral point.

10. A power converter system, comprising an auxiliary resonant commutated pole (ARCP) converter leg, particularly an ARCP half-bridge, having a series connection of a saturable-core inductor and at least one bi-directional auxiliary switch connected to a dc-link neutral point, a ARCP controller configured to control turn-on of the at least one bi-directional auxiliary switch to provide an auxiliary current flowing through the saturable-core inductor, and a saturation instant detector configured to detect a saturation instant of the saturable-core inductor due to the auxiliary current exceeding a saturation current after turn-on of the at least one bidirectional auxiliary switch, wherein the ARCP controller is responsive the detector to continue providing the auxiliary current and thereby a boost current for a predetermined boost period after the detected saturation instant of the saturable-core inductor so as to achieve a desired total boost current, and wherein the saturation instant detector comprises an auxiliary current sensing unit to sense a rapid change in the auxiliary current.

11. The power converter system as claimed in claim 10, wherein the auxiliary current sensing unit comprises a Hall sensor or a Rogowski coil.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In the following the invention will be described in greater detail by means of preferred embodiments with reference to the accompanying drawings, in which

[0021] FIG. 1 is a schematic diagram illustrating an exemplary ARCP inverter;

[0022] FIGS. 2A-2F are diagrams illustrating an example of mode A commutation;

[0023] FIGS. 3A-3D are diagrams illustrating an example of mode B commutation;

[0024] FIG. 4 is a schematic diagram illustrating an auxiliary circuit with a saturable-core inductor and alternative auxiliary switch position compared to FIG. 1;

[0025] FIG. 5 illustrates an example of behaviour of an auxiliary current in theory and in practice in a basic ARCP commutation;

[0026] FIG. 6 illustrates an example of behaviour of a auxiliary current Ia in theory and in practice in an ARCP commutation having a boost time control according to an embodiment of the invention;

[0027] FIG. 7 is a schematic diagram illustrating an exemplary detector or sensing circuitry according to an embodiment of the invention;

[0028] FIG. 8 presents simplified waveforms of the boost current and the output voltage of the sensing circuitry of FIG. 7;

[0029] FIG. 9 is a schematic diagram illustrating an exemplary detector or sensing circuitry according to another embodiment of the invention;

[0030] FIG. 10 presents simplified waveforms of the boost current and the output voltages of the sensing circuitry of FIG. 9; and

[0031] FIG. 11 is a simplified flow diagram illustrating an exemplary boost time control according to an embodiment of the invention.

DETAILED DESCRIPTION

[0032] A dc-ac or ac-dc converter, also known as an inverter or a rectifier respectively, converts power from dc to ac or ac to dc power system at desired voltages and frequencies. Further, a dc-dc converter, such as a dc chopper, converts power from dc to dc power system. Although embodiments are described using inverters and inverter systems as examples, the invention is similarly applicable to rectifiers and rectifier systems as well as dc-dc converters. Inverter and rectifier can be exactly similar in structure and the control operations can be similar, the difference being the direction of a power flow. When a converter operates as an inverter (dc/ac converter), it converts the power from a dc system to an ac system, i.e., the ac side of the converter is referred as an output side and the dc side is considered as an input side. When a converter operates as a rectifier (ac/dc converter), it converts power from an ac system to a dc system, i.e., the ac side of the converter is considered as an input side and the dc side is considered as an output side. Further, connecting ac/dc and dc/dc converters in back-to-back configuration, i.e. dc-sides connected together, between two ac systems, one of the converters is operating in rectifier mode and the other in inverter mode, depending on the power flow direction. Operation modes of the converters may vary during the operation, as power flow may vary.

[0033] It shall be appreciated that the modulation control according to embodiments of the invention is universally applicable to any type of ARCP inverters and their derivates and modifications regardless the specific design, configuration, and operation variations of an inverter from a basic ARCP inverter. The basic configuration and operation of ARCP is described, for example, an article The auxiliary resonant commutated pole converter, IEEE-IAS Conference Proceedings 1990, pp. 1228-35, and in U.S. Pat. No. 5,047,913 by R. W. De Doncker et al. The ARCP inverter can be implemented using various topologies, which all perform essentially similarly. The schematic of an exemplary ARCP inverter 1 is illustrated in FIG. 1 and described herein in order to alleviate comprehending operation and configuration of embodiments of the invention in relation to an exemplary basic ARCP. It is not intended to limit embodiments of the invention to the described and illustrated exemplary ARCP.

[0034] The exemplary ARCP inverter INV1 illustrated in FIG. 1 may be a bridge inverter including a DC-link 2 and a power section 10. The DC-link may include a DC-link 2 comprising a first dc-link rail 2, a second dc-link rail 24, a first dc-link capacitor C.sub.d1 coupled with the first de-link rail 22 and a dc-link midpoint, called a neutral point NP1, and a second dc-link capacitor C.sub.d2 coupled with the second dc-link rail 24 and the neutral point NP1. During operation, the first dc-link rail 22 is at a first voltage, so called positive (P) dc-link potential, and the second dc-link rail 24 is at a second voltage lower than the first DC voltage, so called negative (N) dc-link potential, and the dc-link midpoint NP is at a midpoint voltage, so called neutral point voltage U.sub.NP. The capacitances of the dc-link capacitors C.sub.d1 and C.sub.d2 are substantially equal, for example C.sub.d1=C.sub.d2=2C.sub.dc, so that the voltages U.sub.1 and U.sub.2 provided across the dc-link capacitors C.sub.d1 and C.sub.d2 series-connected between the dc-link rails 22 and 24 are substantially equal, i.e. a half of a dc-link voltage U.sub.dc=U.sub.1+U.sub.2 between the dc-link rails 22 and 24. Thus, also the neutral point voltage or potential U.sub.NP essentially corresponds to half of the voltage U.sub.dc, in other words U.sub.NP=U.sub.dc/2.

[0035] The dc-link rail 22 (the positive dc-link potential P) and the dc-link rail 24 (the negative dc-link potential N) may be connected to a first voltage terminal U.sub.dc+ and a second voltage terminal U.sub.dc of the common DC power source 4. The common dc power input to the parallel-connected ARCP inverter modules INV1 and INV2 may be obtained from any kind of a dc power source 4, such as from an existing power supply network through a rectifier, or from a battery, fuel cell, photovoltaic array, etc. It shall be appreciated that dc-link 2 may be provided in a number of forms and may have a number of voltages and other attributes. It shall also be appreciated that the voltage difference between positive and negative dc-link rails is flexible, depending on how the dc-link 2 is charged or how the dc-link 2 is discharged by the connected circuits. For example, some embodiments may use a front-end isolation transformer and rectifier connected to the dc-link with the positive and negative rails floating and the differential voltage typically in the range of 50V-1500V, but in principle in other voltages outside this range as well. In other embodiments, the positive rail, mid-point, or negative rail may be grounded to earth. Preferably, the positive and negative rails are balanced. For example, if the dc-link neutral point NP is at 0 VDC, dc-link rail 22 would be at a positive voltage (e.g., in the range of +25 VDC to +500 VDC, the range of in the range of +150 VDC to +400 VDC or other positive voltage ranges) and dc-link rail 24 would be at a negative voltage corresponding to the positive voltage (e.g., in the range of 25 VDC to 500 VDC, the range of in the range of 150 VDC to 400 VDC or other negative voltage ranges corresponding to the other positive voltage ranges). It shall be appreciated that the foregoing examples are few of many voltage magnitudes and polarities that may be present in or associated with the operation of dc-link 2. It shall be additionally appreciated that the voltage magnitudes of the foregoing examples may be subject to fluctuation, margins of error, tolerance, and other variations and may not be rigidly fixed to the precise example magnitudes stated. It shall be further appreciated the term bus may be utilized in place of the term link such that, for example, references to a dc-link are understood to encompass a dc-bus and vice versa.

[0036] The exemplary half-bridge power section 10 illustrated in FIG. 1 may include a pair of main or power switching devices S.sub.1 and S.sub.2 coupled in parallel to the dc-link rails 22 and 24 of the de-link 2. The first main switching device S.sub.1 may have a first terminal electrically coupled to the positive dc-link rail 22 and a second terminal electrically coupled to an output node 110. The second main switching device S.sub.2 may have a first terminal coupled to output node 110 and a second terminal coupled to the negative dc-link rail 24. Across the first main switching device S.sub.1 between the positive dc-link rail 22 and the output node 110 is connected a first antiparallel diode D.sub.1, and across the second main switching device S.sub.2 between the output node 110 and the negative dc-link rail 24 is connected a second antiparallel diode D.sub.2. Further, a first resonant capacitor C.sub.1 is operationally connected (i.e., directly or via additional components, such as an active or passive damping circuit series connected with the resonant capacitor) in parallel with the first main switching device S.sub.1, and a second resonant capacitor C.sub.2 is operationally connected in parallel with the second main switching device S.sub.2. More generally, there may be one or more resonant capacitors connected in such manner that at least one terminal of the resonant capacitor(s) is connected to one of the dc-link rails (P, NP, N) and the other terminal(s) is (are) operationally connected to the phase output node 110. The first main switching device S.sub.1 is operable to turn on and turn off, and thereby to respectively connect and disconnect the de-link rail 22 and the output node 110, in response to control signal(s) G.sub.1 received from a control and driver circuitry, such as an inverter-specific ARCP switching controller 8 illustrated in FIG. 1. The second main switching device S.sub.2 is operable to turn on and turn off, and thereby to respectively connect and disconnect the dc-link rail 24 and the output node 110, in response to control signal(s) G.sub.2 received from the control and driver circuitry, such as the ARCP switching controller 8.

[0037] In embodiments, the switching devices S.sub.1 and S.sub.2 may be an insulated-gate bipolar transistor (IGBT), or another type of semiconductor switching device, such as an integrated gate-commutated thyristor (IGCT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a silicon carbide (SiC) MOSFET to name several examples.

[0038] It should be appreciated that although a single-phase ARCP inverter is illustrated as an example herein, an ARCP inverter may be implemented as a three-phase inverter, or generally include any number of inverter phases or inverter legs. Moreover, although a half-bridge ARCP inverter is illustrated as an example herein, the ARCP inverter may have other configurations, particularly a full-bridge configuration. In a multi-phase inverter, there may be an identical ARCP power section 10 for each phase or inverter leg of the inverter, and a common or dedicated dc-link 2 for each phase or inverter leg. In embodiments, power sections 10 of inverter legs in a multi-phase ARCP inverter may be controlled by a same inverter-specific switching controller 8. In embodiments, two or more ARCP inverters or inverter legs may be connected in parallel to feed a common load.

[0039] In operation, when the first main switch S.sub.1 is turned on (to a conductive state), a first switch current Is can flow between the dc-link rail 22 and the output node 110. Similarly, when the second main switching device S.sub.2 is turned on (to a conductive state), a second switch current I.sub.s2 can flow between the output node 110 and the de-link rail 24. On the other hand, when the first main switching device S.sub.1 is turned off (to a non-conductive state), the first switch current I.sub.s1 will not flow in the switch-forward direction between the dc-link rail 22 and the output node 110, although a current I.sub.d1 may flow in the switch-reverse direction through the first anti-parallel diode D.sub.1 of the first main switching device S.sub.1. Similarly, when the second main switching device S.sub.2 is turned off (to a non-conductive state), the second switch current I.sub.s2 not flow in the switch-forward direction between the output node 110 and the de-link rail 24, although a current I.sub.d2 may flow in the switch-reverse direction through the anti-parallel diode D.sub.2 of the second switching device S.sub.2. Thus, by turning on and off the first main switching device S.sub.1 and the second main switching device S.sub.2, the output voltage at the output node 110 will be controlled or commutated to be either the voltage P from the dc-link rail 22 or the voltage N from the dc-link rail 24. The purpose of the resonant capacitors C.sub.1 and C.sub.2 is to limit the voltage slew rate of the output node; this ensures that the voltages U.sub.c1 and U.sub.c2 across the main switching devices S.sub.1 and S.sub.2 do not significantly change during turn-off such that the main switching devices are turned off at essentially zero-voltage.

[0040] The exemplary half-bridge power section 10 of the ARCP inverter illustrated in FIG. 1 further includes an auxiliary circuit comprising a resonant inductor L.sub.1 and a bidirectional auxiliary switch S.sub.aux1 connected in series between the neutral point NP and the output node 110. It shall be appreciated that the resonant inductor and auxiliary switch may be located in any order in an ARCP circuit without having effect on the invention The auxiliary switch S.sub.aux1 is operable to turn on and turn off, and thereby to respectively connect and disconnect the neutral point and the output node 110, in response to control signals received from the control and driver circuitry, such as the ARCP switching controller 8. The auxiliary switch S.sub.aux1 can behave like a bidirectional thyristor: it can be triggered into conduction, and it turns off if or before the current tries to reverse its direction. In embodiments, the bidirectional auxiliary switch S.sub.aux1 may be implemented with a pair of ordinary switching devices connected back-to-back, for example in a common-emitter or common-collector configuration and provided with anti-parallel diodes. FIG. 1 illustrates an exemplary auxiliary switch S.sub.aux1 comprising a first auxiliary switching device Sat and a second auxiliary switching device Sa.sub.2 in a common-emitter series connection, a first anti-parallel diode Da.sub.1 connected across the first auxiliary switching device Sa.sub.1, and a second antiparallel diode Da.sub.2 connected across the second auxiliary switching device Sa.sub.2. To initiate a new output commutation, one of the two auxiliary switching devices Sa.sub.1 and Sa.sub.2 is turned on and conducting at a time, in response to control signals Ga.sub.1 and Ga.sub.2 received from a control and driver circuitry, such as an ARCP switching controller 8 illustrated in FIG. 1. Depending on the main switching devices S.sub.1 and S.sub.2 conducting states, one of the two antiparallel diodes Da.sub.1 and Da.sub.2 may be forward biased and thus start conducting current. In this case, the auxiliary current I.sub.a will flow through one forward biased diode in series with one switch. The auxiliary switching devices in the auxiliary circuit are preferably turned on and off at zero-current. When the first auxiliary switching device Sa.sub.1 is turned on and the second switching device Sa.sub.2 is turned off, the auxiliary current I.sub.a1 will flow in one direction through Sa.sub.1 and Da.sub.2. When the first auxiliary switching device Sa.sub.1 is turned off and the second switching device Sa.sub.2 is turned on, the auxiliary current I.sub.a will flow in the opposite direction through Sa.sub.2 and Da.sub.1. The auxiliary circuit is only used when the output node 110 is required to commutate from one voltage rail to the other. The auxiliary circuit functions by creating a pulse of current that, in combination with the resonant capacitors, is used to slew the output voltage on the output node 110.

[0041] The ARCP switching control 8 illustrated in FIG. 1 refers generally to any control functions, logic, hardware, firmware, software, etc. required to control main and auxiliary switching devices in the ARCP inverter leg(s) based on a PWM signal or PWM signals. Given a PWM signal, a standard hard-switching inverter does not need too much additional logic to form a complete inverter drive system. At a minimum, the direct PWM signal is sent to one switch while the complement of the PWM input signal is sent to the other switch in that phase. The ARCP on the other hand, requires more than the PWM modulation and control: it requires an additional more complex control, particularly due to the auxiliary circuit and the auxiliary switch(es). In the exemplary embodiment illustrated in FIG. 1, the ARCP control 8 is adapted to provide control signals, such as G.sub.1, G.sub.2, G.sub.a1 and G.sub.a2 to the ARCP power section 10 or inverter leg based on a respective PWM signal received from a PWM modulator. The PWM modulator may be e.g., a part of the higher-level control 86 in FIG. 1, and the PWM commands may be sent via a communication link to the inverter INV. The ARCP control 8 may have to provide for instance the following functions for the ARCP power section 10 or inverter leg: Activation of the correct auxiliary switch before commutating the main switches, controlling the boost time, ensuring that the main switches are switched at essentially zero-voltage, ensuring that the auxiliary switches are switched at essentially zero-current, initially starting the switching sequence upon power up, etc. Depending on a selected ARCP control strategy, various sensing feedbacks FB may be required to implement the control algorithms, such as feedback from main switch zero-voltage sensors, auxiliary switch zero-current sensors, an auxiliary current sensor, an output (load) current sensor, a dc-link voltage sensor, a dc-link capacitor sensor(s), a neutral point voltage sensor, etc. In embodiments, a boost time control using a saturation sensing may be included in the switching control 8. In embodiments, a boost time control using a saturation sensing may be implemented by means of Field Programmable Gate Arrays (FPGAs).

[0042] As used herein, the mode of commutating the output current I.sub.o from a diode to a switch (e.g., the current I.sub.o from the diode D.sub.2 to the switch S.sub.1) in ARCP is called mode A and the mode of commutating the output current I.sub.o from a switch to a diode (e.g., the current I.sub.o from the switch S.sub.1 to the diode D.sub.2) is called mode B, when the auxiliary circuit is involved in commutation and a boost current is provided. The mode of commutating high output current I.sub.o from a switch to diode, when the output current I.sub.o itself is sufficient to drive the output voltage from one dc-link rail to another and the auxiliary circuit is not involved, is called mode O herein.

[0043] Mode A commutation: If the output current I.sub.o is positive (Io>0) and the output voltage U.sub.o swings from the potential N (the dc-link 24) to the potential P (the dc-link 22), the lower diode D.sub.2 commutate its current I.sub.d2 to the upper switch S.sub.1. If the output current I.sub.o is negative (Io<0) and the output voltage U.sub.o swings from the potential P (the dc-link 22) to the potential N (the dc-link 24), the upper diode D.sub.1 commutates its current I.sub.d1 to the lower switch S.sub.2.

[0044] Mode B commutation: If the output current I.sub.o is positive (Io>0) and the output voltage U.sub.o swings from the potential P (the dc-link 22) to the potential N (the dc-link 24), the upper switch S.sub.1 commutates its current to the lower diode D.sub.2. If the output current I.sub.o is negative (I.sub.o<0) and the output voltage U.sub.o swings from the potential N (the dc-link 24) to the potential P (the dc-link 22), the lower switch S.sub.2 commutates its current to the upper diodes D.sub.1.

[0045] In the following, examples of typical ARCP commutation in modes A and B are briefly described for a single phase of the ARCP inverter INV.

[0046] As an example of the mode A, a commutation of the positive output current I.sub.o (Io>0) from the lower diode D.sub.2 to the upper main switch S.sub.1 and the output voltage U.sub.o from N to P will described with reference to FIGS. 2A-2F. [0047] The diode D.sub.2 is conducting the output current I.sub.o (=I.sub.d2), the diode D.sub.2 supplying the output current I.sub.o (FIG. 2A) and switches S.sub.1, Sat and Sa.sub.2 not conducting (turned off); during the commutation S.sub.2 turns off and S.sub.1 turns on. [0048] The command for commutation arrives at time instant t.sub.Ao. The auxiliary switch Sa.sub.1 is turned on (at zero current) after a time interval t.sub.wA, which marks the start of the boosting interval t.sub.bA. The neutral point voltage U.sub.NP is applied across the resonant inductor L.sub.1, which causes the auxiliary current I.sub.a through the resonant inductor L.sub.1 to ramp up linearly (FIG. 2C), and the current I.sub.d2 in diode D.sub.2 decreases accordingly as I.sub.d2=I.sub.oI.sub.a (FIG. 2A). In order to turn the diode D.sub.2 off, the auxiliary current I.sub.a must increase to the level of the output current I.sub.o and even beyond (by a boosting current I.sub.bA), so that finally I.sub.a=I.sub.o+I.sub.bA. The boosting current portion I.sub.bA of the total inductor current I.sub.a is diverted to the switch S.sub.2 parallel to the diode D.sub.2 (FIG. 2B) while the load 6 takes its own, i.e., the output current I.sub.o. [0049] The switch S.sub.2 is turned off after a time interval t.sub.bA (FIG. 2B), which marks the end of the boosting interval t.sub.ba1, and the commutation swing of the output voltage U.sub.c2 from N (zero) to P (the full U.sub.dc) starts. The boosting current I.sub.bA must be large enough to force the output potential swing from N to P, charging the capacitor C.sub.2 and discharging the capacitor C.sub.1. If there is a slight unbalance of the dc link voltage halves so that U.sub.2<U.sub.1, more boosting current is needed, and if U.sub.2>U.sub.1, less boosting current suffices. [0050] The interval for the swing of U.sub.C2 from zero to U.sub.dc has duration t.sub.sA.

[00001]$\begin{array}{cc}{t}_{\mathrm{sA}}=\sqrt{L_{1}C}\left[{\cos }^{-1}\left(\frac{U_{c2}-U_{\mathrm{dc}}}{\sqrt{L_1/C}{I}_{\mathrm{pA}}}\right)-\right],& \left(1\right)\end{array}$

[0051] where

[0052] I.sub.pA is the peak value of the resonant part of the inductor current

[00002]$\begin{array}{cc}{I}_{\mathrm{pA}}=\sqrt{\frac{{\mathrm{CU}}_{c2}^2}{L_1}+I_{\mathrm{bA}}^2},& \left(2\right)\end{array}$

[0053] is a phase angle

[00003]$\begin{array}{cc}={\sin }^{-1}\left(I_{\mathrm{bA}}/I_{\mathrm{pA}}\right),& \left(3\right)\end{array}$

[0054] and C=C.sub.1+C.sub.2 in the exemplary topology B shown in FIG. 2. The voltage change rate average is du/dt=U.sub.dc/t.sub.sA.

[0055] When U.sub.c2 reaches U.sub.dc and U.sub.c1 reaches zero after a time interval t.sub.sA (FIG. 3D), the portion of the auxiliary current I.sub.a exceeding the output current I.sub.o turns on the diode D.sub.1 and is called I.sub.tA (FIGS. 4C and 4D). The switch S.sub.1 may be turned on as soon as U.sub.c2 has reached U.sub.dc. The boosting time t.sub.bA may preferably be set to a value that minimizes the current I.sub.tA close to zero. This way the losses and the reverse recovery current of D.sub.1 will be minimized, as well as the duration of the commutation. This strategy narrows the window t.sub.tAx. Thus, the precise timing of S.sub.1 turn-on is critical. [0056] Because the diode D.sub.1 and the switch S.sub.1 clamp the output voltage to the positive dc potential P, the inductor current I.sub.a decays linearly to zero during a time interval is t.sub.tA (FIG. 2C). [0057] The current I.sub.d1 decays first from I.sub.tA to zero in time t.sub.tAx, whereafter the switch current I.sub.s1 increases linearly from zero to the load current level I.sub.o (FIG. 2F) while I.sub.a continues to decrease from I.sub.o towards zero (FIG. 2C), after which the auxiliary diode Da2 turns off and the commutation sequence is finished. [0058] The total duration of the commutation from the turn-on of the auxiliary switch Sa.sub.2 to completion in mode A is t.sub.A=t.sub.bA+t.sub.sA+t.sub.tA. There is a current in the auxiliary branch during this time interval.

[0059] As an example of the mode B, a commutation of the positive output current I.sub.o (Io>0) from the upper main switch S.sub.1 to the lower diode D.sub.2 and a swing of the output voltage U.sub.o from N to P will described with reference to FIGS. 5A-5D. [0060] The switch S.sub.1 is conducting the output current I.sub.o (I.sub.o=I.sub.s1) (FIG. 3A) and switches S.sub.2, S.sub.a1 and Sa.sub.2 not conducting (turned off); during the commutation the upper switch S.sub.1 turns off and the lower diode D.sub.2 turns on. [0061] The command for commutation arrives at time instant t.sub.B0. After a waiting time t.sub.wB, the auxiliary switch S.sub.a2 is turned on, and boosting current I.sub.bB (in negative direction in the inductor L.sub.1, positive direction in S.sub.1) is linearly built up for a time t.sub.bB (FIG. 3B). [0062] The boosting current adds on top of the load current in the switch S.sub.1, which turns off a total current of I.sub.s1=I.sub.o+I.sub.bB at the end of t.sub.bB (FIG. 3A). The swing of U.sub.c1 from zero to U.sub.dc starts (FIG. 3C). The output potential swing from P to N is a combination of the linear portion caused by I.sub.o and a resonant portion caused by I.sub.bB. The duration of the swing is t.sub.sB

[00004]$\begin{array}{cc}{t}_{\mathrm{sB}}=\sqrt{L_{1}C}\left[{\cos }^{-1}\left(\frac{U_{c1}-U_{\mathrm{dc}}}{\sqrt{L_1/C}{I}_{\mathrm{pB}}}\right)-\frac{}{2}-\right],& \left(4\right)\end{array}$

[0063] where

[0064] I.sub.pB is the peak value of the resonant part of the inductor current,

[00005]$\begin{array}{cc}{I}_{\mathrm{pB}}=\sqrt{\frac{{\mathrm{CU}}_{c1}^2}{L_1}+{\left(I_o-I_{\mathrm{bB}}\right)}^2},& \left(5\right)\end{array}$

[0065] is a phase angle,

[00006]$\begin{array}{cc}={\tan }^{-1}\left(\frac{\sqrt{C/L_1}{U}_{c1}}{-I_o+I_{\mathrm{bB}}}\right),& \left(6\right)\end{array}$

[0066] and C=C.sub.1+C.sub.2. The voltage change rate average is du/dt=U.sub.dc/t.sub.sB. [0067] The remaining current I.sub.a in the inductance at the end of the swing adds initially on top of the output current I.sub.o in the diode D.sub.2 so that I.sub.d2=I.sub.o+I.sub.tB. The diode current decays linearly to the final value I.sub.o, as the inductor current reaches zero again after time t.sub.tB (FIGS. 5B and 5D). The total duration of the commutation in mode B from the triggering of Sa to completion is t.sub.B=t.sub.bB+t.sub.sB+t.sub.tB.

[0068] The descriptions above for modes A and B assumed a positive direction of I.sub.o. The operation for a negative I.sub.o (I.sub.o<0) is identical, just the roles of S.sub.1 and S.sub.2, D.sub.1 and D.sub.2, and U.sub.c1 and U.sub.c2 are swapped from mode A to mode B, and vice versa.

[0069] The resonant branch of the ARCPI topology is prone to an excess voltage oscillation and potential overvoltage across the auxiliary switches S.sub.a1 and S.sub.a2, which is mainly due to reverse recovery current of auxiliary diodes D.sub.a1 and D.sub.a2 and the LC resonance circuit. The resonant inductor L.sub.1 may typically be a conventional inductor with or without a magnetic core, and one solution for the oscillation and overvoltage problems has been to use a saturable-core inductor L.sub.sat in series with the conventional resonant inductor L.sub.1 in the auxiliary circuit, as illustrated in FIG. 4. Alternatively, as known for person skilled in the art, there can be also only one inductor in the resonant path, which has the desired saturable-core and inductance characteristics through the operational current range. It shall be appreciated that the resonant inductor, the saturable-core inductor and auxiliary switch may be located in any order in an ARCP circuit without having effect on the invention.

[0070] The saturable inductor L.sub.sat is designed to provide high inductance for very low levels of current, but almost zero inductance above the saturation current. An example of a behavior of the auxiliary current I.sub.a in theory and in practice in an ARCP commutation with I.sub.a>0 (la flows in direction from the neutral point NP) is presented in FIG. 5. FIG. 5 shows that, in theory, the auxiliary current I.sub.a increases linearly. However, in practice, the actual auxiliary current I.sub.a starts to increase slowly and gradually, because saturable inductor L.sub.sat slows down the current rise until a full saturation current is achieved at the saturation instant t.sub.sat. If the boost time to is calculated theoretically assuming a linearly increasing auxiliary current I.sub.a, the actual total auxiliary current I.sub.a (and thereby the boost current I.sub.b) achieved during the calculated boost time to is only a fraction of the optimal current value and the zero-voltage switching condition is not achieved. A challenge with the saturable core inductor L.sub.sat is that the inductance is non-linear and varies depending on, for example, a temperature and a frequency. Therefore, it is difficult to calculate a correct boost time and control the boost current when a saturable core inductor is used.

[0071] An aspect of invention is a power inverter system having a saturation instant detector configured to detect a saturation instant of a saturable-core inductor, i.e., the instant when the auxiliary current exceeds a saturation current of the saturable-core inductor after turn-on of an auxiliary switch. An ARCP controller is configured to continue providing the auxiliary current for a predetermined boost period after the detected saturation instant of the saturable-core inductor.

[0072] The predetermined boost period may be a boost time to determined or calculated based on the known inductance of the resonant inductor L.sub.1 in a normal manner. Thus, the boost time after saturation instant can be determined precisely using the known inductance of the resonant inductor L.sub.1. Basically, the calculated boost time to is applied from the detected saturation instant instead of the turn-on instant of the auxiliary switch, and thereby there is a sufficient time for the actual auxiliary current I.sub.a (and thereby the boost current I.sub.b) to reach a required or optimal value, as illustrated in FIG. 6. This eliminates the varying characteristics of the saturable inductor in boost time calculation. Consequently, it is possible to control an ARCP inverter optimally to achieve a zero-voltage switching and an optimal efficiency. The saturated inductance of the saturable-core inductor L.sub.sat can be assumed to be approximately zero, but any known non-zero saturated inductance of the saturable-core inductor L.sub.sat may be taken into account in the determination or calculation of the boost time, if desired.

[0073] In embodiments, the ARCP control may calculate a boost time to using, for example, the equation (7) for mode A commutations and the equation (8) for mode B commutations

[00007]$\begin{array}{cc}{t}_{\mathrm{bA}}=\left(I_o+I_b\right)2L_1/U_{\mathrm{dc}}& \left(7\right)\end{array}$$\begin{array}{cc}{t}_{\mathrm{bB}}=-2L_1{I}_b/U_{\mathrm{dc}}& \left(8\right)\end{array}$

[0074] wherein L.sub.1 is the inductance of the resonant inductor of the auxiliary circuit.

[0075] In embodiments, the saturable-core inductor comprises a primary winding and a secondary winding. The auxiliary current is flowing through the primary winding and secondary winding is used for saturation sensing purposes. The saturation instant t.sub.sat of the saturable inductor L.sub.sat can be detected from the voltage induced in the secondary winding. In principle, when the auxiliary current flowing in the primary winding is low and the saturable-core inductor L.sub.sat is not saturated, the voltage in the secondary winding is proportional to the voltage of the primary winding. When the auxiliary current increases beyond the saturation current, the voltage induced in the secondary winding drops to near to zero.

[0076] As an example, a saturable core inductor may be implemented by routing busbar or wire (forming a primary winding) through one or more saturable transformer cores of a ring or tube shape. A secondary winding may be implemented by routing another parallel wire through the same saturable core, for example.

[0077] FIG. 7 shows a schematic diagram illustrating an exemplary detector or sensing circuitry according to an embodiment of the invention. An auxiliary current I.sub.a flows through resonant inductor L.sub.1 and a saturable-core inductor L.sub.sat (a primary winding W.sub.1) connected in series with the auxiliary switch S.sub.aux between a neutral point NP and the middle point of the inverter leg (output). The auxiliary current I.sub.a induces a secondary voltage V.sub.sec1 across the secondary winding W.sub.2 of the saturable-core inductor. The secondary voltage V.sub.sec1 is first rectified by a full-bridge rectifier including diodes D3, D4, D5 and D6, and the rectified secondary voltage is then fed to a voltage divider including resistors R1 and R2. The rectification enables that the detector or sensing circuitry operates similarly with both positive and negative auxiliary currents (i.e., currents flowing from and to the NP, respectively). The voltage divider scales the rectified secondary voltage V.sub.sec2 to an appropriate level for a comparator including an operational amplifier A1 and a feedback resistor R5. In this example, the voltage V.sub.sec2 is connected to the negative input terminal of the comparator. Clamping diodes D.sub.1 and D.sub.2 may be connected from the input of the comparator to supply voltage Vcc and ground GND, respectively, to provide overvoltage and undervoltage protections. A reference voltage to the comparator is generated by a voltage divider including resistors R3 and R4. The feedback resistor R5 is used to generate small hysteresis to the circuitry. FIG. 8 presents simplified waveforms of the auxiliary current I.sub.a current and the output voltage V.sub.out of the sensing circuitry. In practice, the output voltage V.sub.out of the comparator is normally in the high state, when there is no auxiliary current I.sub.a. The output voltage V.sub.out goes to the low state, when the auxiliary current I.sub.a starts to flow and the saturable-core inductor L.sub.sat is operating in a non-saturable region. When the auxiliary current I.sub.a increases and exceeds saturation threshold, the saturable-core inductor L.sub.sat is saturated and the output voltage V.sub.out of the comparator goes back to the high state. There is a clear rising edge in the output voltage V.sub.out which indicates the saturation instant t.sub.sat.

[0078] In embodiments, the saturation instant detector is connected to the dc-link neutral point NP and configured to detect the saturation instant based on a voltage of the dc-link neutral point NP. The dc-link capacitors, such as C.sub.d1 and C.sub.d2, have typically parasitic inductance and resistance, which cause a voltage drop during fast current transient. In principle, a positive auxiliary current I.sub.a causes the neutral point voltage U.sub.NP to drop, and a negative auxiliary current I.sub.a causes the neutral point voltage U.sub.NP to rise. A sudden drop or rise of the neutral point voltage due to the positive or negative auxiliary current exceeding a saturation threshold can be sensed and used for detecting a saturation instant.

[0079] FIG. 9 shows a schematic diagram illustrating an exemplary the detector or sensing circuitry according to an embodiment of the invention. An auxiliary current I.sub.a flows through resonant inductor L.sub.1 and a saturable-core inductor L.sub.sat connected in series with the auxiliary switch S.sub.aux between a neutral point NP and the middle point of the inverter leg (output). The detecting or sensing circuitry uses separate comparator circuitry for positive and negative voltage peaks of the neutral point voltage U.sub.NP. The upper comparator circuitry senses positive auxiliary current from the neutral point NP through resonant inductor L.sub.1 and a saturable-core inductor L.sub.sat to the auxiliary switch, which causes the neutral point voltage U.sub.NP to slightly drop and the output voltage to swing towards U.sub.dc+. A voltage divider comprising resistors R1 and R3 between the U.sub.dc+ and the neutral point NP generates a reference voltage to a positive input of the upper comparator comprising an operational amplifier A1 and a feedback resistor R9. The resistor R9 generates a small hysteresis for the comparator. An input voltage to a negative input of the comparator A1 is generated by a voltage divider comprising resistors R2 and R4 between the U.sub.dc+ and the neutral point NP. The input voltage is filtered by a capacitor C3 connected between the negative input and the neutral point NP. The capacitor C3 generates a small delay for the negative input. When the voltage between the neutral point voltage U.sub.NP and U.sub.dc-changes fast, there will be a voltage difference between the positive and negative inputs of the comparator A1, which triggers the comparator output V.sub.OH to change state accordingly. The lower comparator for detecting a negative auxiliary current pulse operates similarly and generates V.sub.OL output. More specifically, the lower comparator circuitry senses a negative auxiliary current to the neutral point NP through resonant inductor L.sub.1 and a saturable-core inductor L.sub.sat from the auxiliary switch, which causes the neutral point voltage U.sub.NP to slightly rise and the output voltage to swing towards U.sub.dc. A voltage divider comprising resistors R5 and R7 between the U.sub.dc and the neutral point NP generates a reference voltage to a positive input of the lower comparator comprising an operational amplifier A.sub.2 and a feedback resistor R10. The resistor R10 generates a small hysteresis for the comparator. A reference voltage to the comparator is generated by a voltage divider including resistors R6 and R8 between the U.sub.dc and the neutral point NP. An input voltage to a negative input of the comparator A.sub.2 is generated by a voltage divider comprising resistors R6 and R8 between the U.sub.dc and the neutral point NP. The input voltage is filtered by a capacitor C4 connected between the negative input and the neutral point NP. The capacitor C4 generates a small delay for the negative input. When the voltage between the neutral point voltage U.sub.NP and U.sub.dc changes fast, there will be a voltage difference between the positive and negative inputs of the comparator A.sub.2, which triggers the comparator output V.sub.OL to change state accordingly.

[0080] FIG. 10 presents simplified waveforms of an auxiliary current Ia, a sensed neutral point voltage U.sub.NP, and output voltages V.sub.OL and V.sub.OH of the sensing circuitry. In principle, a positive auxiliary current I.sub.a causes the neutral point voltage U.sub.NP to drop, which sets V.sub.OH output from low to high. A negative auxiliary current I.sub.a causes the neutral point voltage U.sub.NP to rise, which sets V.sub.OL output from high to low. The leading edge of the voltage pulse V.sub.OH or V.sub.OL marks a saturation instant t.sub.sat.

[0081] Other exemplary embodiments for sensing or detecting a saturation instant t.sub.sat include an auxiliary current sensing using, for example, a Hall sensor or a Rogowski coil and detecting a rapid increase of current by a very fast AD converter or comparator. A still further example to sense a auxiliary current by a wire or a PCB trace that is located near the high current path (busbar) and sense the voltage induced due to a rapid current change by a comparator.

[0082] FIG. 11 is a simplified flow diagram illustrating an exemplary boost time control by detecting a saturation instant t.sub.sat of a saturable-core inductor L.sub.sat and continuing providing the auxiliary current (and thereby the boost current) for a predetermined boost period after the detected saturation instant. In this example, it is assumed that the detection input to the boost time control is a detection signal V.sub.out as shown in FIG. 8. First, boosting time to is calculated by a known resonant inductance using equations 7 and 8, for example (step 110). Then, boosting period is started by turning on the auxiliary switch S.sub.aux as in a basic ARCP (step 112). Because the auxiliary current starts to flow through the saturable inductor L.sub.sat, the detector output V.sub.out changes from a high state to a low state as shown in FIG. 8. The boost time control checks the state of the detector output V.sub.out and waits in a checking loop (step 114) until the saturation instant t.sub.sat is sensed by the detector and the detector output V.sub.out goes back to the high state. In response to the detector output V.sub.out going back to the high state, a boost timer counting the boosting period to is initiated to zero (step 116), i.e., the boosting period to is restarted from the saturation instant t.sub.sat. The boosting period is continued by the timer (in a loop of steps 118 and 120) until the predetermined boosting time to has elapsed. Finally, the predetermined boosting time to has elapsed, the auxiliary switch S.sub.aux is turned off to end the boost period (step 122). It should be noted that person skilled in the art may use the detected saturation time information in other types of calculation or determination means to correct the boost period, than previous example illustrates.

[0083] The ARCP control and boost time control techniques described herein may be implemented by various means. For example, these techniques may be implemented in hardware (one or more devices), firmware (one or more devices), software (one or more modules), or combinations thereof. For a firmware or software, implementation can be through modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in any suitable, processor/computer-readable data storage medium(s) or memory unit(s) and executed by one or more processors/computers. The data storage medium or the memory unit may be implemented within the processor/computer or external to the processor/computer, in which case it can be communicatively coupled to the processor/computer via various means as is known in the art. Additionally, components of systems described herein may be rearranged and/or complimented by additional components in order to facilitate achieving the various aspects, goals, advantages, etc., described with regard thereto, and are not limited to the precise configurations set forth in a given figure, as will be appreciated by one skilled in the art.

[0084] It will be obvious to a person skilled in the art that, as the technology advances, the inventive concept can be implemented in various ways. The invention and its embodiments are not limited to the examples described above but may vary within the scope of the claims.