MULTI-STAGE TRANSIMPEDANCE AMPLIFIER WITH RESISTOR-CAPACITOR (RC) COMPENSATION

Abstract

A multi-stage transimpedance amplifier comprises a first gain stage cascaded with a second gain stage, the second gain stage's output connected to the first gain stage's inverting input and to the second gain stage's inverting input, a compensation network electrically connected between the first gain stage's output and the second gain stage's output, the first gain stage, the second gain stage, and the compensation network together implementing a transfer function having complex conjugate poles and a real-valued zero, the compensation network comprising a resistor electrically connected in series with a capacitor, the resistance of the resistor and the capacitance of the capacitor determining the positioning of the complex conjugate poles, and a third gain stage cascaded with the second gain stage for introducing an additional pole in the transfer function, the third gain stage's output connected to the second gain stage's non-inverting input.

Claims

1. A multi-stage transimpedance amplifier comprising: a first gain stage; a second gain stage cascaded with the first gain stage, each of the first gain stage and the second gain stage having an inverting input, a non-inverting input, and an output, the output of the second gain stage being connected to the inverting input of the first gain stage and to the inverting input of the second gain stage; a compensation network electrically connected between the output of the first gain stage and the output of the second gain stage, the first gain stage, the second gain stage, and the compensation network together implementing a transfer function having complex conjugate poles and a real-valued zero, the compensation network comprising a resistor electrically connected in series with a capacitor, the resistor having a resistance and the capacitor having a capacitance, wherein respective values of the resistance and the capacitance determine a positioning of the complex conjugate poles; and a third gain stage cascaded with the second gain stage for introducing an additional pole in the transfer function, the third gain stage having an output connected to the non-inverting input of the second gain stage.

2. The multi-stage transimpedance amplifier of claim 1, wherein the first gain stage, the second gain stage, the third gain stage and the compensation network are arranged in a shunt-feedback configuration.

3. The multi-stage transimpedance amplifier of claim 1, wherein the first gain stage, the second gain stage, the third gain stage and the compensation network are arranged in a feed-forward common-base/common-gate configuration.

4. The multi-stage transimpedance amplifier of claim 1, wherein the first gain stage, the second gain stage, the third gain stage and the compensation network are arranged in a common-base/common-gate shunt-feedback configuration.

5. The multi-stage transimpedance amplifier of claim 1, wherein the second gain stage is configured to receive an input signal and the first gain stage is configured to convert the input signal into an amplified output signal.

6. The multi-stage transimpedance amplifier of claim 1, wherein the third gain stage has an output resistance and a shunt capacitance, further wherein respective values of the output resistance and the shunt capacitance determine a positioning of the additional pole.

7. The multi-stage transimpedance amplifier of claim 1, wherein the first gain stage, the second gain stage, the third gain stage, and the compensation network are arranged in a fully differential configuration.

8. The multi-stage transimpedance amplifier of claim 7, wherein the fully differential configuration of the first gain stage and the third gain stage is implemented using a resistive-loaded differential pair circuit.

9. The multi-stage transimpedance amplifier of claim 1, wherein the first gain stage, the second gain stage, the third gain stage, and the compensation network are arranged in a single-ended configuration.

10. The multi-stage transimpedance amplifier of claim 9, wherein the single-ended configuration of the second gain stage is a unity feedback configuration implemented using an emitter follower circuit.

11. The multi-stage transimpedance amplifier of claim 1, further comprising a fourth gain stage cascaded with the first gain stage, the fourth gain stage comprising an inverting input, a non-inverting input, and an output, the output of the first gain stage connected to the non-inverting input of the fourth gain stage and the output of the fourth gain stage connected to inverting input of the fourth gain stage.

12. The multi-stage transimpedance amplifier of claim 11, further comprising an additional compensation network electrically connected between the output of the third gain stage and the output of the first gain stage.

13. The multi-stage transimpedance amplifier of claim 1, wherein the first gain stage, the second gain stage, and the compensation network together implement the transfer function having the poles positioned in a real left-half plane.

14. A method for providing a multi-stage transimpedance amplifier, the method comprising: providing a first gain stage and a second gain stage, each of the first gain stage and the second gain stage having an inverting input, a non-inverting input, and an output; providing a compensation network comprising a resistor electrically connected in series with a capacitor; cascading the first gain stage with the second gain stage, the output of the second gain stage being connected to the inverting input of the first gain stage and to the inverting input of the second gain stage, the resistor having a resistance and the capacitor having a capacitance; electrically connecting the compensation network between the output of the first gain stage and the output of the second gain stage, the first gain stage, the second gain stage, and the compensation network together implementing a transfer function having complex conjugate poles and a real-valued zero, wherein respective values of the resistance and the capacitance determine a positioning of the complex conjugate poles; and cascading a third gain stage with the second gain stage for introducing an additional pole in the transfer function, the third gain stage having an output connected to the non-inverting input of the second gain stage.

15. The method of claim 14, wherein the first gain stage, the second gain stage, the third gain stage and the compensation network are arranged in one of a shunt-feedback configuration, a feed-forward common-base/common-gate configuration, and a common-base/common-gate shunt-feedback configuration.

16. The method of claim 14, further comprising adjusting respective values of an output resistance and a shunt capacitance of the third gain stage for tuning a positioning of the additional pole.

17. The method of claim 14, wherein the first gain stage, the second gain stage, the third gain stage, and the compensation network are arranged in one of a fully differential configuration and a single-ended configuration.

18. The method of claim 14, further comprising providing a fourth gain stage comprising an inverting input, a non-inverting input, and an output, and cascading the fourth gain stage with the first gain stage, the output of the first gain stage connected to the non-inverting input of the fourth gain stage and the output of the fourth gain stage connected to inverting input of the fourth gain stage.

19. The method of claim 18, further comprising electrically connecting an additional compensation network between the output of the third gain stage and the output of the first gain stage.

20. The method of claim 14, wherein the first gain stage, the second gain stage, and the compensation network together implement the transfer function having the poles positioned in a real left-half plane.

Description

DESCRIPTION OF THE FIGURES

[0026] In the figures,

[0027] FIG. 1 is a circuit diagram of an example multi-stage transimpedance amplifier, in accordance with one embodiment;

[0028] FIG. 2A is a circuit diagram illustrating a single-ended realization of the multi-stage transimpedance amplifier of FIG. 1 with one additional gain stage, in accordance with one embodiment;

[0029] FIG. 2B is a circuit diagram illustrating a fully differential realization of the multi-stage transimpedance amplifier of FIG. 1 with an additional gain stage, in accordance with one embodiment;

[0030] FIG. 3A is a resistive-loaded differential pair circuit used to implement the fully differential realization of G.sub.m1 and G.sub.m3 of FIG. 2B, in accordance with one embodiment;

[0031] FIG. 3B is an emitter follower circuit used to implement the single-ended realization of G.sub.m2 of FIG. 2A, in accordance with one embodiment;

[0032] FIG. 4A is an example shunt-feedback transimpedance amplifier circuit using the circuits of FIG. 3A and FIG. 3B, in accordance with one embodiment;

[0033] FIG. 4B is a plot of the effect of the compensation network resistance R.sub.c1 on the positioning of complex conjugate poles, in accordance with one embodiment;

[0034] FIG. 4C is a plot of the effect of the compensation network resistance R.sub.c1 on the real-valued zero positioning, in accordance with one embodiment;

[0035] FIG. 4D is a plot of the effect of changes in the amplifier's magnitude response, subject to changes in the resistance R.sub.c1 alone, in accordance with one embodiment;

[0036] FIG. 4E is a plot of the effect of changes in the amplifier's magnitude response, subject to changes in the capacitance C.sub.c1 alone, in accordance with one embodiment;

[0037] FIG. 5A illustrates circuit details of an output voltage buffer with inductive peaking placed in cascade with a transimpedance stage, in accordance with one embodiment;

[0038] FIG. 5B is a plot of the stage-wise and overall magnitude frequency response for the closed-loop transimpedance amplifier of FIG. 5A in single-ended operation along with the response of a conventional transimpedance stage without RC compensation for same targeted overall gain, in accordance with one embodiment;

[0039] FIG. 6A is a circuit diagram illustrating a single-ended realization of the multi-stage transimpedance amplifier of FIG. 1 with two additional gain stages and additional RC compensation network, in accordance with one embodiment.

[0040] FIG. 6B is a circuit diagram of an example shunt-feedback transimpedance amplifier circuit incorporating the transistorized realization of the amplifier of FIG. 6A, in accordance with one embodiment;

[0041] FIG. 7A is a plot illustrating the effect of the compensation network resistance R.sub.c2 on the frequency response of the amplifier of FIG. 6A, in accordance with one embodiment;

[0042] FIG. 7B is a plot illustrating the effect of the compensation network resistance R.sub.c1 on the frequency response of the amplifier of FIG. 6A, in accordance with one embodiment;

[0043] FIG. 7C is a plot illustrating the effect of the compensation network resistance R.sub.c2 on the complex conjugate pole pair of the amplifier of FIG. 6A, in accordance with one embodiment;

[0044] FIG. 7D is a plot illustrating the effect of the compensation network resistance R.sub.c1 on the complex conjugate pole pair of the amplifier of FIG. 6A, in accordance with one embodiment; and

[0045] FIGS. 8A, 8B, 8C, 8D, and 8E illustrate results obtained upon experimental validation of the multi-stage transimpedance amplifier of FIG. 2B.

DETAILED DESCRIPTION

[0046] Described herein is a multi-stage amplifier with a resistor-capacitor (RC) compensation scheme that may be used as the open-loop amplifier for a closed-loop shunt-feedback-based transimpedance (TI) stage. It should be understood that, while reference is made herein to a multi-stage amplifier having a shunt-feedback topology, it should be understood that any other suitable topology including, but not limited to, a feed-forward common-base (CB)/common-gate (CG) amplifier and a CB/CG shunt-feedback amplifier, may apply.

[0047] As understood by one skilled in the art, different circuits have different transimpedance (TI) limits. For instance, a cascade of N amplifiers with identical poles has the following open-loop transfer function:

[00001]$\begin{array}{cc}A\left(s\right)=\frac{A_o^N}{{\left(1+S/{?}_p\right)}^N}& \left(1\right)\end{array}$

[0048] where A(s) is the open-loop transfer function, A.sub.0.sup.N is the direct-current (DC) gain, and ?.sub.p is the frequency of the pole in rad/s.

[0049] Circuit analysis reveals that for a Butterworth closed-loop response, a typical shunt-feedback transimpedance amplifier (TIA) system (not shown) has a transimpedance-N+1-power-bandwidth product of:

[00002]$\begin{array}{cc}{R}_{T,\mathrm{limit},\mathrm{Nstage}}?{\mathrm{BW}}_{\mathrm{CL}}^{N+1}=\frac{f_t^N}{2?C_{\mathrm{in}}}& \left(2\right)\end{array}$

[0050] where R.sub.T,limit,Nstage?BW.sub.CL.sup.N+1 is the transimpedance-N+1-power-bandwidth product, R.sub.T,limit,Nstage is the TI limit for the N-stage amplifier, and BW.sub.CL.sup.N+1 is the closed-loop bandwidth.

[0051] Such a TIA system also has a TI limit of:

[00003]$\begin{array}{cc}{R}_{T,\mathrm{limit},\mathrm{Nstage}}=\frac{f_t^N}{2?C_{\mathrm{in}}{\mathrm{BW}}_{\mathrm{CL}}^{N+1}}& \left(3\right)\end{array}$

[0052] where f.sub.t.sup.N is the gain-bandwidth product (expressed in Hz) and C.sub.in is the total input capacitance.

[0053] Under closed-loop bandwidth conditions set less than f.sub.t, the ratio of the transimpedance limit of an N-stage amplifier versus a single-stage amplifier is:

[00004]$\begin{array}{cc}\frac{R_{T,\mathrm{limit},\mathrm{Nstage}}}{R_{T,\mathrm{limit},1\mathrm{stage}}}={\left(\frac{f_t}{{\mathrm{BW}}_{\mathrm{CL}}}\right)}^{N-1}& \left(4\right)\end{array}$

[0054] where R.sub.T,limit,1stage is the TI limit for a single-stage amplifier.

[0055] From the above, one can see that an N-stage open-loop amplifier configuration will be capable of achieving a higher transimpedance limit than one that uses a single-stage amplifier configuration. This provides the motivation to use a multi-stage cascade to implement the TI stage.

[0056] In addition to the use of multi-stage cascade, if RC compensation is also used in the TI stage, then the transimpedance can be effectively decoupled from the bandwidth. This means that for an N-stage cascade, the TI limit can be enhanced compared to the conventional TI limit (i.e. as defined by E. S?ckinger in The transimpedance limit, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8, pp. 1848-1856, August 2010), as will be discussed further below.

[0057] TIA amplifiers are typically realized as a cascade of several (N) amplifier stages, with the TI stage receiving an input signal from a source (e.g., a photodiode), followed by an additional cascade of gain stages, denoted herein as Gain Amplifier (GA). The GA is used to achieve the overall gain specifications of the TIA amplifier, as well as to implement continuous time linear equalization (CTLE).

[0058] Although reference is made herein to a two-stage amplifier, it should be understood that high-order multi-stage designs, i.e., where N?2, may also apply. A two-stage amplifier having two coincident real-valued poles at ?.sub.p1 as in the conventional S?ckinger's transfer function of equation (1) but having an additional zero at s=?1/C.sub.inR.sub.F (where R.sub.F is the feedback resistance) and another real-valued pole at ?.sub.p2 will be considered. The pole at ?.sub.p2 is introduced to ensure a maximally flat Butterworth response in a closed-loop configuration. The zero at s=?1/C.sub.inR.sub.F is introduced to eliminate the presence of the term created by C.sub.in and R.sub.F in the characteristic equation of the closed-loop transfer function. Consequently, the transfer function of the open-loop amplifier can be expressed as follows:

[00005]$\begin{array}{cc}A\left(s\right)=A_o^2\frac{\left(1+{\mathrm{sC}}_{\mathrm{in}}{R}_F\right)}{{\left(1+S/{?}_{p1}\right)}^2\left(1+S/{?}_{p2}\right)}& \left(5\right)\end{array}$

[0059] The resulting closed-loop transfer function is then given as:

[00006]$\begin{array}{cc}\frac{V_o\left(s\right)}{I_{in}\left(s\right)}=\frac{-R_F{?}_{p2}{?}_{p1}^2{A}_o^2}{\left[s^3+s^2\left(2{?}_{p1}+{?}_{p2}\right)+s\left({?}_{p1}^2+2{?}_{p1}{?}_{p2}\right)+{?}_{p1}^2{?}_{p2}\left(A_o^2+1\right)\right]}& \left(6\right)\end{array}$

[0060] Replacing A.sub.o?.sub.p1=2?f.sub.t and using A.sub.o.sup.2+1?A.sub.o.sup.2, the 3-dB bandwidth of this closed-loop system can be identified as:

[00007]$\begin{array}{cc}{\mathrm{BW}}_{\mathrm{CL}}?{\left[\frac{f_t^2{?}_{p2}}{2?}\right]}^{1/3}& \left(7\right)\end{array}$

[0061] The equality is reached in (7) for a maximally flat Butterworth response. Therefore, the open-loop transfer function (5) results in a closed-loop transfer function whose bandwidth is independent of R.sub.F. This is not surprising given that R.sub.F no longer appears in the denominator term of (6).

[0062] Furthermore, if instead of two coincident real-valued poles in (5), two complex conjugate poles are used, the resulting bandwidth of the closed-loop system will be greater than that in (7) while still being independent of R.sub.F. Such an amplifier having two complex conjugate poles is defined as follows:

[00008]$\begin{array}{cc}A\left(s\right)=\frac{A_o^2\left(1+{\mathrm{sC}}_{in}{R}_F\right)}{\left(1+\frac{s}{{?}_{p1}\left(1+j?\right)}\right)\left(1+\frac{s}{{?}_{p1}\left(1-j?\right)}\right)\left(1+\frac{s}{{?}_{p2}}\right)}& \left(8\right)\end{array}$

[0063] Here the term ? accounts for the separation distance between the real and imaginary parts of the complex conjugate poles, i.e.:

[00009]$\begin{array}{cc}?\stackrel{?}{=}.Math.\frac{\mathrm{imag}\mathrm{part}\mathrm{of}\mathrm{pole}}{\mathrm{real}\mathrm{part}\mathrm{of}\mathrm{pole}}.Math.& \left(9\right)\end{array}$

[0064] This parameter will become the central focus for the design of high-speed TIA circuits and will be referred to as the complex pole spreading factor.

[0065] The resulting closed-loop transfer function for this circuit is given as follows:

[00010]$\begin{array}{cc}T\left(s\right)=\frac{V_o\left(s\right)}{I_{in}\left(s\right)}=\frac{A_o^2{R}_F}{\begin{array}{c}\{\frac{s^3}{{?}_{p1}^2{?}_{p2}\left(1+{?}^2\right)}+s^2\left[\frac{2}{{?}_{p1}{?}_{p2}\left(1+{?}^2\right)}+\frac{1}{{?}_{p1}^2\left(1+{?}^2\right)}\right]+\\ s\left[\frac{2{?}_{p1}}{{?}_{p1}^2\left(1+{?}^2\right)}+\frac{1}{{?}_{p2}}\right]+A_o^2+1\}\end{array}}& \left(10\right)\end{array}$

[0066] In closed-loop operation, the 3-dB bandwidth of this system is given as:

[00011]$\begin{array}{cc}{\mathrm{BW}}_{\mathrm{CL}}?{\left[\frac{f_t^2{?}_{p2}\left(1+{?}^2\right)}{2?}\right]}^{1/3}& \left(11\right)\end{array}$

[0067] Once again, the equality is reached in equation (11) for a maximally flat Butterworth response. As is evident, the bandwidth of the complex conjugate pole system remains independent of R.sub.F. Further, this bandwidth is greater than that of the repeated real-valued poles' transfer function by a factor of about

[00012]$\sqrt[3]{\frac{{?}_{p2},\mathrm{complex}\mathrm{poles}}{{?}_{p2},\mathrm{real}\mathrm{poles}}\left(1+{?}^2\right)}.$

[0068] Consequently, a greater closed-loop bandwidth is possible for any R.sub.F if the open-loop amplifier has complex conjugate poles and a zero located at s=?1/C.sub.inR.sub.F.

[0069] FIG. 1 shows an example circuit of a multi-stage amplifier 100 for realizing complex conjugate poles. The amplifier 100 comprises a cascade of two transconductance gain (or G.sub.m) stages, namely a first stage 102.sub.1 (labelled G.sub.m,1 in FIG. 1) and a second stage 102.sub.2 (labelled G.sub.m,2 in FIG. 1) which each have a non-inverting input 103.sub.NI, an inverting input 103.sub.I, and an output 103.sub.O.

[0070] The second stage 102.sub.2 is configured to receive an input voltage V.sub.in (e.g., from an input voltage source, not shown) at an input node 104 (which is connected to the non-inverting input 103.sub.NI) and the first stage 102.sub.1 is configured to provide (via its output 103.sub.O) an output voltage V.sub.o (e.g., to a load, not shown) at an output node 106 of the amplifier 100. The non-inverting input 103.sub.NI of the first stage 102.sub.1 is grounded while the inverting input 103.sub.I of the second stage 102.sub.2 is connected to its output 103.sub.O. The output 103.sub.O of the second stage 102.sub.2 is further connected to the inverting input 103.sub.I of the first stage 102.sub.1.

[0071] The first stage 102.sub.1 is assumed to have a finite output resistance R.sub.D1 (illustrated as resistor 108.sub.1 in FIG. 1) and a shunt capacitance C.sub.p1 (illustrated as capacitor 110.sub.1 in FIG. 1). Similarly, the second stage 102.sub.2 is assumed to have a finite output resistance R.sub.D2 (illustrated as resistor 108.sub.2 in FIG. 1) and a shunt capacitance C.sub.p2 (illustrated as capacitor 110.sub.2 in FIG. 1). The resistor 108.sub.2 and the capacitor 110.sub.2 (which models the parasitic capacitance) are connected in parallel, between an intermediate node 112 (connected to the output 103.sub.O of the second stage 102.sub.2) and ground, and the resistor 108.sub.1 and the capacitor 110.sub.1 (which models the parasitic capacitance) are connected in parallel, between the output node 106 (which is connected to the output 103.sub.O of the first stage 102.sub.1) and ground.

[0072] The amplifier 100 also includes a bridging RC network 114, which may be used to establish complex conjugate pole locations. In one embodiment, the first stage 102.sub.1 and the second stage 102.sub.2, together with the RC network 114, implement a transfer function having complex conjugate poles along with a real-valued zero. The zero may compensate the undesired pole created by photodiode capacitance along with the feedback resistance. It should be understood that the first stage 102.sub.1 and the second stage 102.sub.2, together with the RC network 114 may also implement a transfer function having real-valued poles positioned in the left-half plane (LHP), i.e. real-valued LHP poles, along with a real-valued zero, as noted above with reference to equation (5).

[0073] The RC network 114 is coupled between nodes 112 and 106 and comprises a resistor 116 having a resistance R.sub.c1 electrically connected in series with a capacitor 118 having a capacitance C.sub.c1.

[0074] The input-output transfer function for the circuit of the amplifier 100 can be derived as:

[00013]$\begin{array}{cc}\frac{V_o\left(s\right)}{V_{in}\left(s\right)}=-\frac{G_{m1}{R}_{D1}\frac{G_{m2}{R}_{D2}}{G_{m2}{R}_{D2}+1}\left(?s+1\right)}{{?}_3{s}^3+{?}_2{s}^2+{?}_{1}s+1}& \left(12\right)\end{array}$

[0075] where

[00014]$\begin{array}{cc}?=C_{c1}{R}_{c1}-\frac{C_{c1}}{G_{m1}}& \left(13\right)\end{array}$${?}_1=\frac{\begin{array}{c}(\left(\left(G_{m1}+G_{m2}\right)R_{D1}+G_{m2}{R}_{c1}+1\right)C_{c1}+C_{p1}{G}_{m2}{R}_{D1}+\\ C_{p2})R_{D2}+\left(R_{D1}+R_{c1}\right)C_{c1}+R_{D1}{C}_{p1}\end{array}}{G_{m2}{R}_{D2}+1}$${?}_2=\frac{\begin{array}{c}(\left(\left(C_{p1}{G}_{m2}{R}_{c1}+C_{p2}+C_{p1}\right)R_{D1}+C_{p2}{R}_{c1}\right)C_{c1}+\\ C_{p1}{C}_{p2}{R}_{D1})R_{D2}+C_{c1}{C}_{p1}{R}_{D1}{R}_{c1}\end{array}}{G_{m2}{R}_{D2}+1}$${?}_3=\frac{C_{c1}{C}_{p1}{C}_{p2}{R}_{D1}{R}_{D2}{R}_{c1}}{G_{m2}{R}_{D2}+1}$

[0076] One can equate the denominator term of (12) to the desired position of the complex conjugate poles as:

[00015]$\begin{array}{cc}{?}_3{s}^3+{?}_2{s}^2+{?}_{1}s+1=\left(1+\frac{s}{{?}_{p1}\left(1+j?\right)}\right)\left(1+\frac{s}{{?}_{p1}\left(1-j?\right)}\right)\left(1+\frac{s}{{?}_{p2}}\right)& \left(14\right)\end{array}$

for which the ?-terms can be identified as:

[00016]$\begin{array}{cc}{?}_3=\frac{1}{{?}_{p1}^2\left(1+{?}^2\right){?}_{p2}},& \left(15\right)\end{array}$${?}_2=\frac{2{?}_{p1}+{?}_{p2}}{{?}_{p1}^2\left(1+{?}^2\right){?}_{p2}}$${?}_1=\frac{{?}_{p1}\left(1+{?}^2\right)+2{?}_{p2}}{{?}_{p1}^2\left(1+{?}^2\right){?}_{p2}}$

[0077] As the amplifier of FIG. 1 is intended for closed-loop operation, its input-output transfer function would take on the general form displayed in (10). Moreover, as the goal is to achieve a 3rd-order Butterworth response, the denominator polynomial in (10) should appear as:

[00017]$\begin{array}{cc}{\left(\frac{s}{{?}_o}\right)}^3+2{\left(\frac{s}{{?}_o}\right)}^2+2\left(\frac{s}{{?}_o}\right)+1& \left(16\right)\end{array}$

[0078] Resulting in the following two constraint equations on the pole positions:

[00018]$\begin{array}{cc}2{?}_{p1}\left(A_o+1\right){?}_{p2}^2-2{?}_{p2}{?}_o^2\left(A_o+1\right)=-{?}_o^3& \left(17\right)\end{array}$$\begin{array}{cc}2{?}_{p1}+{?}_{p2}=2{?}_o& \left(18\right)\end{array}$

[0079] with ?.sub.o=BW.sub.CL/2?.

[0080] For a particular open-loop gain (A.sub.o) and a desired closed-loop bandwidth (BW.sub.CL), ?.sub.p1 and ?.sub.p2 can be found as the simultaneous solution to equations (17) and (18). Further, the required complex pole spreading factor (?) is found by solving the following equation using the newly acquired information:

[00019]$\begin{array}{cc}?=\sqrt{\frac{{?}_o^3}{\left(A_o+1\right){?}_{p1}^2{?}_{p2}}-1}& \left(19\right)\end{array}$

[0081] with ?.sub.p1, ?.sub.p2 and ? now determined, one can equate the ?-terms in (13) with those in (15), together with the constraint on the zero location, i.e., ?=C.sub.inR.sub.F, and solve for the circuit parameters of FIG. 1 from the resulting nonlinear equations.

[0082] Referring now to FIG. 2A and FIG. 2B, example circuits of a first multi-stage amplifier 200 and a second multi-stage amplifier 210 comprising an additional (i.e. third) gain stage 102.sub.3 (labelled G.sub.m,3 in FIG. 2A) at the front-end of the cascade structure 100 of FIG. 1 will now be described. In particular, the output 103.sub.O of the additional gain stage 102.sub.3 is electrically connected to the non-inverting input 103.sub.NI of the second gain stage 102.sub.2, and the input node 104 is coupled to the inverting input 103.sub.1 of the additional gain stage 102.sub.3, with the non-inverting input 103.sub.NI of the additional gain stage 102.sub.3 being grounded. As used herein, the term front-end refers to the side of the transimpedance amplifier circuit at which the source (not shown) of the input signal is connected. This is opposed to the term back-end, which refers to the side of the transimpedance amplifier circuit at which the amplified output signal (based on the input signal) is provided.

[0083] The additional gain stage 102.sub.3 is assumed to have a resistance R.sub.D3 (illustrated as resistor 108.sub.3 in FIG. 2A) and a parasitic capacitance C.sub.p3 (illustrated as capacitor 110.sub.3 in FIG. 2A). The resistor 108.sub.3 and the capacitor 110.sub.3 are connected in parallel, between an intermediate node 120 (connected to the non-inverting input 103.sub.NI of the second stage 102.sub.2) and ground. The additional gain stage 102.sub.3 serves to increase the open-loop low-frequency gain and to reduce the noise of the open-loop amplifier because the noise of any cascade architecture can be reduced by setting greater gain in the amplifier's front-end stage. If the additional gain stage 102.sub.2 is used as the front-end stage, the noise of the open-loop amplifier will be increased due to its unity gain feedback loop, which will directly increase the TIA input-referred noise. Moreover, the addition of gain stage 102.sub.3 introduces a pole at a high frequency set by the parasitic capacitance C.sub.p3 and the resistance R.sub.D3. Therefore, the additional gain stage 102.sub.3 will not affect the pole-zero distribution previously mentioned.

[0084] Two types of gain stages (G.sub.m) may be used herein. One type of gain stage has a fully differential output and the other has a single-ended output together with unity-gain feedback. The amplifier 200 of FIG. 2A is an example of a single-ended realization (or configuration) while the amplifier 210 of FIG. 2B is an example of a fully differential realization (or configuration).

[0085] In the fully differential embodiment of FIG. 2B, the input signal (Vin) is provided at input nodes 104, 104, with the inverting input 103.sub.I of the additional gain stage 102.sub.3 being coupled to the input node 104 and the non-inverting input 103.sub.NI of the additional gain stage 102.sub.3 being coupled to the input node 104. The output signal (Vo) is provided at output nodes 106, 106 to which the first gain stage 102.sub.1 is coupled. Two second gain stages 102.sub.2 and 102.sub.2 are coupled to the additional gain stage 102.sub.3 and arranged in a mirror configuration. The second gain stages 102.sub.2, 102.sub.2 are each assumed to have a finite output resistance R.sub.D2 (respectively illustrated as resistors 108.sub.2 and 108.sub.2 in FIG. 2B) and a shunt capacitance C.sub.p2 (respectively illustrated as capacitors 110.sub.2 and 110.sub.2 in FIG. 2B). Each resistor 108.sub.2, 108.sub.2 is connected in parallel with a respective capacitor 110.sub.2, 110.sub.2, as described herein above with reference to FIG. 1.

[0086] In the fully differential embodiment of FIG. 2B, the amplifier 210 further comprises two bridging RC networks 114, 114 arranged in a mirror configuration. The first bridging RC network 114 is coupled between the intermediate node 112 (to which the inverting input 103.sub.I of the second gain stage 102.sub.2, the output 103.sub.O of the second gain stage 102.sub.2, and the inverting input 103.sub.I of the first gain stage 102.sub.1 are coupled) and the output node 106. The first bridging network 114 and comprises a resistor 116 having a resistance R.sub.c1 electrically connected in series with a capacitor 118 having a capacitance C.sub.c1. The second bridging RC network 114 is coupled between an intermediate node 112 (to which the inverting input 103.sub.I of the second gain stage 102.sub.2, the output 103.sub.O of the second gain stage 102.sub.2, and the non-inverting input 103.sub.NI of the first gain stage 102.sub.1 are coupled) and the output node 106. The second bridging network 114 comprises a resistor 116 having a resistance R.sub.c1 electrically connected in series with a capacitor 118 having a capacitance C.sub.c1.

[0087] In one embodiment, the fully differential transconductance stage (comprising the third gain stage 102.sub.3 and the first gain stage 102.sub.1) of FIG. 2B can be implemented using a resistive-loaded differential pair circuit 300 as depicted in FIG. 3A. Conversely, the single-ended transconductance stage (comprising the second gain stages 102.sub.2 and 102.sub.2) with unity feedback of FIG. 2A can be implemented using an emitter follower circuit 310 as shown in FIG. 3B. Substituting the circuits 300, 310 of FIG. 3A and FIG. 3B into the open-loop transimpedance amplifier circuit 210 of FIG. 2B and arranging the overall amplifier in a shunt-feedback arrangement results in the fully differential circuit 400 shown in FIG. 4A. In one embodiment, by adjusting the values of either R.sub.c1 or C.sub.c1 in the RC compensation network (reference 114, 114 in FIG. 2B), the circuit 400 can be used to tune the position of the closed-loop poles and zero of the transimpedance amplifier circuit.

[0088] To demonstrate this capability, a test case was setup with the values of the resistances (i.e., R.sub.1, R.sub.2, R.sub.e1, R.sub.e2) used in the transistor arrangement 400 of FIG. 4A being set to 1 k? (i.e., R.sub.1=R.sub.2=R.sub.e1=R.sub.e2=1 k?) for simulation in Spectre using GF BiCMOS 9HP process node. With Cc, fixed to 50 fF, the value of the compensation network's resistance R.sub.c1 was swept from 45? to 10 k? and the position of the poles and zero of the closed-loop TIA circuit 400 were computed by Spectre. The results are captured in the two s-plane pole and zero plots 410, 420 of FIGS. 4B and 4C. The position of two poles as a function of R.sub.c1 is shown in the plot 410 of FIG. 4B. As can be seen from plot 410, the pole plot consists of two poles that are real-valued for R.sub.c1?2.2 k? and become complex conjugate for R.sub.c1>2.2 k?. As R.sub.c1 increases, so does the complex pole spreading factor ?. In the case of the real-valued zero, one can see from the plot 420 of FIG. 4C that the real-valued zero moves downward in frequency with increasing value of R.sub.c1. The impact of a change in R.sub.c1 on the magnitude response of the closed-loop behavior of the TIA circuit can be seen in the plot 430 of FIG. 4D. From plot 430, one sees that the effect on the pole-zero changes gives rise to an increasing 3-dB bandwidth with increasing R.sub.c1. The effect of changes in C.sub.c1 when R.sub.c1 is held constant at 3 k? can also be noted, as shown in plot 440 of FIG. 4E for C.sub.c1 sweeping from 15 fF to 250 fF. From plot 440, one sees that a change in C.sub.c1 mainly affects the position of the real-valued zero. An increase in C.sub.c1 decreases the frequency of the zero while a change in C.sub.c1 has minimal effect on the positioning of poles. Therefore, tuning of loop specifications can give the desired pole-zero configuration in the open loop response.

[0089] To simulate the proposed multi-stage transimpedance amplifier, the circuit 400 of FIG. 4A was designed for a closed loop overall bandwidth of 34 GHz and transimpedance of 70 dB? in the presence of a photodiode having a parasitic capacitance of 65 fF. The resulting circuit parameters for this design are summarized in Table 1 below.

TABLE-US-00001 TABLE 1 Parameter Value Parameter Value Technology GF BiCMOS Q.sub.1-Q.sub.4 1 ? 0.1 ?m ? 9 HP (90 nm) 2 ?m (f.sub.t = 310 GHz) R.sub.F 4.5 k? Q.sub.buff 3 ? 0.1 ?m ? 2 ?m R.sub.c1 3 k? I.sub.1 1.8 mA C.sub.c1 50 fF I.sub.2 1.4 mA R.sub.1/R.sub.2 1 k? I.sub.3 2.7 mA R.sub.e1/R.sub.e2 1 k? I.sub.4 1.1 mA R.sub.buff 50 ? I.sub.buff 12 mA L.sub.Buff 550 pH (6 ?m ? 3 ?m)

[0090] Additionally, as shown in the circuit diagram 500 of FIG. 5A, a 500 output buffer stage 502 was used to follow the transimpedance stage 504 so that the TIA could be connected in a 50? balanced system. This buffer 502 may be implemented with a fully differential stage having a 50? collector resistance, as shown in the circuit diagram 500 of FIG. 5A. Series inductors 506 may be used in the collectors of the resistive-loaded differential-pair amplifier to compensate for bond pads, wire bonds, and other packaging losses.

[0091] Referring now to FIG. 5B, a plot 510 shows a curve 512 of the overall magnitude of the input-output frequency response of the proposed shunt-feedback TIA (in single-ended operation mode) along with stage-wise responses of the proposed transimpedance stage (curve 514) and of the output buffer (curve 516). Also included in plot 510 is the frequency response behavior of a conventional transimpedance stage implemented without the RC compensation scheme (curve 518). These results were obtained through a transistor level simulation of the circuit using the Cadence Spectre simulation platform. Models for the transistors and other components were provided in the design kit associated with the Global Foundries SiGe BiCMOS 9HP process. From FIG. 5B, it can be seen that, in some embodiments, the proposed transimpedance stage achieves a higher bandwidth (28 GHz) compared to the conventional design (8 GHz) for the same transimpedance gain (71 dB?). This bandwidth extension may be achieved without using any inductors because the effect of peaking inductors of the buffer only appears in the overall response shown by curve 512 in FIG. 5B.

[0092] Referring now to FIG. 6A, the circuits of FIG. 2A and FIG. 2B can be modified to include an additional RC compensation network 602 (comprising a resistor 604 having a resistance R.sub.c2 electrically connected in series with a capacitor 606 having a capacitance C.sub.c2), along with an additional buffer stage 102.sub.4 (labelled G.sub.m4 in FIG. 6A) to achieve improved control on the placement of poles and zeros. The additional RC compensation network 602 is connected between an output 103.sub.O of the third gain stage 102.sub.3 and an output 103.sub.O of the first gain stage 102.sub.1. In the illustrated embodiment, the inverting input 103.sub.1 of the fourth gain stage 102.sub.4 is connected to its output 103.sub.O, with the non-inverting input 103.sub.NI of the fourth gain stage 102.sub.4 being connected to the output 103.sub.O of the first gain stage 102.sub.1. 12 The resulting fully-differential shunt-feedback realization is shown in the circuit diagram 610 of FIG. 6B.

[0093] The overall transfer function A.sub.op(s) of the circuit of FIG. 6A can be computed using nodal analysis and can be represented as:

[00020]$\begin{array}{cc}{A}_{\mathrm{op}}\left(s\right)=\frac{{.Math.}_{n=0}^5{a}_n{s}^n}{{.Math.}_{m=0}^7{b}_m{s}^m}& \left(20\right)\end{array}$

[0094] where the coefficients a.sub.n and b.sub.m for n=1, 2, . . . , 5 and m=1, 2, . . . , 9 represent all technology parameters, design dependent parameters and the RC compensation components. The proposed system has seven (7) poles and five (5) zeros.

[0095] The effect of the resistance 604 (R.sub.c2) of the additional compensation network 602 on the amplifier's frequency response is shown in plot 700 of FIG. 7A, while the effect of the resistance 116 (R.sub.c1) of the compensation network 114 on the amplifier's frequency response is shown in plot 702 of FIG. 7B. Corresponding effects on the dominant complex conjugate pole pair are shown in plots 704 and 706 of FIG. 7C and FIG. 7D. From plots 700, 702, 704, and 706, it can be seen that, starting from a critically damped system, a designer can reduce R.sub.c2 to decrease the damping ratio and can change R.sub.c1 for further fine tuning to obtain targeted ?.

[0096] Referring now to FIGS. 8A, 8B, 8C, 8D, 8E, and 8F, results obtained upon experimental validation of the proposed circuit and design methodology will now be described. The proposed TIA was fabricated in the BiCMOS GF-9HP process.

[0097] FIG. 8A shows a plot 800 illustrating a comparison between the measured and transistor level simulated frequency response of the TIA circuit in fully differential mode operation. The plot 800 is obtained using a first test setup in which S-parameters of the TIA were measured using a microwave network analyser (e.g., the Keysight N5247B PNA-X microwave network analyzer, or any other suitable device). The transimpedance gain was then extracted from the measured S-parameters. In FIG. 8A, the measured transimpedance gain (curve 802) is compared to the simulated transimpedance (curve 804), and the measured S-parameter S.sub.21 (curve 806) is compared to the simulated S-parameter S.sub.21 (curve 808). FIG. 8A shows that the measured results are in close match with the post-layout simulation results. In particular, in the illustrated example, the measured S.sub.21 is 3 dB lower than the simulated S.sub.21 while the bandwidth is the same.

[0098] A second test setup involving a digital sampling oscilloscope and a spectrum analyzer (e.g., a Keysight DCA-X 86100D digital sampling oscilloscope and Keysight N9040B Spectrum Analyzer) was used to extract the noise properties of the proposed TIA circuit. The oscilloscope was used to extract a histogram of the output voltage noise from which the standard deviation of the noise voltage can be computed. The spectrum analyzer was used to measure the output noise voltage spectral density. In this embodiment, during each noise test, the inputs of the TIA circuit were left open, one of the differential outputs was terminated to a 50? resistor, and noise was measured on the other differential output. FIG. 8B shows a plot 810 illustrating the histogram of the output voltage noise obtained from the oscilloscope. The standard deviation of this histogram shows the equivalent output RMS noise voltage, which is 1.273 mV in this embodiment. In order to de-embed the noise of the measurement setup, it is desirable to subtract the noise of the oscilloscope (i.e. 1.12 mV) from the measured noise.

[0099] FIG. 8C shows a plot 820 that illustrates a comparison of the measured and simulated output voltage noise spectral densities. In particular, the output noise voltage spectral density measured from the spectrum analyzer after noise calibration is shown as curve 822, and the simulated noise density is illustrated as curve 824. From FIG. 8C, it can be seen that the noise measured using the oscilloscope and the noise measured using the spectrum analyzer are closely matched with the simulated noise density. The simulated output noise spectral density is higher than the measured density between 10 GHz to 25 GHz obtained using the spectrum analyzer. This is mainly due to the fact that there is less peaking in the measured transimpedance gain across this frequency range compared to the simulated one, as shown in FIG. 8A. The peak reduction in the measured results may be due to bond-pad loading, measurement setup losses, and process variations. In addition, the measured noise from the oscilloscope is slightly higher than that measured using the spectrum analyzer. This is due to the fact that de-embedding of ambient noise could be achieved to a greater accuracy via the spectrum analyzer compared to that for the oscilloscope. Therefore, the ambient noise is mainly causing slightly higher noise from the oscilloscope, as compared to the spectrum analyzer.

[0100] The transient behavior of the proposed TIA was then measured by applying a data stream (e.g., a PRBS-31 NRZ data stream) using a signal generator (e.g., Exosight EX05608), with the TIA being used in single-ended operation mode and the spare input and output terminated to 50? loads to create a 50? balanced system. A series of attenuators were used to reduce the input to an equivalent current level of 100 ?A.sub.pp (5 mV.sub.pp) amplitude to verify the sensitivity of the proposed TIA. FIG. 8D shows a plot 830 of a measured eye diagram achieved at the output of the TIA for a 30 Gb/s data stream, with a peak-to-peak eye amplitude of 113 mV.sub.pp. As can be seen from the example of FIG. 8A, in this embodiment, the measured 3 db bandwidth for the TIA is 34 GHz, which indicates that the TIA may be able to support data streams up to 68 Gb/s. In order to demonstrate this finding, the application of 67 Gb/s PRBS-31 NRZ data stream was simulated and the resulting eye diagram is shown in the plot 840 of FIG. 8E. Plot 840 shows that a 55 mV.sub.pp open eye may be obtained, which indicates that the proposed TIA can support up to a 67 Gb/s data rate.

[0101] From the above, it can be seen that, in some embodiments, with the appropriate pole-zero positioning, the DC transimpedance gain can be decoupled from the closed-loop TI bandwidth using the systems and methods described herein. This may allow for the simultaneous optimization of low frequency transimpedance gain, bandwidth and noise properties. The systems and methods described herein may also allow to achieve a TI limit that is higher than the conventional limit without the need for area-consuming inductors in the TI stage.

[0102] The foregoing disclosure of the exemplary embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many variations and modifications of the embodiments described herein will be apparent to one of ordinary skill in the art in light of the above disclosure. The scope of the invention is to be defined only by the claims appended hereto, and by their equivalents.