Gradient amplifier with compensation for dead time and forward voltage

Abstract

Non-linearities of a gradient amplifier (1) for powering a gradient coil (16) are caused by the finite dead time of the amplifier and/or by a forward voltage drop. The gradient amplifier (1) includes a controllable full bridge (8) and an output filter (9). The full bridge (8) is controlled to provide a desired coil current (i.sub.c), including receiving a desired duty cycle (a.sub.eff) of the gradient amplifier (1), measuring an input current (i.sub.filt) and an output voltage (uc.sub.filt) of the output filter (9), evaluating an modulator duty cycle (a.sub.mod), and providing the modulator duty cycle (a.sub.mod) for controlling the full bridge (8). The gradient amplifier (1) powers a gradient coil (16) including at least two half bridges (10), each having at least two power switches (11) connected in series. An output filter (9) connected to a tapped center points of the half bridges (10) between two the power switches (11). A controller provides a desired duty cycle (a.sub.eff) of the gradient amplifier (1), a compensation block (5) for providing an modulator duty cycle (a.sub.mod). A modulator (6) controls the power switches (11) according to the modulator duty cycle (a.sub.mod).

Claims

1. A method for compensating non-linearities of a gradient amplifier for powering a gradient coil, the gradient amplifier comprising a controllable full bridge and an output filter, whereby the full bridge is controlled to provide a desired coil current, the method comprising: receiving a desired duty cycle of the gradient amplifier, measuring an input current and an output voltage of the output filter, evaluating a modulator duty cycle as a function of the desired duty cycle and the measured input current and the measured output voltage, and providing the modulator duty cycle to a modulator for controlling the full bridge, comprising: generating a three-dimensional look-up table, which provides the modulator duty cycle as a function of the desired duty cycle, the input current and the output voltage, including generating supporting points, which have a mixed logarithmically/linear distribution comprising generating a set of supporting points for positive values with a number of n logarithmically distributed main divisions and a number of 2.sup.m linear subdivisions between each main division, where m is a set of bits following a most significant bit, and wherein the step of evaluating the modulator duty cycle comprises performing a look-up in the three-dimensional look-up table, the step of performing the look-up in the three-dimensional lookup-table comprises: determining an index value of the element in the three-dimensional look-up table by determining a logarithmic offset by evaluating a position of the most significant bit of the value to be looked-up and multiplying the position by 2.sup.m, taking the value of the set of m bits following the most significant bit as linear offset, and providing a sum of the logarithmic offset and the linear offset as index value.

2. The method according to claim 1, further comprising the step of generating an inverted three-dimensional look-up table, which provides the desired duty cycle as a function of the modulator duty cycle, the input current, and the output voltage, whereby the step of evaluating the modulator duty cycle further comprises performing a look-up of the desired duty cycle in the inverted three-dimensional lookup-table and determining the modulator duty cycle from the desired duty cycle according to the inverted three-dimensional look-up table.

3. The method according to claim 2, wherein the step of determining the modulator duty cycle from the desired duty cycle according to the inverted three-dimensional look-up table comprises approximating of the modulator duty cycle using a bisection method.

4. The method according to claim 1, wherein the step of evaluating the modulator duty cycle comprises performing an interpolation between supporting points of the three-dimensional look-up table.

5. The method according to claim 1, further including: performing a linear interpolation between the supporting points of the three-dimensional look-up table, whereby a remainder following the set of m bits following the most significant bit defines the position of the value to be looked-up between adjacent supporting points.

6. The method according to claim 1, wherein the step of generating the three-dimensional look-up table comprises determining supporting points of the three-dimensional look-up table by simulation or by mathematical calculation.

7. A non-transitory computer-readable medium carrying a set of instructions that controls a computer to perform the method according to claim 1.

8. A method for compensating non-linearities of a gradient amplifier for powering a gradient coil, the gradient amplifier comprising a controllable full bridge and an output filter, whereby the full bridge is controlled to provide a desired coil current, the method comprising: receiving a desired duty cycle of the gradient amplifier, measuring an input current and an output voltage of the output filter, evaluating a modulator duty cycle as a function of the desired duty cycle and the measured input current and the measured output voltage, and providing the modulator duty cycle to a modulator for controlling the full bridge and comprising the step of generating a three-dimensional look-up table, which provides the modulator duty cycle as a function of the desired duty cycle, the input current and the output voltage, comprising generating supporting points, which have a mixed logarithmically/linear distribution comprising generating a set of supporting points equally distributed around zero with a number of 2n logarithmically distributed main divisions and a number of 2.sup.m linear subdivisions between each main division, where m is a set of bits following a most significant bit, and wherein the step of evaluating the modulator duty cycle comprises performing a look-up in the three-dimensional look-up table, the step of performing the look-up in the three-dimensional lookup-table comprises: determining an index value of the element in the three-dimensional look-up table by forming the absolute value of value to be looked-up, determining a logarithmic offset by evaluating a position of the most significant bit of the absolute value and multiplying the position by 2.sup.m, taking the value of the set of m bits following the most significant bit as linear offset, and in case the value to be looked-up being a negative value, providing the half number of elements of the three-dimensional look-up table reduced by a sum of the logarithmic offset and the linear offset as index value, and otherwise providing a sum of a half number of elements of the three-dimensional look-up table, the logarithmic offset and the linear offset as index value.

9. A gradient amplifier for powering a gradient coil comprising: at least two half bridges, each half bridge having at least two power switches connected in series; an output filter having inputs connected to tapped center points of the half bridges, and outputs configured to be connected to a magnetic field gradient coil; a compensation block configured to receive a desired duty cycle (a.sub.eff), an input current (i.sub.filt) received on the filter inputs, and a filter output voltage (Uc.sub.filt) at the filter outputs, input the desired duty cycle (a.sub.eff), the input current (i.sub.filt) and the filter output voltage (Uc.sub.filt) into a three-dimensional look-up table, and retrieve a modulator duty cycle (a.sub.mod) from the three dimensional-look-up table; and a modulator configured to control the power switches with the modulator duty cycle (a.sub.mod) retrieved from the three-dimensional look-up table.

10. The gradient amplifier according to claim 9, wherein the power switch comprises a power transistor.

11. The gradient amplifier according to claim 10, wherein the power transistor includes a MOSFET or an IGBT connected in parallel with a diode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

(2) In the drawings:

(3) FIG. 1 shows a schematical view of a gradient amplifier according to an embodiment of the invention,

(4) FIG. 2 shows details of the power stage of the gradient amplifier of FIG. 1 with a gradient coil connected to the power stage,

(5) FIG. 3 shows an equivalent circuit of the full bridge with the output filter of FIG. 2,

(6) FIG. 4 shows a half-bridge of the full bridge of FIG. 2 in different operation states with the respective currents in these operation states,

(7) FIG. 5 shows a timing diagram illustrating output voltages of the full bridge of FIG. 2,

(8) FIG. 6 shows an equivalent circuit for forward voltages of the full bridge of FIG. 2,

(9) FIG. 7 shows a timing diagram of the output diagram of the full bridge obtained by analytic calculations,

(10) FIG. 8 shows a timing diagram of the output diagram of the full bridge obtained by simulation in time domain,

(11) FIG. 9 shows a graph of a combined logarithmic/linear distribution of supporting points on a positive axis with an exemplary look-up value,

(12) FIG. 10 shows a determination of the look-up table index based on the combined logarithmic/linear distribution of supporting points and the exemplary look-up value according to FIG. 9,

(13) FIG. 11 shows a graph of a combined logarithmic/linear distribution of supporting points on an axis covering positive and negative look-up values,

(14) FIG. 12 shows a determination of the look-up table index based on the combined logarithmic/linear distribution of supporting points according to FIG. 11 for a negative exemplary look-up value,

(15) FIG. 13 shows a general interpolation for positive and negative values,

(16) FIG. 14 shows a general three-dimensional multi-linear interpolation,

(17) FIG. 15 shows table functions for the desired duty cycle as function of the modulator duty cycle and the inverted function for the modulator duty cycle as function of the desired duty cycle,

(18) FIG. 16 shows an illustration of the bisection method,

(19) FIG. 17 shows a transient response for a gradient amplifier without non-linear compensation by a compensation block,

(20) FIG. 18 shows a transient response for a gradient amplifier with non-linear compensation by a compensation block, and

(21) FIG. 19 shows a three-dimensional diagram of an exemplary compensation table for the filter current equal to zero.

DETAILED DESCRIPTION OF EMBODIMENTS

(22) FIG. 1 shows a schematical view 1 of a gradient amplifier according to an embodiment of the invention. The gradient amplifier 1 comprises a main current controller 2, which provides a requested voltage U.sub.eff that corresponds to an averaged converter voltage over one PWM cycle.

(23) The gradient amplifier 1 further comprises a duty cycle calculation unit 3, which provides a desired duty cycle a.sub.eff, also referred to as effective duty cycle a.sub.eff, by dividing U.sub.eff by the overall DC bus voltage. Hence, a.sub.eff corresponds to the duty cycle that is requested by the main controller 2. The main controller 2 and the duty cycle calculation unit 3 form a controller unit 4, which provides as output the desired duty cycle a.sub.eff.

(24) The gradient amplifier 1 further comprises a compensation block 5 for providing a modulator duty cycle a.sub.mod, which is a duty cycle containing a compensation of non-linearities of the gradient amplifier 1. The compensation block 4 receives as input values the effective duty cycle a.sub.eff, a measured filter current i.sub.filt and a measured filter voltage u.sub.cfilt, and provides the modulator duty cycle a.sub.mod by means of a look-up table and interpolation, which will be described later in detail.

(25) The gradient amplifier 1 further comprises a modulator 6 and a power stage 7, whereby the modulator 6 controls the power stage 7. The power stage, which is best seen in FIG. 2, comprises a controllable full bridge 8 and an output filter 9. The full bridge 8 in this embodiment comprises two half-bridges 10, each of which comprising two switches 11 with a power transistor 12 and a diode 13, which is a power diode in this embodiment and maybe the intrinsic diode of this device. The power transistor 12 in this embodiment is an IGBT, and the power diode 13 is connected in parallel to the collector-emitter path of the power transistor 12, whereby for each power switch 11 the collector-emitter path of the power transistor 12 has the same direction as the reverse direction of the power diode 13. In detail, the full bridge 8 is controlled by the modulator 6 by controlling the power transistors 12, whereby the modulator 6 uses a Pulse Width Modulation (PWM). Each half-bridge 10 is tapped at its center point between the power switches 11 and connected to the output filter 9.

(26) The output filter 9 is a LC-filter comprising at least an inductance 14 and a capacitance 15 for reducing interferences and ripple-currents. The filter inductance is typically low to minimize voltage loss over the output filter 9.

(27) The output filter 9 is electrically connected to a gradient coil 16. The gradient coil 16 generates a magnetic field depending on a gradient coil current i.sub.GC for providing spatial information in an MRI-system, which is in its entirety not shown in the figures.

(28) In operation, the control unit 4 provides a desired duty cycle a.sub.eff to the compensation block 5. The compensation block 5 is further connected to receive measurements of the filter current i.sub.filt and filter voltage u.sub.cfilt of the output filter 9. The compensation block 5 comprises a three-dimensional look-up table for evaluating a modulator duty cycle a.sub.mod from the provided input values and applying multidimensional linear interpolation. In this embodiment of the invention, the look-up table has the modulator duty cycle a.sub.mod as output value and the desired duty cycle a.sub.eff, the filter current i.sub.filt filter voltage u.sub.cfilt as input values. The look-up table is calculated according to any of the examples given below.

(29) FIG. 15 shows that the compensation function a.sub.mod=f(a.sub.eff,i.sub.filt,u.sub.cfilt) has steep slopes, so that a high number of supporting points is required to achieve sufficient accuracy. Thus, in order to reduce the number of required data points, in an alternative embodiment, the look-up table is inverted and has the desired duty cycle a.sub.eff as output value and the modulator duty cycle a.sub.mod, the filter current i.sub.filt filter voltage u.sub.cfilt as input values with the compensation function a.sub.eff=f(a.sub.mod,i.sub.filt,u.sub.cfilt). In this case, a bisectional approximation of the modulator duty cycle a.sub.mod is performed, as shown in FIG. 16. Particularly, the determination of the required a.sub.mod for a given a.sub.eff, is done by root determination with the bisection method. The function, of which the root a.sub.mod0 has to be determined is the function f*=a.sub.eff(a.sub.mod,i.sub.filt,u.sub.cfilt)a.sub.eff0, where a.sub.eff0 is the value for which the a.sub.mod has to be found. According to the bisectional method, one starts with a known interval [a=1, b=1] that comprises the value of a.sub.mod. Now, the center point m.sub.1 of this interval is determined. If f*(m.sub.1) and f*(a) have opposite sign, the root is in between a and m.sub.1. If this is not the case, the root is in between m.sub.1 and b. Now, this step is repeated with this new interval and the determination of the new center point m.sub.2. During each iteration step, the width of the interval is reduced by a factor of 2. The method has guaranteed convergence, and the accuracy of the solution does not depend on the type of function. The run-time of the algorithm is very predictable, which is advantageous for the realization in a digital control environment.

(30) In order to reduce the number of required supporting points of the three-dimensional look-up table, a mixed logarithmic/linear distribution of the supporting points is chosen in this embodiment. Such a distribution for positive values is shown in FIG. 9. There are n logarithmically (base of 2) distributed main divisions and 2.sup.m linear sub-divisions in between. FIG. 9 illustrates this kind of distribution with n=4 and m=2. The advantage of such a distribution is, that the table indices i for a given value x can be determined very fast and easy from the binary value of x. The table index resulting from the logarithmic ticks is simply given by the position of the most significant 1-bit multiplied with the number 2.sup.m of linear divisions. If all bits of the integer part are 0, the offset is also 0. The next m=2 bits that follow the most significant 1 bit (this extends also to the fractional part) determine the index offset given by the linear division. If the integer part is 0, the first two bits of the fractional part determine the linear table offset. The linear offset has to be added to the logarithmic offset to obtain the overall table index. The bits following the linear offset determine directly the fractional part (0-1) between the table index value and its successor according to (xx.sub.1)/(x.sub.2x.sub.1). Accordingly, this value can be used directly for the linear interpolation, so that there is no division necessary for the interpolation guaranteeing fast execution in the digital control system, as described in detail below.

(31) FIG. 10 illustrates the determination of the table index for an example value of x=3.65625. The table values resulting from this evaluation are the values 11 and 12. The reminder of 0.3125 is used directly for the interpolation.

(32) The look-up table should also cover negative and positive values with a logarithmic distribution around zero. This is because the major nonlinearities of the hardware system are centered around zero. Thus, a distribution of the supporting points can be chosen as depicted in FIG. 11. The determination of the table indices can be done as shown in FIG. 12. At first the absolute value of the x-value is determined and then the table index is determined as described above with reference to a table containing only positive values. For positive x the overall table index is 12 plus this table index, for negative x the overall table index is 12 minus this table index.

(33) The interpolation between the table values is slightly different for positive and negative x-values, as shown in FIG. 13. For positive x the index i resulting from the above algorithm denotes the supporting point that is smaller than the value x itself. That means the supporting point i+1 is larger than x. For x<0 the situation is reversed. The index i denotes the supporting point that is larger than x, the supporting point i1 is smaller. In both cases a remainder of zero corresponds to the table index i itself

(34) The overall one-dimensional interpolation algorithm itself is now given by:
x=x.sub.in/x.sub.max*2.sup.n-1
x.sub.abs=abs(x)

(35) i.sub.log=max(bitposition of leftmost 1 bit in x.sub.abs, 0)

(36) i.sub.log1: i.sub.lin=binary number given by m bits in x.sub.abs after leftmost 1 bit

(37) i.sub.log=0: i.sub.lin=binary number given by first m bits in x.sub.abs of fractional part
x0: i=n2.sup.m+i.sub.log 2.sup.m+i.sub.lin
x<0: i=n2.sup.mi.sub.log 2.sup.m+i.sub.lin

(38) r=all remaining bits after linear bits in x.sub.abs (fractional part 0-1)
x0: f=f.sub.i+r(f.sub.i+1f.sub.i)
x<0: f=f.sub.i+r(f.sub.i1f.sub.i)

(39) By the above described one-dimensional determination of the table indices, the 8 vertices of a cube can be determined containing the point x, y, z, where the function value has to be calculated. FIG. 14 illustrates the three-dimensional interpolation method as described below.

(40) The eight vertices (x.sub.1/2, y.sub.1/2, z.sub.1/2) are the corners of a cube 20. The corresponding function values f.sub.i,j,k are stored in the table. In a first step, four one-dimensional interpolations on the cube edges are executed according to one of the three axis. From this the function values f.sub.ij at the four corners of the intermediate plain 21, thus formed by the points f.sub.11, f.sub.21, f.sub.12 and f.sub.22, will follow. The x-value of this plain 21 is already identical to the x-value of the data point (x,y,z). The dimension of the remaining interpolation task is two, meaning that it is reduced by 1.

(41) In a second step, two more one-dimensional interpolations are executed on the edges of the plain 21. From this function values f.sub.i at the two end-points of line 22 are determined. The x- and y-values of the line 22 are already identical to the x- and y-values of the data point (x,y,z). The dimension of the remaining interpolation task is further reduced to one.

(42) In a last step, a single one-dimensional interpolation on the line 22 is executed, that determines the function value fat the given point (x,y,z).

(43) All in all seven 1-dimensional interpolations have to be executed for the 3-dimensional multi-linear interpolation. These are:

(44) $f_{11}=f_{111}+f_{211}\frac{x-x_1}{x_2-x_1}$$f_{12}=f_{112}+f_{212}\frac{x-x_1}{x_2-x_1}$$f_{21}=f_{121}+f_{221}\frac{x-x_1}{x_2-x_1}$$f_{22}=f_{122}+f_{222}\frac{x-x_1}{x_2-x_1}$$f_1=f_{11}+f_{21}\frac{y-y_1}{y_{2-}{y}_1}$$f_2=f_{12}+f_{22}\frac{y-y_1}{y_2-y_1}$$f=f_1+f_2\frac{z-z_1}{z_2-z_1}$

(45) As already mentioned above, the interpolation factors (xx.sub.1)(x.sub.2x.sub.1), (yy.sub.1)(y.sub.2y.sub.1),(zz.sub.1)(z.sub.2z.sub.1) need not to be calculated! They already result from the table index determination and are identical to the remainder r in FIG. 12. Thus, no time consuming division is required.

(46) Below a first example for determining table values for the look-up table used in the compensation block 5 by means of mathematical calculation will be explained.

(47) FIG. 3 shows an equivalent circuit for the power stage 7 comprising a voltage source 17 representing the full bridge 8 as well as inductance 14 and capacitance 15 of the output filter 9. The load current of the output filter 9 is the gradient current that is assumed to be constant over one PWM period. The voltage applied to the output filter 9 is the output voltage of the full bridge 8 which is the difference of the voltages of the two half-bridges 10.

(48) The half-bridges 10 are controlled by the modulator 6 according to the phase shift modulation method to generate a PWM signal. FIG. 5 depicts the control signals (HIGH, LOW, INACTIVE) for the two half-bridges 10 and the resulting full bridge output voltage. Accordingly, each half-bridge 10 has three different operational states high, low or inactive, as shown in FIG. 4. In the high-state the upper power switch 11 is on, while the lower power switch 11 is off. Thus, the output of the half-bridge is connected to the positive rail of supply voltage U.sub.0. In low-state the lower power switch 11 is on, while the upper power switch 11 is off. Thus, the output of the half-bridge 10 is connected to the negative rail of U.sub.0. During the dead-time the half-bridge is in inactive-state, which means that both power switch 11 are off. In this case, the current is flowing through the antiparallel power diodes 13, which means that the output voltage depends on the sign of the filter current i.sub.filt. For a filter current i.sub.filt. flowing out of the half-bridge 10, the output is connected to the negative rail of U.sub.0 via the respective power diode 11 of the half-bridge 10, while for a filter current i.sub.filt. flowing into the half-bridge 10, the output is connected to the positive rail of U.sub.0, respectively. The pulse time is chosen to be T.sub.pulse=a.sub.modT.sub.PWM. If no dead-time T.sub.D would be present and the forward voltage would be zero, this would lead to an effective output voltage of a.sub.mod*U.sub.0, thus no compensation would be required as a.sub.mod is equal to a.sub.eff. However, the dead time T.sub.D introduces an effective voltage error and makes a.sub.eff unequal to a.sub.mod, since the filter current i.sub.filt can vary, thus compensation is required.

(49) Additionally to the described nonlinear effect caused by the dead-time, there is also the nonlinear effect that is caused by the forward voltages of the power switches 11, i.e. the power transistor 12 and a power diode 13. Two equivalent circuits for this situation, one for positive and one for negative load currents i, are shown in FIG. 6. It is furthermore for simplification of the analytical calculation assumed that all power transistors 12 and power diodes 13 have the same forward voltage V.sub.f, which has a value that is only dependent on the sign of the load current. From these equivalent circuits the output voltages u.sub.CV for all possible switch signals can be deduced. There are always two power transistors 12/power diodes 13 in the voltage path for all configurations, one from the left half-bridge 10 and one from the right half-bridge 10. Thus, it is

(50) $u_{\mathrm{CV}}=\left\{\begin{array}{c}+U_0\\ 0\\ -U_0\end{array}\right\}-2V_f\mathrm{for}i>0,u_{\mathrm{CV}}=\left\{\begin{array}{c}+U_0\\ 0\\ -U_0\end{array}\right\}+2V_f\mathrm{for}i<0$

(51) So the output voltage is decreased by 2V.sub.f for positive current and increased by 2V.sub.f for negative current leading to a certain voltage error depending on the sign of the current (averaged over one PWM period). This is true for arbitrary switch signals.

(52) With the assumptions above the waveforms for the filter current i.sub.filt, the filter voltage u.sub.cfilt and the output voltage of the full bridge 8 can be now be calculated by evaluating the differential equations for the system shown in FIG. 3, when knowing the states i.sub.filt, u.sub.cfilt, i.sub.GC at the start of the PWM cycle and the duty cycle a.sub.mod for this PWM cycle. Some approximations have been made that reduce the computational effort for the solution of the differential equation. These are in particular that i.sub.GC is assumed to be constant over one PWM period and u.sub.cfilt is assumed to be constant during subsequent zero crossings of the filter current i.sub.filt. FIG. 7 shows an exemplary result with a.sub.mod=0.2, i.sub.filt,0=100 A, u.sub.cfilt,0=500V, i.sub.GC=0 A for such an analytic evaluation. The effective output voltage can simply be calculated by determining the average voltage of the full bridge output voltage u.sub.CV. Such a calculation has to be done for every supporting point of the three dimensional table to generate the whole compensation data. To limit the number of input values for the table to three, the value i.sub.GC will not be an individual input to the table but will be set to i.sub.GC,0. This equalization is a good approximation, especially for stationary currents. The resulting a.sub.eff as a function of a.sub.mod can either be stored directly in the table, or the inverse function amod=f(a.sub.eff) can be calculated offline and stored in the table. In the latter case, the table data can be used directly for compensation, in the first case the inversion has to be done on-line in the control system hardware before it can be used for compensation (see below). The advantage of doing the inversion off-line is a faster execution, while doing the inversion on-line results in a smaller compensation table and saves memory of the compensation block 6.

(53) Below will be explained a second example for determining table values for the look-up table used in the compensation block 5 by use of a time domain simulation software.

(54) The time domain simulation software (e.g. SIMULINK) is used to solve differential equations instead of using analytic calculations to determine the average converter output voltage for each set of parameters (a.sub.mod, i.sub.filt, u.sub.cfilt), as described above. FIG. 8 depicts a time domain simulation of one PWM cycle. The advantage is that the simulation model can be more detailed and thus be more precise than an analytical model. For example parasitic node capacitances at the output of the half-bridges 10 have a big impact on the converter output voltage and can be considered easily. Also the forward voltages of the power transistors 12/power diodes 13 can have a nonlinear dependency on the magnitude of the current. The price for this is a higher computation time for the table data. However, as the tables are determined offline, this is mostly irrelevant. Also for the simulative analysis it can be chosen to execute the function inversion off-line or on-line in the control system hardware.

(55) FIG. 19 shows a 3D-visualization of the three-dimensional look-up table for compensation of the non-linearities of the gradient amplifier 1. It shows the effective duty cycle a.sub.eff as a function of the modulator duty cycle a.sub.mod and the filter capacitor voltage u.sub.cfilt. The remaining value of i.sub.filt is zero. This table is used in the compensation block 5 to find the inverse function a.sub.mod=f(a.sub.eff,i.sub.filt,u.sub.cfilt) by the bisectional method. The table has a number of 41 supporting points in a.sub.mod direction, a number of 11 supporting points in i.sub.filt direction and a number of 21 supporting points in u.sub.cfilt direction. The supporting points in i.sub.filt and u.sub.cfilt direction are distributed semi logarithmically. a.sub.mod uses a linear distribution.

(56) The advantages of this embodiment can be easily seen by comparing FIGS. 17 and 18. FIG. 17 shows a transient response for a gradient amplifier without compensation of the nonlinearities given by the dead-time and forward voltages. The controller is not stable, especially for small gradient currents the performance is far from being acceptable. By applying the above compensation to the system and using the bisection method to find the inverse function the transient response depicted below can be achieved.

(57) While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.