COLUMN INVERSION DRIVING CIRCUIT AND DISPLAY PANEL

Abstract

An embodiment of the present invention provides a column inversion driving circuit. The column inversion driving circuit could reduce the voltage level of the logic low of the n.sup.th impulse signal, which is used to control the n.sup.th TFT matrix, through the cooperation of the voltage level of the n.sup.th impulse signal and the n.sup.th positive data signal. Furthermore, the voltage level of the logic high of the (n+1).sup.th impulse signal, which is used to control the (n+1).sup.th TFT matrix, is also reduced through the cooperation of the voltage level of the (n+1).sup.th impulse signal and the (n+1).sup.th negative data signal. This reduces the power consumption of the column inversion driving circuit.

Claims

1. A column inversion driving circuit, comprising at least one column inversion driving unit, wherein a n.sup.th column inversion unit comprises a n.sup.th TFT matrix and a (n+1).sup.th TFT matrix; wherein a source of the n.sup.th TFT matrix is electrically connected to a n.sup.th column positive data signal, a gate of the n.sup.th TFT matrix is electrically connected to a n.sup.th impulse signal set, and a drain of the n.sup.th TFT matrix is electrically connected to a corresponding sub-pixel of an odd column; wherein a source of the (n+1).sup.th TFT matrix is electrically connected to a (n+1).sup.th column negative data signal, a gate of the (n+1).sup.th TFT matrix is electrically connected to a (n+1).sup.th impulse signal set, and a drain of the (n+1).sup.th TFT matrix is electrically connected to a corresponding sub-pixel of an even column; and wherein a voltage level of a logic low of the n.sup.th impulse signal set is higher than a turn-off voltage of the n.sup.th TFT matrix, a voltage level of a logic high of the (n+1).sup.th impulse signal set is lower than a turn-on voltage of the (n+1).sup.th TFT matrix, and the (n+1).sup.th TFT matrix comprises a plurality of n-channel TFTs.

2. The column inversion driving circuit of claim 1, wherein the n.sup.th TFT matrix comprises a first TFT, a second TFT, and a third TFT; wherein the n.sup.th column positive data signal is electrically connected to a source of the first TFT, a source of the second TFT and a source of the third TFT; the n.sup.th impulse signal set is electrically connected to a gate of the first TFT, a gate of the second TFT and a gate of the third TFT; a drain of the first TFT is electrically connected to a n.sup.th sub-pixel of an odd column; a drain of the second TFT is electrically connected to a (n+1).sup.th sub-pixel of an odd column, and a drain of the third TFT is electrically connected to a (n+2).sup.th sub-pixel of an odd column.

3. The column inversion driving circuit of claim 2, wherein the n.sup.th impulse signal set comprises a first impulse signal, a second impulse signal and a third impulse signal; wherein the first impulse signal is electrically connected to the gate of the first TFT, the second impulse signal is electrically connected to the gate of the second TFT, and the third impulse signal is electrically connected to the gate of the third TFT.

4. The column inversion driving circuit of claim 3, wherein a voltage level of a logic low of the first impulse signal is higher than a turn-off voltage of the first TFT, a voltage level of a logic low of the second impulse signal is higher than a turn-off voltage of the second TFT, and a voltage level of a logic low of the third impulse signal is higher than a turn-off voltage of the third TFT.

5. The column inversion driving circuit of claim 1, wherein the (n+1).sup.th TFT matrix comprises a fourth TFT, a fifth TFT, and a sixth TFT; wherein the (n+1).sup.th column negative data signal is electrically connected to a source of the fourth TFT, a source of the fifth TFT, and a source of the sixth TFT; the (n+1).sup.th impulse signal set is electrically connected to a gate of the fourth TFT, a gate of the fifth TFT, and a gate of the sixth TFT; a drain of the fourth TFT is electrically connected to a n.sup.th sub-pixel of an even column; a drain of the fifth TFT is electrically connected to a (n+1).sup.th sub-pixel of an even column; and a drain of the sixth TFT is electrically connected to a (n+2).sup.th sub-pixel of an even column.

6. The column inversion driving circuit of claim 5, wherein the (n+1).sup.th impulse signal set comprises a fourth impulse signal, a fifth impulse signal and a sixth impulse signal; wherein the fourth impulse signal is electrically connected to the gate of the fourth TFT, the fifth impulse signal is electrically connected to the gate of the fifth TFT, and the sixth impulse signal is electrically connected to the gate of the sixth TFT.

7. The column inversion driving circuit of claim 6, wherein a voltage level of a logic high of the fourth impulse signal is lower than a turn-on voltage of the fourth TFT, a voltage level of a logic high of the fifth impulse signal is lower than a turn-on voltage of the fifth TFT, and a voltage level of a logic high of the sixth impulse signal is lower than a turn-on voltage of the sixth TFT.

8. The column inversion driving circuit of claim 1, wherein the n.sup.th TFT matrix comprises a plurality of n-channel TFTs.

9. A column inversion driving circuit, comprising at least one column inversion driving unit, wherein a n.sup.th column inversion unit comprises a nth TFT matrix and a (n+1)th TFT matrix; wherein a source of the n.sup.th TFT matrix is electrically connected to a n.sup.th column positive data signal, a gate of the n.sup.th TFT matrix is electrically connected to a n.sup.th impulse signal set, and a drain of the n.sup.th TFT matrix is electrically connected to a corresponding sub-pixel of an odd column; wherein a source of the (n+1).sup.th TFT matrix is electrically connected to a (n+1).sup.th column negative data signal, a gate of the (n+1).sup.th TFT matrix is electrically connected to a (n+1).sup.th impulse signal set, and a drain of the (n+1).sup.th TFT matrix is electrically connected to a corresponding sub-pixel of an even column; and wherein a voltage level of a logic low of the n.sup.th impulse signal set is higher than a turn-off voltage of the n.sup.th TFT matrix, and a voltage level of a logic high of the (n+1).sup.th impulse signal set is lower than a turn-on voltage of the (n+1).sup.th TFT matrix.

10. The column inversion driving circuit of claim 9, wherein the n.sup.th TFT matrix comprises a first TFT, a second TFT, and a third TFT; wherein the n.sup.th column positive data signal is electrically connected to a source of the first TFT, a source of the second TFT and a source of the third TFT; the n.sup.th impulse signal set is electrically connected to a gate of the first TFT, a gate of the second TFT and a gate of the third TFT; a drain of the first TFT is electrically connected to a n.sup.th sub-pixel of an odd column; a drain of the second TFT is electrically connected to a (n+1).sup.th sub-pixel of an odd column, and a drain of the third TFT is electrically connected to a (n+2).sup.th sub-pixel of an odd column.

11. The column inversion driving circuit of claim 10, wherein the n.sup.th impulse signal set comprises a first impulse signal, a second impulse signal and a third impulse signal; wherein the first impulse signal is electrically connected to the gate of the first TFT, the second impulse signal is electrically connected to the gate of the second TFT, and the third impulse signal is electrically connected to the gate of the third TFT.

12. The column inversion driving circuit of claim 11, wherein a voltage level of a logic low of the first impulse signal is higher than a turn-off voltage of the first TFT, a voltage level of a logic low of the second impulse signal is higher than a turn-off voltage of the second TFT, and a voltage level of a logic low of the third impulse signal is higher than a turn-off voltage of the third TFT.

13. The column inversion driving circuit of claim 9, wherein the (n+1).sup.th TFT matrix comprises a fourth TFT, a fifth TFT, and a sixth TFT; wherein the (n+1).sup.th column negative data signal is electrically connected to a source of the fourth TFT, a source of the fifth TFT, and a source of the sixth TFT; the (n+1).sup.th impulse signal set is electrically connected to a gate of the fourth TFT, a gate of the fifth TFT, and a gate of the sixth TFT; a drain of the fourth TFT is electrically connected to a n.sup.th sub-pixel of an even column; a drain of the fifth TFT is electrically connected to a (n+1).sup.th sub-pixel of an even column; and a drain of the sixth TFT is electrically connected to a (n+2).sup.th sub-pixel of an even column.

14. The column inversion driving circuit of claim 13, wherein the (n+1).sup.th impulse signal set comprises a fourth impulse signal, a fifth impulse signal and a sixth impulse signal; wherein the fourth impulse signal is electrically connected to the gate of the fourth TFT, the fifth impulse signal is electrically connected to the gate of the fifth TFT, and the sixth impulse signal is electrically connected to the gate of the sixth TFT.

15. The column inversion driving circuit of claim 14, wherein a voltage level of a logic high of the fourth impulse signal is lower than a turn-on voltage of the fourth TFT, a voltage level of a logic high of the fifth impulse signal is lower than a turn-on voltage of the fifth TFT, and a voltage level of a logic high of the sixth impulse signal is lower than a turn-on voltage of the sixth TFT.

16. The column inversion driving circuit of claim 9, wherein the n.sup.th TFT matrix comprises a plurality of n-channel TFTs.

17. A display panel, comprising: a data driver, providing an nth column positive data signal and an (n+1)th column negative data signal; a data selector, providing an nth impulse signal set and an (n+1)th impulse signal set; and a column inversion driving circuit, comprising at least one column inversion driving unit, wherein a nth column inversion unit comprises a nth TFT matrix and a (n+1)th TFT matrix; wherein a source of the nth TFT matrix is electrically connected to the nth column positive data signal, a gate of the nth TFT matrix is electrically connected to the nth impulse signal set, and a drain of the nth TFT matrix is electrically connected to a corresponding sub-pixel of an odd column; wherein a source of the (n+1)th TFT matrix is electrically connected to the (n+1)th column negative data signal, a gate of the (n+1)th TFT matrix is electrically connected to the (n+1)th impulse signal set, and a drain of the (n+1)th TFT matrix is electrically connected to a corresponding sub-pixel of an even column; and wherein a voltage level of a logic low of the nth impulse signal set is higher than a turn-off voltage of the nth TFT matrix, a voltage level of a logic high of the (n+1)th impulse signal set is lower than a turn-on voltage of the (n+1)th TFT matrix, and the (n+1)th TFT matrix comprises a plurality of n-channel TFTs.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1a is a diagram of a conventional MUX1:3 circuit.

[0017] FIG. 1b is a diagram of charging the positive data voltage in the MUX1:3 circuit shown in FIG. 1a.

[0018] FIG. 1c is a diagram of charging the negative data voltage in the MUX1:3 circuit shown in FIG. 1a.

[0019] FIG. 2 is a diagram of a conventional MUX1:6 circuit

[0020] FIG. 3 is a diagram of a column inversion driving circuit according to an embodiment of the present invention.

[0021] FIG. 4 is a diagram of a column inversion driving circuit according to another embodiment of the present invention.

[0022] FIG. 5a is a diagram showing the operations of the column inversion driving circuit according to an embodiment of the present invention.

[0023] FIG. 5b is a diagram of charging the positive data voltage in the column inversion driving circuit shown in FIG. 5a.

[0024] FIG. 5c is a diagram of charging the negative data voltage in the column inversion driving circuit shown in FIG. 5a.

[0025] FIG. 6a is a diagram of the first impulse signal set when the column inversion driving circuit performs the column inversion.

[0026] FIG. 6b is a diagram of the second impulse signal set when the column inversion driving circuit performs the column inversion.

[0027] FIG. 7 is a diagram of a display panel according to an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0028] For the purpose of description rather than limitation, the following provides such specific details as a specific system structure, interface, and technology for a thorough understanding of the application. However, it is understandable by persons skilled in the art that the application can also be implemented in other embodiments not providing such specific details. In other cases, details of a well-known apparatus, circuit and method are omitted to avoid hindering the description of the application by unnecessary details. In order to clearly illustrate the purpose, technique and advantage of the present invention, the MUX1:3 pixel charging mechanism is used as an example.

[0029] Please refer to FIG. 1a. MUXR, MURG, and MURB respectively represent the MUX control signal lines corresponding to R, G, B sub-pixels. D1 and D2 are data signals. MUX transistors are turned on or off to control the transmission of the data signals (data voltages). In this case, the column inversion mechanism is adopted. In the m.sup.th frame, when D1 transmits a positive data voltage, the adjacent D2 transmits a negative data voltage. Thus, the column of sub-pixels R1 correspond to the positive data voltage, the column of sub-pixels G1 corresponds to the negative data voltage, the column of sub-pixels B1 corresponds to the positive data voltage, and so on. In the (m+1).sup.th frame, the polarities are inversed. When the column of gates are turned on (column scan signal corresponds to the high voltage level), the data lines, controlled by the MUXR, MUXG, and MUXB, charges the R, G, and B sub-pixels at different time. The MUXR, MUXG, and MUXB are turned on in an order. Only when the gate and the MUXR are simultaneously turned on, the data line D1 changes the R1. When the gate and the MUXG are simultaneously turned on, the data line D1 changes the G1. When the gate and the MUXB are simultaneously turned on, the data line D1 changes the B1. Therefore, the switching frequency of the MUX is three times of the switching frequency of the gate. MUX1:n circuit has a similar operation, which means that the switching frequency of the MUX is n times of the switching frequency of the gate.

[0030] Please refer to FIG. 1b. FIG. 1b is a diagram of charging the positive data voltage in the MUX1:3 circuit shown in FIG. 1a. VON is the turn-on voltage of the transistor. VOFF is the turn-off voltage of the transistor. That is, the MUX control signal needs to be periodically switched between VON and VOFF to turn on/turn off the transistor. X is the voltage of the data line D1. The gate of the transistor is connected to the MUX control signal line. The source of the transistor represents an end having a lower voltage level. Vgs is the voltage difference between the gate and the source of the transistor. At the time when the MUX transistor is being turned on, Vgs is equal to VON. At the time when the MUX transistor is being turned off, Vgs is equal to the absolute value of VOFF−X (VOFF is a negative value). Therefore, the negative voltage level outputted by the MUX control signal is much lower than turn-off threshold value VOFF of the transistor. The voltage difference ΔV=X is wasted.

[0031] Please refer to FIG. 1c. FIG. 1c is a diagram of charging the negative data voltage in the MUX1:3 circuit shown in FIG. 1a. −X is the voltage of the data line D2. At the time when the MUX transistor is being turned on, Vgs is equal to VON−(−X)=VON+X. This is also higher than the threshold voltage of the transistor and wastes the voltage difference ΔV=X. Thus, this mechanism increases the power consumption.

[0032] Similarly, the MUX1:6 pixel charging mechanism also wastes some voltages and increases the power consumption.

[0033] Please refer to FIG. 3. FIG. 3 is a diagram of a column inversion driving circuit according to an embodiment of the present invention. As shown in FIG. 3, a column inversion driving circuit is disclosed. The column inversion driving circuit comprises at least one column inversion driving unit. Here, the n.sup.th column inversion unit comprises the n.sup.th TFT matrix 10 and the (n+1).sup.th TFT matrix 20. The source of the n.sup.th TFT matrix 10 is electrically connected to the n.sup.th column positive data signal. The gate of the n.sup.th TFT matrix 10 is electrically connected to the n.sup.th impulse signal set. The drain of the n.sup.th TFT matrix 10 is electrically connected to a corresponding sub-pixel of an odd column. The source of the (n+1).sup.th TFT matrix 20 is electrically connected to the (n+1).sup.th column negative data signal. The gate of the (n+1).sup.th TFT matrix 20 is electrically connected to the (n+1).sup.th impulse signal set. The drain of the (n+1).sup.th TFT matrix 20 is electrically connected to a corresponding sub-pixel of an even column. The voltage level of a logic low of the n.sup.th impulse signal set is higher than the turn-off voltage of the n.sup.th TFT matrix 10. The voltage level of a logic high of the (n+1).sup.th impulse signal set is lower than the turn-on voltage of the (n+1).sup.th TFT matrix 20.

[0034] The number of TFTs in the n.sup.th TFT matrix 10 is the same as the number of the impulse signals in the n.sup.th impulse signal set and the TFTs in the n.sup.th TFT matrix 10 and the impulse signals in the n.sup.th impulse signal set have one-to-one correspondence. That is, one impulse signal correspondingly controls one TFT. The number of TFTs in the (n+1).sup.th TFT matrix 20 is the same as the number of the impulse signals in the (n+1).sup.th impulse signal set and the TFTs in the (n+1).sup.th TFT matrix 20 and the impulse signals in the (n+1).sup.th impulse signal set have one-to-one correspondence. That is, one impulse signal correspondingly controls one TFT. Here, each TFT is correspondingly connected to a sub-pixel of an odd column or an even column. It could be understood, when there is a polarity inversion, the n.sup.th column positive data signal will become a negative data signal and the (n+1).sup.th column negative data signal will become a positive data signal. Correspondingly, the voltage level of the logic high of the n.sup.th impulse signal is lower than the turn-on voltage of the n.sup.th TFT matrix 10 and the voltage level of the logic low of the (n+1).sup.th impulse signal is higher than the turn-off voltage of the (n+1).sup.th TFT matrix 10. In this embodiment, the impulse signal has a positive period and a negative period. The high voltage level in the positive period corresponds to the logic high and the low voltage level in the negative period corresponds to the logic low. The voltage level of the logic low is negative and the turn-off voltage is also negative. The voltage level of the logic low is higher than the turn-off voltage. That is, the absolute value of the voltage level of the logic low is less than the absolute value of the turn-off voltage. Therefore, this could reduce the power consumption caused by the voltages. In this embodiment, by controlling the voltage levels of the logic high/low of the impulse signal to be lower on the basis of reliably turning on/off the TFT matrix, the waste of the voltage supplied by the impulse signal for turning on/off the TFT matrix could be reduced and thus the power consumption could be reduced as well.

[0035] Please refer to FIG. 4. FIG. 4 is a diagram of a column inversion driving circuit according to another embodiment of the present invention. As shown in FIG. 4, the n.sup.th TFT matrix comprises a first TFT T1, a second TFT T2, and a third TFT T3. The n.sup.th column positive data signal is electrically connected to the source of the first TFT T1, the source of the second TFT T2 and the source of the third TFT T3. The n.sup.th impulse signal set is electrically connected to the gate of the first TFT T1, the gate of the second TFT T2 and the gate of the third TFT T3. The drain of the first TFT T1 is electrically connected to the n.sup.th sub-pixel of an odd column. The drain of the second TFT T2 is electrically connected to the (n+1).sup.th sub-pixel of an odd column. The drain of the third TFT T3 is electrically connected to the (n+2).sup.th sub-pixel of an odd column.

[0036] The above-mentioned n.sup.th sub-pixel of an odd column, the (n+1).sup.th sub-pixel of an odd column, and the (n+2).sup.th sub-pixel of an odd column are three adjacent sub-pixels of the odd column.

[0037] As shown in FIG. 4, the n.sup.th impulse signal set comprises a first impulse signal, a second impulse signal and a third impulse signal. The first impulse signal is electrically connected to the gate of the first TFT T1, the second impulse signal is electrically connected to the gate of the second TFT T2, and the third impulse signal is electrically connected to the gate of the third TFT T3.

[0038] The n.sup.th impulse signal set correspondingly controls the on/off states of the n.sup.th TFT matrix 10.

[0039] The voltage level of the logic low of the first impulse signal is higher than the turn-off voltage of the first transistor T1. The voltage level of a logic low of the second impulse signal is higher than the turn-off voltage of the second TFT T2. The voltage level of a logic low of the third impulse signal is higher than the turn-off voltage of the third TFT T3.

[0040] When the n.sup.th column positive data signal is switched to a negative data signal, the voltage level of the logic high of the impulse signal is lower than the turn-on voltage of the corresponding TFT.

[0041] As shown in FIG. 4, the (n+1).sup.th TFT matrix 20 comprises the fourth TFT T4, the fifth TFT T5, and the sixth TFT T6. The (n+1).sup.th column negative data signal is electrically connected to the source of the fourth TFT T4, the source of the fifth TFT T5, and the source of the sixth TFT T6. The (n+1).sup.th impulse signal set is electrically connected to the gate of the fourth TFT T4, the gate of the fifth TFT T5, and the gate of the sixth TFT T6. The drain of the fourth TFT T4 is electrically connected to the n.sup.th sub-pixel of an even column. The drain of the fifth TFT T5 is electrically connected to the (n+1).sup.th sub-pixel of an even column. The drain of the sixth TFT T6 is electrically connected to the (n+2).sup.th sub-pixel of an even column.

[0042] The above-mentioned n.sup.th sub-pixel of an odd column, the (n+1).sup.th sub-pixel of an odd column, and the (n+2).sup.th sub-pixel of an odd column are three adjacent sub-pixels of the odd column.

[0043] As shown in FIG. 4, the (n+1).sup.th impulse signal set comprises a fourth impulse signal, a fifth impulse signal and a sixth impulse signal. The fourth impulse signal is electrically connected to the gate of the fourth TFT T4. The fifth impulse signal is electrically connected to the gate of the fifth TFT T5. The sixth impulse signal is electrically connected to the gate of the sixth TFT T6.

[0044] The voltage level of the logic high of the fourth impulse signal is lower than the turn-on voltage of the fourth TFT T4. The voltage level of the logic high of the fifth impulse signal is lower than the turn-on voltage of the fifth TFT T5. The voltage level of the logic high of the sixth impulse signal is lower than the turn-on voltage of the sixth TFT T6.

[0045] When the (n+1).sup.th negative data signal becomes a positive data signal, correspondingly, the voltage level of the logic low of the impulse signal is higher than the turn-off voltage of the corresponding TFT.

[0046] The n.sup.th TFT matrix 10 comprises a plurality of n-channel TFTs. But this is not a limitation of the present invention. Please note, the n.sup.th TFT matrix 10 could comprise a plurality of p-channel TFTs. In this embodiment, the voltage levels of the logic low and logic high of the impulse signal need to be adjusted accordingly to meet the needs of turning on/off the TFTs and to avoid the waste of voltages for turning on/off the TFTs.

[0047] The (n+1).sup.th TFT matrix 20 comprises a plurality of n-channel TFTs. Similarly, this is not a limitation of the present invention. Please note, the (n+1).sup.th TFT matrix 20 could comprise a plurality of p-channel TFTs. In this embodiment, the voltage levels of the logic low and logic high of the impulse signal need to be adjusted accordingly to meet the needs of turning on/off the TFTs and to avoid the waste of voltages for turning on/off the TFTs.

[0048] Please refer to FIG. 7. FIG. 7 is a diagram of a display panel according to an embodiment of the present invention. As shown in FIG. 7, a display panel is disclosed. The display panel comprises a data driver 40, a data selector 30 and a column inversion driving circuit of any of the above-mentioned embodiments. The data driver 40 is used to provide the n.sup.th column positive data signal and the (n+1).sup.th column negative data signal. The data selector 30 is used to provide the n.sup.th impulse signal set and the (n+1).sup.th impulse signal set.

[0049] The column inversion driving circuit has an advantage of reducing voltage loss. The display panel also has an advantage of reducing the power consumption.

[0050] The display panel further comprises a timing controller. The timing controller is used to control the data driver 40 and the data selector 30 to output corresponding signals at the right timings to better implement the above-mentioned embodiments.

[0051] The column inversion driving circuit could reduce the voltage waste and power consumption. The related driving method is as shown in FIG. 5a. Another MUX control signal set, including MUXR1, MUXG1, MUXB1, MUXR2, MUXG2 and MUXB2, is added to the conventional MUX1:3 control circuit. Furthermore, the positive data signals and the negative data signals are separately controlled. MUXR1, MUXG1, MUXB1 orderly control the output of the data signal D1. MUXR2, MUXG2, MUXB2 orderly control the output of the data signal D2.

[0052] As shown in FIG. 5b, for the positive data voltage D1, MUX1 signal, including MUXR1, MUXG1 and MUXB1, is determined to be periodically changed between the turn-on voltage VON and VOFF′. Here, the absolute value of VOFF′ is lower than the absolute value of turn-off voltage VOFF. When the transistor controlled by MUX1 is being turned on, Vgs is equal to VON. When the transistor controlled by MUX1 is being turned off, Vgs is the absolute value of VOFF′−X. At this time, the voltage waste ΔV is equal to the absolute value of VOFF′−X subtracting the absolute value of VOFF. This voltage waste ΔV is less than X. Thus, the voltage waste is reduced.

[0053] As shown in FIG. 5c, for the negative data voltage D2, MUX2 signal, including MUXR2, MUXG2 and MUXB2, is determined to be periodically changed between VON′ and the turn-off voltage VOFF. Here, the absolute value of VON′ is lower than the absolute value of turn-on voltage VON. When the transistor controlled by MUX2 is being turned on, Vgs is equal to VON′+X. This voltage waste ΔV is also less than X. Thus, the voltage waste is reduced.

[0054] As shown in FIG. 6a and FIG. 6b, when the display panel is refreshed to a next frame, the polarities of the data line D1 and the data line D2 are inversed. The data line D1 corresponds to a negative voltage and the data line D2 corresponds to a positive voltage. At this time, the MUX1 signal periodically changes between VON′ and VOFF and MUX2 signal periodically changes between VON and VOFF′. This reduces the voltage waste and enormously reduces the power consumption. Similarly, for the MUX1:n, the number of MUX signals becomes double for respectively controlling the positive data voltage and the negative data voltage. In addition, the voltage values also dynamically changes according to the frames.

[0055] The voltage level of VON′ could be implemented as a lower positive voltage in the current power architecture. For example, the input voltage of a power IC in a notebook is 3.3V. The input voltage of a timing controller is 1.1V or 1.8V. These voltages could be used as VON′. Similarly, the voltage level of VOFF′ could be implemented as a higher negative voltage in the current power architecture. There is no need to add another voltage converting module. This ensures that there will be other power consumption caused by any additional element.

[0056] Above are embodiments of the present invention, which does not limit the scope of the present invention. Any modifications, equivalent replacements or improvements within the spirit and principles of the embodiment described above should be covered by the protected scope of the invention.