Systems and methods for fast delta sigma modulation using parallel path feedback loops

Abstract

An error feedback system for a delta sigma modulator is disclosed. The error feedback system has an error transfer function where at least k1 coefficients are set to zero. This allows the error feedback system to be divided into k feedback paths that are performed in parallel at a clock speed that is 1/k of the system clock of the delta sigma modulator (i.e. the rate at which the output of the delta sigma modulator changes).

Claims

1. A delta sigma modulator comprising: a system clock input configured to receive a system clock signal; a delta sigma modulator input configured to receive an input signal; a delta sigma modulator output configured to provide a delta sigma modulated output; a truncator configured to generate the delta sigma modulated output based upon a sum of the input signal and an error feedback signal; an error feedback system that generates the error feedback signal, where the error feedback system comprises: k feedback paths that execute in parallel; wherein each of the k paths are clocked to 1/k clock cycles of the system clock signal and wherein k is an integer equal to or greater than two.

2. The delta sigma modulator of claim 1, wherein the error feedback system receives as an input a difference between: the sum of the input signal and an error feedback signal; and the delta sigma modulated output.

3. The delta sigma modulator of claim 2 wherein the delta sigma modulator is an N order delta sigma modulator where N is an integer equal to or greater than two.

4. The delta sigma modulator of claim 3 wherein each of the k feedback paths include N/k registers that are clocked at a rate 1/k of the system clock signal.

5. The delta sigma modulator of claim 4 wherein each of the k feedback path generates a signal that is a weighted sum of values stored in the N/k registers, where the generated signal is combined with the input to the error feedback system.

6. The delta sigma modulator of claim 4 wherein each of the k feedback path generates a signal that is a weighted sum of values stored in the N/k registers, where the generated signal is quantized by a quantizer to produce an error feedback signal.

7. The delta sigma modulator of claim 3 wherein k is less than N.

8. The delta sigma modulator of claim 1 wherein the truncator is a quantizer.

9. The delta sigma modulator of claim 1 wherein each of the k feedback paths are out of phase with each other.

10. The delta sigma modulator of claim 9 wherein each feedback path generates a separate output and the delta sigma modulator output is selected from the output of a different feedback path every clock cycle of the system clock signal.

11. A method for providing a filtered error signal for a delta sigma modulator comprising: receiving a system clock signal at a system clock input; receiving a delta sigma modulator input signal at a delta sigma modulator input; summing the input signal and an error feedback signal; truncating the sum of the input signal and an error feedback signal to produce a delta sigma modulator output signal; outputting the delta sigma modulator output signal on a delta sigma modulator output; wherein the error feedback signal is generated by an error feedback system using: k feedback paths that execute in parallel; wherein each of the k paths are clocked to 1/k clock cycles of the system clock signal and wherein k is an integer equal to or greater than two.

12. The method of claim 11, wherein the error feedback system receives as an input a difference between: the sum of the input signal and an error feedback signal; and the delta sigma modulated output.

13. The method of claim 12 wherein the delta sigma modulator is an N order delta sigma modulator where N is an integer equal to or greater than two.

14. The delta sigma modulator of claim 13 wherein each of the k feedback paths include N/k registers that are clocked at a rate 1/k of the system clock signal.

15. The method of claim 13 wherein each of the k feedback path generates a signal that is a weighted sum of values stored in the N/k registers, where the generated signal is combined with the input to the error feedback system.

16. The method of claim 13, wherein each of the k feedback path generates a signal that is a weighted sum of values stored in the N/k registers, where the generated signal is quantized by a quantizer to produce an error feedback signal.

17. The method of claim 12 wherein k is less than N.

18. The method of claim 11, wherein the truncator is a quantizer.

19. The method of claim 11 wherein each of the k feedback paths are out of phase with each other.

20. The method of claim 19 wherein each feedback path generates a separate output and the delta sigma modulator output is selected from the output of a different feedback path every clock cycle of the system clock signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates an example of delta sigma modulation used in an ADC application.

(2) FIG. 2 illustrates an example of delta sigma modulation in a DAC.

(3) FIG. 3 illustrates an example of a block diagram of an error feedback design with a 1-bit quantizer.

(4) FIG. 4 illustrates an error feedback structure.

(5) FIG. 5 illustrates an example feedback path in accordance with an embodiment of the invention.

(6) FIG. 6 illustrates the coefficients of an interpolated filter in accordance with an embodiment of the invention.

(7) FIG. 7 illustrates the frequency response of an interpolated filter with fs=5 GHz in accordance with an embodiment of the invention.

DETAILED DISCLOSURE OF THE INVENTION

(8) Turning now to the drawings, systems and methods for implementing fast delta sigma modulation using parallel feedback paths in accordance with some embodiments of the invention are described. In accordance with certain embodiments of the invention, a delta sigma modulation system includes two or more feedback paths. Each feedback path can include one or more filters in accordance with many embodiments. In accordance with many embodiments, one or more coefficients in a filter within a feedback path is set to zero. The setting of the coefficients to zero allows the calculations of the filter to be performed in parallel. In this way, the feedback signal can be generated using previous sample associated with non-zero filter coefficient. The provision of feedback paths that may be completed in parallel in accordance with many embodiments of the invention, offers several advantages over the traditional design of a delta sigma modulator. A first advantage is that the parallel computation of the feedback paths can achieve faster effective speeds than traditional designs. A second advantage is that the delta sigma modulator may no longer be limited by the device delay of any individual feedback path, which can be clocked at lower rates than the delta sigma modulator. In accordance with a number of embodiments, a third advantage is that there is no overhead for the parallelization of the feedback paths. Thus, the number of computations needed to provide the parallel feedback paths may be the same as the number of calculations needed for serial computation of multiple feedback paths with no overhead for parallelization. A fourth advantage of delta sigma modulation performed using parallel feedback paths is that very high modulation speeds or rates may be achieved with applications in areas including, but not limited to, direct-RF conversion and switched-mode power amplifiers.

(9) A description of systems and methods for performing delta sigma modulation using parallel feedbacks paths follows.

(10) Analog to Digital Conversion Using Delta Sigma Modulation

(11) Delta sigma modulation may be used to convert analog signals into digital signals. An example of delta sigma modulation system used in an ADC is illustrated in FIG. 1. One skilled in the art will appreciate that the delta sigma modulation ADC system 100 may be embodied in hardware components, software components, or any combination thereof. Furthermore, one skilled in the art will appreciate that delta sigma modulation system 100 is only a representation of a system that performs delta sigma modulation and the exact components and/or processes performed may be different in various other systems implementing delta sigma modulation.

(12) In FIG. 1, the delta sigma modulation system receives an input signal along path 110 and uses an adder component 102 to combine the input signal with an error signal 170 generated by a feedback loop described below. In accordance with many embodiments, the error signal is subtracted from the input signal to remove noise from the input signal. An integrator component 115 then receives the corrected input signal and sums the corrected input signal over a sample interval. The integrated signal 130 is then provided to ADC system 105 that compares the output 130 of integrator 115 with a reference signal to determine a digital signal 140. The digital signal 140 is provided to a 1-bit DAC system 135 that converts digital signal 140 to an analog error signal 170. Digital filter 125 receives the digital signal 140, removes quantization noise from the digital signal and provides an output digital signal 150.

(13) In FIG. 1, noise shaping can be performed by oversampling in an integrator 115 having a high pass characteristic, where the low frequency quantization noise is attenuated. The noise shaping for a particular delta sigma modulator can depend on the oversampling ratio of the low-resolution ADC clock, the input signal band of interest, and the order of the particular delta sigma modulator. The digital filter 125 can be used to remove any out of band quantization noise generated by integrator 115 and/or ADC system 105. In accordance with some embodiments, a very high resolution ADC (e.g., 12 bits or more) can be achieved using a single bit ADC running at high speed.

(14) Digital to Analog Conversion Using Delta Sigma Modulation

(15) Delta sigma modulation may also be used in a DAC application. An example of the components and/or processes of delta sigma modulation in a DAC operation are illustrated in FIG. 2. One skilled in the art will appreciate that the delta sigma modulation DAC system 200 may be embodied in hardware components, software components, or any combination thereof. Furthermore, one skilled in the art will appreciate that the delta sigma modulation DAC system 200 is only a representation of a system that performs delta sigma modulation and the exact components and/or steps performed may be different in various other systems implementing delta sigma modulation.

(16) In FIG. 2, a low frequency high-resolution (16 bits) signal may be converted from the signal encoded with a digital word into an analog signal. Instead of using a high resolution DAC for conversion, the DAC conversion is performed by a high speed, low resolution DAC 225. In system 200, the input digital signal 210 is received by interpolation filter 205 and up-sampled to high-speed signal 220. The high-speed signal 220 is modulated using a delta sigma modulator 215. The modulated signal 230 is then converted to an analog signal 240 with a one-bit DAC 22. An analog output filter 235 may then be used to remove the high frequency quantized noise due to the delta sigma modulation from the analog signal 240 to provide the output analog signal. The output analog signal may have the same quality as a signal generated using a high resolution DAC in a low frequency band of interest. However, the system 200 using a delta sigma modulator may be much cheaper than systems with a high precision DAC. Typically, the feedback structure is used for delta sigma operation in DAC conversion since there is no mismatch in the digital implementation.

(17) Error Feedback Loop in a Delta Sigma Modulator

(18) There are many different delta sigma modulator implementations that have different architectures. The exact architecture of a delta sigma implementation depends on factors including, but not limited to, the oversampling ratio of the low-resolution ADC clock, the input signal band of interest, and the order of the delta sigma modulator implementation. However, delta sigma implementations typically include an error feedback structure. An example of a block diagram components and/or processes of an error feedback design of a delta sigma modulator with a 1-bit quantizer in accordance with an embodiment of the invention is illustrated in FIG. 3. One skilled in the art will recognize that only the components of a delta sigma modulator 300 necessary for understanding the error feedback path are shown in FIG. 3. Furthermore, the components and/or processes illustrated in FIG. 3 may be implemented by hardware components, software components, or any combination thereof.

(19) As illustrated in FIG. 3, delta sigma modulator 300 includes an adder component 305 that receives a delta sigma modulator input signal 310 and a filtered error signal 350. The input signal 310 and the filtered error signal 350 are combined by the adder component 305 to output a corrected input signal 330. The corrected input signal is received by a 1-bit truncator component 315 and an adder component 325. The 1-bit truncator component 315 generates the delta sigma modulator output signal 320 that is provided as an output and is received by adder component 325. The adder component 325 combines the corrected input signal and the output signal to generate an error signal 340. H.sub.e 335 is an error feedback transfer function. The quantizer error may be calculated and filtered by the error feedback transfer function H.sub.e 335 from the error signal to generate the filtered error signal. The filtered error signal is provided to adder component 305 to be summed with the delta sigma modulator input signal 310 for quantization.

(20) Despite the many advantages that a delta sigma modulator can offer, conventional delta sigma modulators are considered to experience speed limitation due to the feedback loop. The quantized error in a conventional delta sigma signal is calculated at every clock cycle and then used to calculate the next quantizer input. Thus, the speed of the delta sigma modulator is limited by the delay of the feedback path calculation. This delay may depend on the feedback transfer function complexity and the transistor delay. As a result, conventional delta sigma modulators are typically limited to a few hundred MHz. However, there are applications such as switched-mode PAs that utilize delta sigma modulators that operate at rates approaching or exceeding several GHz. Accordingly, many embodiments of the invention implement a feedback structure that can enable operation of a delta sigma modulator at higher rates, as described in detail below.

(21) Very Fast Delta Sigma Modulator Implementation

(22) Many embodiments of the invention increase the speed of the feedback structure of a delta sigma modulator. In accordance with many embodiments of the invention, the speed of the error structure is increased by using parallel error feedback paths. In accordance with a number of embodiments, the use of parallel feedback paths is provided by using zero coefficients in one or more filters in one or more of the parallel feedback paths. In particular, many embodiments of error feedback paths of delta sigma modulators, such as the error feedback path shown in FIG. 3, implement the z-transform of the signal in error feedback path as follows:

(23) V(z) is the delta sigma modulator output;

(24) U(z) is the delta sigma modulator input;

(25) E(z) is the quantization error;

(26) Using the above definitions, the delta sigma modulator can be expressed by the following equation:
U(z)H.sub.e(z)E(z)V(z)=E(z)

(27) The above equation can be rearranged as follows:
V(z)=U(z)+E(z)(1H.sub.e(z))

(28) The signal transfer function, STF(z)=1, defines the input-output signal relationship. The noise transfer function, NTF(z)=(1H.sub.e (z)), defines the output noise and quantization noise relationship. As such, the NTF(z) determines the noise shaping and can be expressed in an infinite impulse filter (IIR) form where N is the order of the filter as follows:

(29) $\mathrm{NTF}\left(z\right)=\frac{B\left(z\right)}{A\left(z\right)}=\frac{1+{}_1{z}^{-1}+{}_2{z}^{-2}+\mathrm{.Math.}+{}_N{z}^{-N}}{1+{}_1{z}^{-1}+{}_2{z}^{-2}\mathrm{.Math.}+{}_N{z}^{-N}}$

(30) The error feedback transfer function H.sub.e (z) can be expressed in terms of NFT(z) as follows:

(31) $H_e\left(z\right)=1-\mathrm{NTF}\left(z\right)=\frac{\left({}_1-{}_1\right)z^{-1}+\left({}_2-{}_2\right)z^{-2}+\mathrm{.Math.}+\left({}_N-{}_N\right)z^{-N}}{1+{}_1{z}^{-1}+{}_2{z}^{-2}\mathrm{.Math.}+{}_N{z}^{-N}}$

(32) An implementation of an error feedback path having an N order filter for a delta sigma modulation system is shown in FIG. 4. One skilled in the art will recognize that only the components of a delta sigma modulator necessary for understanding an N order error feedback path are shown in FIG. 4. Furthermore, the components and/or processes illustrated in FIG. 4 may be implemented by hardware components, software components, or any combination thereof.

(33) An N order filter 400 for a delta sigma modulator is shown in FIG. 4. The N order filter 400 receives an input error signal, e(n), in adder component 405 that adds the input error signal with the response of the N order filter. The corrected input error signal is accumulated in a delay line of N registers 415 that forms the N order filter. Each of the N registers 415 provides the corrected input error signal to a first error filter component 425 and a second error filter component 435. Each of the nth order first error filter components 425 multiplies the corrected error signal in a given register n by a coefficient, .sub.n. The weighted outputs of each of the N registers is then combined by the adder components 406 to form the denominator of feedback transfer function H.sub.e (z). The second error filter components 435 receive the corrected input signal from each of the N registers 415 and multiply the corrected input signal from a given register n by a coefficient, .sub.n-.sub.n. The weighted accumulated corrected input error signals are then combined by the adders 455 to generate the numerator of the feedback transfer function H.sub.e (z). As noted above, all of the computations can be performed in parallel during each clock cycle as the calculation of the filter output simply requires generation of the weighted sum of the accumulated corrected input error signals.

(34) Adder component 455 receives the signal corresponding to the numerator of the transfer function and a delta sigma modulator inputs signal, u(n), via an input and adds the signals to generate an adjusted reference signal. The output signal from adder component 455 is provided to a quantizer 475. Quantizer 475 generates a quantized signal that is provided as a delta sigma modulator output, v(n), via an output. The quantizer output is also provided to the adder component 465. The adder component 465 subtracts the adjusted reference signal and the quantized signal from quantizer 475 to generate an error signal. When each of the N registers is clocked by the system clock of the delta sigma modulator, the corrected input signal stored in a given register is shifted to an adjacent register (e.g. the corrected input signal stored in register n is shifted to register n+1). In the illustrated embodiment, the rate of the delta sigma modulator can be limited by the rate at which the delay line can be clocked.

(35) As can be seen from FIG. 4, all of the registers from the N orders of the error feedback path are clocked at the same speed as the delta sigma modulator. Accordingly, all operations in the feedback path are completed in one clock cycle. The feedback path is the critical path in this design that can limit the maximum speed of the delta sigma modulator.

(36) Parallel Error Feedback Paths in a Delta Sigma Modulator

(37) In light of the fact that the error feedback path limits the maximum speed of a delta sigma modulator, the speed of the error feedback path needs to be improved in order to increase the speed of the modulator. In accordance with some embodiments of the invention, the speed of the error feedback path in a delta sigma modulator is improved by uncoupling the error feedback path from the clock speed of the modulator. In accordance with many embodiments, the uncoupling is achieved by setting one or more filter coefficients to zero. In accordance with a number of embodiments, the setting of one or more filter coefficients to zero allows the use of two or more parallel feedback error paths in a delta sigma modulator that can perform calculations more slowly than the rate of the delta sigma modulator. In accordance with several of the embodiments, the first K coefficients of the filter are set to zero allowing K error feedback paths to compute the error in parallel. This can improve the speed of the error feedback paths by at least K times the clock speed.

(38) A feedback loop filter in a delta sigma modulator where both .sub.1 and .sub.1 are zero for use in an error feedback circuit having parallel error feedback paths in accordance with an embodiment of the invention is illustrated in FIG. 5. The fact that .sub.1 and .sub.1 of the filter are zero translates into an implementation in which a feedback path simply does not include circuitry necessary to connected the register containing the most recently stored value to the circuitry used to calculate the error feedback path. The circuitry of the parallel feedback paths is discussed further below.

(39) The feedback loop filter 500 is divided into 2 parallel delay lines 510, 511 running at half () of the clock rate, where the registers in each of the delay lines accumulate N/2 corrected input error signals and the values are shifted between registers every two clock cycles. The output of a given register n is scaled by a number of different coefficients 521 and two weighted sums are formed by adder components 509. Each of the weighted sums is combined with the appropriate error signal e(n) and e(n+1) to create the corrected input error signals provided to each of the delay lines respectively.

(40) Similarly, weightings 526 can be applied to the corrected input error signals in each of the delay lines and added using adder components 531, 532 to form the numerator of the feedback transfer function H.sub.e (z) at each clock time interval and the resulting value utilized to generate an error feedback signal that is combined with the delta sigma input (u(n), u(n+1)) and quantized using quantizers 540, 555 to produce the delta sigma modulator output (v(n), v(n+1)). The output selected as the delta sigma modulator output alternates each clock cycle. Each of the two output signals adjusts once per two clock cycles; the adjustments occurring out of step with each other by one clock cycle. Adder components 535, 545, 540, 550 subtract the quantized outputs from the sums of the delta sigma modulator input signals and the error feedback signals to produce the next error signal (e(n), e(n+1)).

(41) The effective speed of a delta sigma modulator utilizing a feedback filter similar to that illustrated in FIG. 5 may double (2) relative to the speed with which individual calculations can be performed within the feedback loop filter. This approach may be extended to zeroing out the first k1 coefficients and achieving a k times speed increase by providing k parallel paths that each operate at a 1/k clock rate. Although FIG. 5 illustrates the error feedback of a delta sigma modulator divided into two parallel paths, other implementations in accordance with some other embodiments may utilize more than two parallel paths in order to further reduce the clock delay of the feedback loop and thus increase the speed of the delta sigma modulator.

(42) The architecture utilized by many embodiments of the invention achieves speed improvement by placing constraints on the delta sigma modulator filter coefficients. In particular, many embodiments constrain some filter coefficients to be zero so parallel implementation of the feedback paths that are clocked by clock signals that have lower clock rates that the rate at which the delta sigma modulator output changes its output value is possible. There are many ways to achieve the desired noise shaping response and meeting this filter coefficient constraint at the same time. Some embodiments use an interpolated FIR or IIR filter for the noise shaping transfer function. The interpolated filter may have a special property for its coefficients. The coefficients of an interpolated filter are shown in FIG. 6. As can be seen from FIG. 6, one of the six coefficients is non zero with the remaining coefficient being zero. In such an embodiment, a six times increase of the output speed may be achieved. The frequency response of an interpolated filter with a sampling frequency F.sub.s=5 GHz is shown in FIG. 7. In the interpolated filter described by FIG. 7, the actual hardware speed is of F.sub.s due to parallelization that is easily achievable using today's technology. Many embodiments can thus achieve k times speed improvement using an interpolated filter with order N in which the first k1 coefficients are zero by providing k parallel feedback paths operating at 1/k the clock rate of the delta sigma modulator. Certain embodiments design the transfer function using an optimization algorithm (linear programming, quadratic programming, and convex programming) with zero filter coefficients in selected locations.

(43) Although the present invention has been described in certain specific aspects, many additional modifications and variations would be apparent to those skilled in the art. It is therefore to be understood that the present invention may be practiced otherwise than specifically described, including various changes in the implementation. Thus, embodiments of the present invention should be considered in all respects as illustrative and not restrictive.