Abstract
An optoelectronic semiconductor component and a method for producing optoelectronic semiconductor components are disclosed. In an embodiment a optoelectronic semiconductor component includes a plurality of semiconductor pillars, each pillar having a tip and a base region at opposite ends, an electrical isolation layer surrounding at least part of the semiconductor pillars on side faces and at least one first electrical contact pad and at least one second electrical contact pad for energizing the semiconductor pillars, wherein a first portion of the semiconductor pillars are emitter pillars configured to generate radiation, wherein a second portion of the semiconductor pillars are non-radiating electrical contact pillars, wherein the contact pillars extend through the isolation layer such that all contact pads are located on the same side of the isolation layer, and wherein each contact pillars is coated with an electrically ohmically conductive outer layer.
Claims
1. An optoelectronic semiconductor component comprising: a plurality of semiconductor pillars, each pillar having a tip and a base region at opposite ends, wherein the semiconductor pillars comprise emitter pillars configured to generate radiation and non-radiating electrical contact pillars; an electrical isolation layer surrounding at least part of the semiconductor pillars on side faces; at least one first electrical contact pad and at least one second electrical contact pad for energizing the semiconductor pillars; and at least one current distribution layer located on a side of the electrical isolation layer opposite the first and second contact pads, the current distribution layer configured to provide an electrical connection between at least one of the contact pillars and at least one of the emitter pillars, wherein the semiconductor pillars extend through the electrical isolation layer such that the first and second contact pads are located on the same side of the electrical isolation layer, wherein the tip of each of the contact pillars is coated with an electrically ohmically conductive outer layer, wherein, for each current distribution layer, the electrically ohmically conductive outer layer is arranged between the current distribution layer and the tip of the at least one of the contact pillars so that the current distribution layer is in direct contact with the electrically ohmically conductive outer layer and the tip of the at least one of the emitter pillars facing the current distribution layer, and wherein the electrical isolation layer is arranged laterally between the side faces of the emitter pillars and side faces of the electrically ohmically conductive outer layer coated on the contact pillars.
2. The optoelectronic semiconductor component according to claim 1, wherein the at least one of the emitter pillars are arranged rotationally symmetrically around the at least one of the contact pillars, when viewed from above.
3. The optoelectronic semiconductor component according to claim 1, wherein the electrically ohmically conductive outer layer comprises a metallic layer impermeable to the radiation.
4. The optoelectronic semiconductor component according to claim 3, wherein the current distribution layer is permeable to the radiation, and wherein a thickness of the current distribution layer is between 10 nm and 0.4 μm inclusive.
5. The optoelectronic semiconductor component according to claim 1, wherein the radiation of the emitter pillars is configured to exit the optoelectronic semiconductor component through the current distribution layer.
6. The optoelectronic semiconductor component according to claim 1, wherein the emitter pillars and the contact pillars are identical except for the electrically ohmically conductive outer layer.
7. The optoelectronic semiconductor component according to claim 1, wherein the electrically ohmically conductive outer layer protrude into the current distribution layer.
8. The optoelectronic semiconductor component according to claim 1, wherein the electrical isolation layer is a cured silicone.
9. The optoelectronic semiconductor component according to claim 1, wherein the electrical isolation layer is a cured thermoplastic.
10. The optoelectronic semiconductor component according to claim 1, wherein the optoelectronic semiconductor component accommodates up to 30 contact pillars per μm.sup.2.
11. The optoelectronic semiconductor component according to claim 1, wherein a height of the current distribution layer is not more than 20% of a mean height of the semiconductor pillars.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) In the following an optoelectronic semiconductor component described herein and a method described herein are explained in more detail with reference to the drawing and on the basis of exemplary embodiments. Identical reference signs indicate identical elements in the individual figures. The represented elements are not shown true to scale, however; rather, individual elements can be represented in exaggerated size for improved comprehension.
(2) In the drawings:
(3) FIGS. 1A to 1J show schematic sectional drawings of method steps of a method described here for producing exemplary embodiments of optoelectronic semiconductor components,
(4) FIG. 1K shows a schematic bottom view of an exemplary embodiment of an optoelectronic semiconductor component described here,
(5) FIG. 2 shows a perspective plan view of an exemplary embodiment of an optoelectronic semiconductor component described here,
(6) FIGS. 3A and 3B show schematic sectional views of semiconductor pillars for exemplary embodiments of optoelectronic semiconductor components,
(7) FIG. 4 shows a schematic sectional view of an exemplary embodiment of an optoelectronic semiconductor component described here,
(8) FIG. 5 shows a perspective plan view of an exemplary embodiment of an optoelectronic semiconductor component described here,
(9) FIGS. 6A and 6C show schematic sectional drawings of method steps of a method described here for producing exemplary embodiments of optoelectronic semiconductor components,
(10) FIGS. 6B and 6D show schematic bottom views and schematic plan views of exemplary embodiments of optoelectronic semiconductor components described here,
(11) FIG. 7 shows a perspective plan view of an exemplary embodiment of an optoelectronic semiconductor component described here, and
(12) FIG. 8 shows a schematic sectional view of an exemplary embodiment of an optoelectronic semiconductor component described here, mounted on a carrier.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
(13) FIG. 1 illustrates a production process for an optoelectronic semiconductor component. FIG. 1A shows that a plurality of semiconductor pillars 3 are epitaxially grown on a growth substrate 70. Optionally, a growth layer 74 is located on the growth substrate 70. A mask layer 71, which has base openings 72, is also present on the growth layer 74. The semiconductor pillars 3 grow out of the base openings 72. For example, the mask layer 71 is a silicon nitride layer, in which the base openings 72 are generated, preferably by photolithography.
(14) The semiconductor pillars 3 each preferably have a semiconductor core 31 and a semiconductor shell 33. An active zone, not drawn in FIG. 1A, is located between them. All semiconductor pillars 3 are grown identically within the manufacturing tolerances.
(15) FIG. 1B illustrates that a metallic outer layer 43 is produced over some of the semiconductor pillars 3. The outer layer 43 is ohmically conductive. The outer layer 43, having a thickness of 0.5 μm for example, can completely envelop the associated semiconductor pillars 3 which are provided for contact pillars 4. Semiconductor pillars 3 provided as emitter pillars 5 remain free of such outer layers 43. Mask layers used during manufacture are not drawn, in order to simplify the illustration.
(16) In addition, FIG. 1B shows as an option that the base openings 72 in the mask layer for the contact pillars 4 are enlarged to form expansion openings 73. If such an enlargement is made to the expansion openings 73, the outer layer 43 can be in contact with the growth substrate 70 or the growth layer 74 and, in particular, can penetrate the mask layer 71 completely. In this variant, it is possible to use the same photomask, not drawn, for creating the extension openings 73 and the outer layers 43.
(17) In the step of FIG. 1C an intermediate carrier 75 is provided. The intermediate carrier 75 contains a raw material layer 21, made of a silicone or a thermoplastic, for example. The raw material layer 21 is comparatively soft.
(18) The semiconductor pillars 3 with the outer layers 43 are pressed into the raw material layer 21, whereupon the raw material layer 21 is cured to form an isolation layer 2. This is shown in FIG. 1D. The outer layers 43 can touch the intermediate carrier 75 or else, other than shown in FIG. 1D, they can remain spaced apart from the intermediate carrier 75 by a part of the isolation layer 2.
(19) FIG. 1E illustrates that the growth substrate 70 has been detached. The growth layer 74 is also preferably removed. From the growth layer 74, broken-off regions 38 can remain on the semiconductor pillars 3.
(20) If no expansion openings 73 are created in the step of FIG. 1B, then in the step of FIG. 1E a side facing away from the intermediate carrier 75 is essentially formed entirely by the mask layer 71 and by the broken-off regions 38 optionally protruding from the mask layer 71. The broken-off regions 38 and thus the base openings 72 correspond essentially to a diameter of the semiconductor cores 31.
(21) FIG. 1F, on the other hand, illustrates that the expansion openings 73 can be produced after the growth substrate 70 has been removed. This production of the expansion openings 73 of FIG. 1F is an alternative to the process step as illustrated in FIG. 1B.
(22) The expansion openings 73 can terminate flush with the outer layers 43 in the lateral direction, so that in the case of the contact pillars 4, both the entire semiconductor pillars 3 as well as the associated outer layers 43 are partially or preferably completely free of the mask layer 71. In the step of FIG. 1F there is no change to the mask layer 71 on the emitter pillars 5.
(23) Optionally, the broken-off regions 38 at least on the contact pillars 4 can be removed, see FIG. 1G.
(24) FIG. 1G also illustrates that metallisations 45 are produced on each of the contact pillars 4. The metallisation 45 can be formed from a single layer or else, unlike in the drawing, from a plurality of layers. As an alternative to metallisations, electrically conductive, transparent oxide layers can also be used.
(25) FIG. 1H shows that the broken-off regions 38 are still present both on the contact pillars 4 and the emitter pillars 5. A number of the emitter pillars 5 are electrically connected to the associated contact pillar 4 via a current distribution layer 44. The current distribution layer 44 is preferably radiation-permeable, for example made from ITO. The current distribution layer 44 is electrically connected to the metallization 45 and thus to the outer layer 43 and to the semiconductor cores 31 of the associated emitter pillars 5, but not to the active zone or the semiconductor shells 33 thereof.
(26) According to FIG. 1I, a carrier 77 is attached and the intermediate carrier 75 has been removed. The carrier 77 can be a temporary carrier or a permanent carrier. The carrier 77 is preferably radiation-permeable.
(27) According to FIG. 1J, on a side of the isolation layer 2 facing away from the carrier 77, first electrical contact pads 41 are produced on the emitter pillars 5 and second electrical contact pads 42 are produced on the contact pillars 4. The contact pads 41, 42 are produced galvanically, for example. The contact pads 41, 42 can also be formed from one or more metal layers, alternatively from transparent conductive oxides.
(28) FIG. 1J also illustrates that a radiation R generated during operation is emitted through the carrier 77 and through the current distribution layers 44. The contact pillars 4 also provide an electrical subdivision into groups 55 of emitter pillars 5 with the associated contact pillar 4. In contrast to the example shown, for redundancy reasons a plurality of the contact pillars 4 can also be present per group 55.
(29) Finally, it can be seen from FIG. 1J that the isolation layer 2 is optionally reduced in thickness so that, for example, the semiconductor pillars 3 for the contact pillars 4 can project out of the isolation layer 2. The same can also apply to the emitter pillars 5, in contrast to the illustration of FIG. 1J. In contrast to the drawing in FIG. 1J, it is also possible that emitter pillars 5 are merely exposed and not reduced in height.
(30) FIG. 1K shows a closer view of the contact pads 41, 42 of the semiconductor component 1 of FIG. 1J. For example, four of the emitter pillars 5 are arranged point-symmetrically around the centrally positioned contact pillar 4.
(31) The exemplary embodiment of FIG. 2 shows that eight of the emitter pillars 5 are assigned to one of the contact pillars 4. Different groups can be formed, for example groups 55R for generating red light, groups 55G for generating green light, and groups 55B for generating blue light. Accordingly, color-emitting groups 55R, 55G, 55B can be grouped into a pixel 6.
(32) Red, green and blue light is produced either directly by the semiconductor pillars 3 themselves or, specifically for red and green light, by a fluorescent material, not shown in FIG. 2, which may be contained in the carrier 77, for example, and/or which is applied to the current distribution layers 44. A corresponding fluorescent or fluorescent materials may be present in the same way in all exemplary embodiments.
(33) Unlike in the illustration in FIG. 2, it is possible that no subdivision is made into dedicated groups, so that a two-dimensional light source without internal subdivision is provided. In this case, for example, a two-dimensionally applied, continuous fluorescent material is present, for producing white light together with blue light, for example.
(34) FIG. 3A shows that in addition to the semiconductor core 31, the active zone 32 and the semiconductor shell 33, the semiconductor pillars 3 can also have an energization layer 34, for example made of a metal or a transparent conductive oxide. Only the semiconductor cores 31 are in contact with the growth layer 74. In addition, isolation is provided by the mask layer 71. The semiconductor pillars 3 have a marked peak 35.
(35) On the other hand, the semiconductor pillars 3 of FIG. 3B are flat at the tip 35. It is possible that the layers 32, 33 do not extend as far as the mask layer 71.
(36) Such semiconductor pillars 3 can be used in all exemplary embodiments.
(37) FIG. 4 illustrates that all semiconductor pillars 3 are identically designed in respect of the components 31, 32, 33, 34. Due to the energization layer 34, it is possible that the energization layer 34 is identical to the outer layer 43 of the contact pillars 4. This provides an electrical cross-connection via the current distribution layer 44, which electrically connects the relevant energization layers 34 of the associated contact pillars 4 and emitter pillars 5 together.
(38) It is also illustrated that in the case of the contact pillars 4, the components 31, 32, 33, 34 are directly connected to the second contact pad 42 due to the extension opening 73.
(39) FIG. 5 illustrates that the contact pads 41, 42 do not necessarily completely cover and/or extend beyond the semiconductor pillars 3. Thus, the contact pads 41, 42 according to FIG. 5 are primarily located on the side faces 37, so that the semiconductor pillars 3 can extend beyond the two-dimensional contact pads 41, 42.
(40) FIG. 6 illustrates another production method for the semiconductor components 1. The method step of FIG. 6A is based in particular on the step of FIG. 1F.
(41) Both the first and second contact pads 41, 42 are produced on the side of the isolation layer 2 facing away from the intermediate carrier 75. The mask layer, not drawn, is preferably designed in accordance with FIG. 1.
(42) FIG. 6B shows that the second contact pad 42, seen in plan view, is enclosed by the first contact pad 41, separated by an annular-shaped area of the isolation layer 2. Otherwise, FIG. 6B is identical to FIG. 1K.
(43) According to FIG. 6C, after the intermediate carrier 75 has been removed the current distribution layer 44, which is radiation-permeable, is produced. The contact tips 46 of the outer layer 43 preferably each protrude into the current distribution layer 44. All semiconductor pillars 3 can have the same height.
(44) FIG. 6D illustrates a plan view corresponding to FIG. 6C.
(45) As shown in FIG. 7, it is possible that the current distribution layer 44 can be confined to the side surfaces 37 of the semiconductor pillars. This allows the semiconductor pillars 3 to extend beyond the current distribution layer 44, unlike the case shown in FIG. 6. In addition, this allows a radiation characteristic to be set by shaping, for example, the tips 35 of the emitter pillars 5.
(46) FIG. 8 shows that the semiconductor component 1 of FIG. 6C, for example, is mounted on an external carrier 77. An electrical connection is made via electrical connecting means 78, for example solder balls. Electrical conductor tracks 79a, 79b can be used to implement electrical activation of the contact pillars 4 and the emitter pillars 5. The emitter pillars 5 can be combined into groups 55, which can preferably be electrically activated independently of each other.
(47) As an alternative to solder balls, planar layers such as electroplated layers, or cylindrical structures such as so-called pillars, can also be used for the connecting means 78.
(48) A suitable interconnection in the carrier 77 enables a display with a high resolution, in particular pixel-precise, to be implemented. For example, the carrier 77 is then an IC, a microcontroller or an application-specific IC. Each first and/or second electrical contact pad 41, 42 can therefore be assigned its own switching element in the carrier 77 for targeted and mutually independent energization.
(49) The arrangement with the semiconductor pillars 3 can also be applied electrically, in particular soldered, in a planar manner on a re-wiring carrier as an extremely thin layer, only electrically connected by the annular contacts or contact pillars 4. The light-active layer then consists of the thin single pixels on the re-wiring carrier.
(50) The components shown in the figures, unless otherwise indicated, preferably follow one another directly in the specified sequence. Layers that do not touch each other in the figures are preferably spaced apart from each other. Where lines are drawn parallel to each other, the corresponding surfaces are preferably also oriented parallel to each other. Also, unless otherwise indicated, the relative positions of the drawn components with respect to one another are reproduced correctly in the figures.
(51) The invention described here is not limited by the description based on the exemplary embodiments. Rather, the invention comprises each new feature, as well as any combination of features, which includes in particular every combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.
