Non-inverting amplifier circuits

Abstract

Amplifier circuits comprising an input transistor, a load transistor, and a feedback resistor. In one example, one embodiment is directed to an amplifier circuit comprising an input transistor, a load transistor having a control terminal and a reference terminal, and a feedback transistor. The input transistor receives an input signal, the input transistor is electrically coupled to the load transistor and the feedback transistor, the control terminal of the load transistor is electrically coupled to a bias voltage, the feedback transistor is electrically coupled to the load transistor providing negative feedback, and the reference terminal of the load transistor serves as an output of the amplifier circuit.

Claims

1. A non-inverting amplifier circuit providing a voltage gain comprising: an input transistor; a load transistor having a control terminal and a reference terminal; and a feedback transistor; wherein: the input transistor receives an input signal; the input transistor is electrically coupled to the load transistor and the feedback transistor; the control terminal of the load transistor is electrically coupled to a bias voltage; the feedback transistor is electrically coupled to the load transistor providing negative feedback; the reference terminal of the load transistor serves as an output of the amplifier circuit; the input transistor is a MOS transistor; and the load transistor is a MOS transistor having a gate and a source, the gate corresponding to the control terminal and the source corresponding to the reference terminal.

2. The circuit of claim 1, wherein the feedback transistor has a higher threshold voltage than the load transistor.

3. A non-inverting amplifier circuit providing a voltage gain comprising: an input transistor; a load transistor having a control terminal and a reference terminal; and a feedback transistor; wherein: the input transistor receives an input signal; the input transistor is electrically coupled to the load transistor and the feedback transistor; the control terminal of the load transistor is electrically coupled to a bias voltage; the feedback transistor is electrically coupled to the load transistor providing negative feedback; the reference terminal of the load transistor serves as an output of the amplifier circuit; the input transistor is a bipolar transistor; and the load transistor is a bipolar transistor having a base and an emitter, the base corresponding to the control terminal and the emitter corresponding to the reference terminal.

4. A non-inverting amplifier circuit providing a voltage gain comprising: an input transistor; a load transistor having a control terminal and a reference terminal; a feedback transistor; and a current source electrically coupled to the input transistor, the current source increasing the current through the input transistor; wherein: the input transistor receives an input signal; the input transistor is electrically coupled to the load transistor and the feedback transistor; the control terminal of the load transistor is electrically coupled to a bias voltage; the feedback transistor is electrically coupled to the load transistor providing negative feedback; and the reference terminal of the load transistor serves as an output of the amplifier circuit.

5. The circuit of claim 4, wherein the input transistor is a MOS transistor.

6. The circuit of claim 5, wherein the load transistor is a MOS transistor having a gate and a source, the gate corresponding to the control terminal and the source corresponding to the reference terminal.

7. The circuit of claim 6, wherein the feedback transistor has a higher threshold voltage than the load transistors.

8. A non-inverting amplifier circuit providing a voltage gain comprising: an input transistor; a load transistor having a control terminal and a reference terminal; a feedback transistor; and a level shifting circuit electrically coupled to the feedback transistor and the load transistor; wherein: the input transistor receives an input signal; the input transistor is electrically coupled to the load transistor and the feedback transistor; the control terminal of the load transistor is electrically coupled to a bias voltage; the feedback transistor is electrically coupled to the load transistor providing negative feedback; and the reference terminal of the load transistor serves as an output of the amplifier circuit.

9. The circuit of claim 8, wherein the level shifting circuit comprises a capacitor charged to a predetermined voltage.

10. The circuit of claim 8, wherein the level shifting circuit comprises a MOS transistor and a current source.

11. The circuit of claim 8, wherein the level shifting circuit comprises a resistor and a current source.

12. A differential amplifier circuit providing a voltage gain comprising: a first input transistor; a second input transistor; at least one load transistor having a control terminal and a reference terminal; and at least one feedback transistor; wherein: the first and the second input transistors receive an input signal; the first input transistor is electrically coupled to the at least one load transistor and the at least one feedback transistor; the control terminal of the at least one load transistor is electrically coupled to a bias voltage; the at least one feedback transistor is electrically coupled to the at least one load transistor providing negative feedback; the reference terminal of the at least one load transistor serves as an output of the amplifier circuit; the input transistors are MOS transistors; and the at least one load transistor is a MOS transistor having a gate and a source, the gate corresponding to the control terminal and the source corresponding to the reference terminal.

13. The circuit of claim 12, wherein the at least one feedback transistor has a higher threshold voltage than the at least one load transistor.

14. A differential amplifier circuit providing a voltage gain comprising: a first input transistor; a second input transistor; at least one load transistor having a control terminal and a reference terminal; and at least one feedback transistor; wherein: the first and the second input transistors receive an input signal; the first input transistor is electrically coupled to the at least one load transistor and the at least one feedback transistor; the control terminal of the at least one load transistor is electrically coupled to a bias voltage; the at least one feedback transistor is electrically coupled to the at least one load transistor providing negative feedback; the reference terminal of the at least one load transistor serves as an output of the amplifier circuit; the input transistors are bipolar transistors; and the at least one load transistor is a bipolar transistor having a base and an emitter, the base corresponding to the control terminal and the emitter corresponding to the reference terminal.

15. A differential amplifier circuit providing a voltage gain comprising: a first input transistor; a second input transistor; at least one load transistor having a control terminal and a reference terminal; at least one feedback transistor; and a positive feedback transistor electrically coupled to the at least one load transistor and the at least one feedback transistor, the positive feedback transistor providing positive feedback to increase the voltage gain; wherein: the first and the second input transistors receive an input signal; the first input transistor is electrically coupled to the at least one load transistor and the at least one feedback transistor; the control terminal of the at least one load transistor is electrically coupled to a bias voltage; the at least one feedback transistor is electrically coupled to the at least one load transistor providing negative feedback; the reference terminal of the at least one load transistor serves as an output of the amplifier circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and/or structurally similar elements).

(2) FIG. 1 (prior art) provides an illustration of a prior art common-source amplifier.

(3) FIG. 2 (prior art) provides an illustration of a prior art common-gate amplifier.

(4) FIG. 3 (prior art) provides an illustration of a prior art source-coupled amplifier.

(5) FIG. 4A illustrates an example of an amplifier according to one embodiment of the present invention with an NMOS input transistor and PMOS load and feedback transistors.

(6) FIG. 4B illustrates an example of an amplifier according to another embodiment of the present invention with an NMOS input transistor, PMOS load and feedback transistors, and a current source.

(7) FIG. 5A illustrates an example of an amplifier according to another embodiment of the present invention, which further includes a level shifting circuit implemented using a capacitor pre-changed to a predetermined voltage.

(8) FIG. 5B illustrates an example of an amplifier according to another embodiment of the present invention, which further includes a level shifting circuit implemented by a PMOS transistor and a current source.

(9) FIG. 5C illustrates an example of an amplifier according to another embodiment of the present invention, which further includes a level shifting circuit implemented by a resistor and a current source.

(10) FIG. 6 illustrates an example of an amplifier according to another embodiment of the present invention, with a PMOS input transistor and NMOS load and feedback transistors.

(11) FIG. 7 illustrates an example of an amplifier according to another embodiment of the present invention, with an NMOS input transistor and NMOS load and feedback transistors.

(12) FIG. 8 illustrates an example of an amplifier according to another embodiment of the present invention, with an NPN input transistor and PNP load and feedback transistors.

(13) FIG. 9A illustrates an example of an amplifier according to another embodiment of the present invention, with an NPN input transistor and PNP load and feedback transistors, further including a level shifting circuit implemented by a resistor and a current source.

(14) FIG. 9B illustrates an example of an amplifier according to another embodiment of the present invention, with an NPN input transistor and PNP load and feedback transistors, further including a level shifting circuit implemented by an NPN transistor and a current source.

(15) FIG. 9C illustrates an example of an amplifier according to another embodiment of the present invention, with an NPN input transistor and PNP load and feedback transistors, further including a level shifting circuit implemented by an VBE multiplier.

(16) FIG. 10 illustrates an example of a differential amplifier according to another embodiment of the present invention with an NMOS input transistors and PMOS load and feedback transistors.

(17) FIG. 11 illustrates an example of a differential amplifier according to another embodiment of the present invention with an NMOS input transistors, PMOS load and feedback transistors and positive feedback gain enhancement.

DETAILED DESCRIPTION

(18) Following below are more detailed descriptions of various concepts related to, and embodiments of, inventive apparatus relating to amplifier circuits. It should be appreciated that various concepts introduced above and discussed in greater detail below may be implemented in any of numerous ways, as the disclosed concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

(19) FIG. 1 provides an illustration of a prior art CS amplifier circuit 20 with a load resistor R.sub.L and a source resistance R.sub.S. In this amplifier circuit, the incremental gain is shown to be:
a.sub.vg.sub.m1R.sub.L(1)
where g.sub.m1 is the transconductance of the input transistor M1. As indicated by the minus sign, the incremental gain is negative, thus this amplifier provides inverting amplification. The input impedance at low frequencies is infinite, a desirable property for many applications.

(20) The output resistance of the amplifier 20 is approximately the same as the load resistor R.sub.L:
R.sub.oR.sub.L(2)
Therefore, the CS amplifier's gain will be reduced if any resistive load is presented at the output. For example, if load resistance R.sub.1 is attached between the output and the incremental ground, the corresponding incremental gain is reduced to
a.sub.vg.sub.m1(R.sub.LR.sub.1)(3)
where (R.sub.LR.sub.1) is the equivalent resistance of R.sub.L in parallel with R.sub.1. Thus, unless R.sub.1 is much larger than R.sub.L, the incremental gain is substantially reduced.

(21) Often, the power supply rejection ratio is an important consideration, especially for system-on-a-chip applications. The power supply rejection ratio (PSRR) of the amplifier in FIG. 1 is shown to be approximately same as the incremental gain because the power supply noise couples to the output without attenuation:
PSRRg.sub.m1R.sub.L(4)
This power supply rejection ratio is often lower than required.

(22) FIG. 2 provides an illustration of a prior art CG amplifier circuit 30 with a load resistor R.sub.L and a source resistance R.sub.S. In this amplifier circuit, the incremental gain is shown to be:

(23) $\begin{array}{cc}{a}_v\frac{g_{m1}{R}_L}{1+g_{m1}{R}_S}& \left(5\right)\end{array}$
where g.sub.m1 is the transconductance of the transistor M1. The incremental gain is positive, thus this amplifier provides non-inverting amplification.

(24) The input impedance at low frequencies is approximately 1/g.sub.m1, which is too low for applications where the source resistance R.sub.S is not very small. As can be seen in Equation (5), the incremental gain is reduced by a factor of 1+g.sub.m1R.sub.S compared with that of the CS amplifier in FIG. 1.

(25) As in the CS amplifier, the output resistance of the CG amplifier is approximately the same as the load resistor R.sub.L:
R.sub.oR.sub.L(6)

(26) Therefore, the CG amplifier's gain will be reduced if any resistive load is presented at the output. For example, if load resistance R.sub.1 is attached between the output and the incremental ground, the corresponding incremental gain is further reduced to

(27) $\begin{array}{cc}{a}_v\frac{g_{m1}(R_L.Math.R_1)}{1+g_{m1}{R}_S}& \left(7\right)\end{array}$
Thus, unless R.sub.1 is much larger than R.sub.L, the incremental gain is substantially reduced.

(28) The power supply rejection ratio of the CG amplifier in FIG. 2 is also shown to be approximately same as the incremental gain because the power supply noise couples to the output without attenuation as with the amplifier 20 in FIG. 1:

(29) $\begin{array}{cc}\mathrm{PSRR}\frac{g_{m1}{R}_L}{1+g_{m1}{R}_S}& \left(8\right)\end{array}$
Due to the lower incremental gain of the CG amplifier compared with that of a CS amplifier, the PSRR of the CG amplifier is often too low to be acceptable.

(30) FIG. 3 provides an illustration of a prior art source-coupled amplifier circuit 40 with a load resistor R.sub.L and a source resistance R.sub.S. In effect, the SF comprising M1 drives the CG amplifier comprising M2 and R.sub.L. The incremental gain of this circuit is shown to be

(31) $\begin{array}{cc}{a}_v\frac{g_{m1}{R}_L}{1+\frac{g_{m1}}{g_{m2}}}& \left(9\right)\end{array}$
where g.sub.m1 and g.sub.m2 are the transconductance of the transistor M1 and M2, respectively. The incremental gain is positive, thus this amplifier provides non-inverting amplification. The input resistance is infinite at low frequencies as in the CS amplifier of FIG. 1. The disadvantage of this amplifier is the additional power and area due to the SF, as well as extra noise contributed by the SF. Moreover, the incremental gain, as well as the PSRR, are reduced by a factor of

(32) $1+\frac{g_{m1}}{g_{m2}}$
compared with that of the CS amplifier.

(33) FIG. 4A shows an embodiment of an amplifier 50 according to the present invention. As in the prior art amplifier 20 in FIG. 1, an NMOS transistor MN1 constitutes the input transistor. A PMOS transistor MP2 functions as a load transistor, and the PMOS transistor MP1 functions as a feedback transistor. The bias voltage V.sub.BIAS is preferably referenced to the ground potential independent of the power supply, and adjusted in such way to bias all transistors in the saturation region. A negative feedback loop from the gate of MP1 to the drain of MP2, and back to the gate of MP1 adjusts the gate voltage of MP1 so that the drain currents of MP1 and MP2 match the drain current of MN1. The source terminal of the load transistor MP2 serves as an output of the amplifier 50.

(34) The incremental gain of this circuit is shown to be

(35) $\begin{array}{cc}{a}_v\frac{g_{\mathrm{mn}1}}{g_{\mathrm{mp}2}}& \left(10\right)\end{array}$
where g.sub.mn1 and g.sub.mp2 are the transconductance of the transistor MN1 and MP2, respectively. The incremental gain is positive, thus this amplifier provides non-inverting amplification. If same voltage gain is desired as that of the CS amplifier, the transconductance g.sub.mp2 is set to be:

(36) $\begin{array}{cc}{g}_{\mathrm{mp}2}=\frac{1}{R_L}& \left(11\right)\end{array}$
such that
a.sub.vg.sub.mn1R.sub.L(12)

(37) The input resistance is infinite at low frequencies as desired. The output resistance is given by

(38) $\begin{array}{cc}{R}_o\frac{1}{\left(1+g_{\mathrm{mp}1}{r}_{\mathrm{op}1}\right)g_{\mathrm{mp}2}}& \left(13\right)\end{array}$
where g.sub.mp1 and r.sub.op1 are the transconductance and output resistance of the transistor MP1, respectively. If g.sub.mp2 is set according to Equation (11), the output resistance is

(39) $\begin{array}{cc}{R}_o\frac{R_L}{1+g_{\mathrm{mp}1}{r}_{\mathrm{op}1}}& \left(14\right)\end{array}$

(40) Comparing with the output resistance of CS and CB amplifiers, the output resistance of the amplifier 50 is reduced by a large factor, 1+g.sub.mp1r.sub.op1, making it much easier for it to drive resistive loads as well as capacitive loads.

(41) The PSRR of the amplifier 50 is shown to be approximately
PSRRg.sub.mn1(r.sub.on1r.sub.op2)(15)
where r.sub.on1 and r.sub.op2 are the output resistance of the transistor MN1 and MP2, respectively. Typically, r.sub.on1r.sub.op2 is much larger than the load resistor R.sub.L, such that the PSRR of the amplifier according the present invention is higher than that of the prior art amplifiers in FIG. 1, FIG. 2, and FIG. 3.

(42) FIG. 4B illustrates another embodiment of the present invention where a current source I provide higher bias current in the NMOS transistor MN1, thereby increasing its transconductance g.sub.m1. As evidenced in Equations (10) and (15), higher g.sub.m1 provides higher gain and PSRR.

(43) For the amplifier 50 in FIG. 4A to function properly, all transistors must be biased in the saturation region. It can be shown that the output swing, which is the range of the output voltage for which both MP1 and MP2 are in the saturation region is given by |V.sub.TP1||(V.sub.GSP2V.sub.TP2)| where V.sub.TP1, V.sub.TP2, and V.sub.GSP2 are the threshold voltages of MP1 and MP2, and the gate-to-source voltage of MP2, respectively. In order to make the output swing large, large |V.sub.TP1| and small |(V.sub.GSP2V.sub.TP2)| are desired. Therefore, it may be preferred to employ a device type that offers the high threshold voltage for MP1. The gate length of MP1 may also be chosen to maximize its threshold voltage. Reverse back-gate biasing may be employed to further increase the threshold voltage of MP1.

(44) In some applications, it may be beneficial to insert a level shifting voltage between the drain of MP2 and the gate of MP1 to further increase the output swing. A variety of level shifting method, for example, using a pre-charged capacitor, may be employed. The output swing increases by the level shift amount. FIG. 5A shows a level shifting circuit implemented by a capacitor charged to a predetermined voltage V.sub.1. FIG. 5B shows a level shifting circuit implemented using a PMOS transistor MP3 and a current source I.sub.1. The gate-to-source voltage of MP3 determines the level shift amount. FIG. 5C shows a level shifting circuit implemented by a resistor R.sub.1 and a current source I.sub.2, where the level shift amount is I.sub.1R.sub.1.

(45) Since there is only a single leg of the circuit that the bias current flows through, the power consumption of the amplifier 50 in FIG. 4A is comparable to that of the CS amplifier in FIG. 1. In addition, it can be shown that the input referred noise is comparable to the CS amplifier if the incremental gain is made to be the same. Therefore there is no power or noise penalty in the amplifier circuit of FIG. 4, and the area penalty of the additional transistor is small.

(46) FIG. 6 shows another embodiment of the present invention. It is a flipped version of the amplifier 50 in FIG. 4A, having a PMOS input transistor MP1 and an NMOS load transistor MN2, and an NMOS feedback transistor MN1. Except for the flipped topology, the properties of the amplifier 60 are similar to those of the amplifier 50.

(47) FIG. 7 shows another embodiment of the present invention. It is a folded version of the amplifier 50 in FIG. 4A, having NMOS input transistor MN1 and an NMOS load transistor MN3 and NMOS feedback transistor MN2. The current source I.sub.1 supplies the bias currents for all transistors MN1, MN2, and MN3. Except for the NMOS input transistor instead of a PMOS input transistor, the amplifier 70 functions similarly to the amplifier 60 in FIG. 6.

(48) FIG. 8 shows an embodiment of the present invention using bipolar transistors. An NPN transistor QN1 constitutes the input transistor. A PNP transistor QP1 functions as the feedback transistor, and a PNP transistor QP2 functions as the load transistor. The resistor R.sub.1 effectively increases gain. The bias voltage V.sub.BIAS is preferably referenced to the ground potential independent of the power supply, and adjusted in such way to bias all transistors in the forward active region. A negative feedback loop from the base of QP1 to the collector of QP2, and back to the base of QP1 adjusts the base voltage of QP1 so that the collector currents of QP1 and QP2 match the collector current of QN1.

(49) The incremental gain of this circuit is shown to be

(50) 0$\begin{array}{cc}{a}_v{g}_{\mathrm{mn}1}\left(\frac{1}{g_{\mathrm{mp}2}}+R_1\right)& \left(16\right)\end{array}$
where g.sub.mn1 and g.sub.mp2 are the transconductance of the transistor QN1 and QP2, respectively. The incremental gain is positive, thus this amplifier provides non-inverting amplification. If same voltage gain is desired as that of a CE amplifier, the resistor R.sub.1 and transconductance g.sub.mp2 is set to be:

(51) $\begin{array}{cc}{R}_1+\frac{1}{g_{\mathrm{mp}2}}=R_L& \left(17\right)\end{array}$
such that
a.sub.vg.sub.mn1R.sub.L

(52) The input resistance is r.sub.1 at low frequencies as in a CE amplifier. The output resistance is given by

(53) $\begin{array}{cc}{R}_o\frac{1}{\left(1+{}_{\mathrm{op}1}\right)}\left(\frac{1}{g_{\mathrm{mp}2}}+R_1\right)& \left(18\right)\end{array}$
where .sub.op1 is the current gain of QP1, and g.sub.mp1 and r.sub.op1 are the transconductance and output resistance of the transistor QP1, respectively. If R.sub.1 and g.sub.mp2 are set according to Equation (17), the output resistance is

(54) $\begin{array}{cc}{R}_o\frac{R_L}{1+{}_{\mathrm{op}1}}& \left(19\right)\end{array}$
The output resistance of the amplifier 80 is reduced by a large factor, 1+.sub.op1, making it much easier for it to drive resistive or capacitive loads.

(55) The PSRR is shown to be approximately
PSRRg.sub.mn1(r.sub.on1r.sub.op2)(20)
where r.sub.on1 and r.sub.op2 are the output resistance of the transistor QN1 and QP2, respectively. Typically, r.sub.on1r.sub.op2 is much larger than the load resistor R.sub.L, such that the PSRR of the amplifier according the present invention is higher than that of CE or CB amplifiers.

(56) Since there is only a single leg of the circuit that the bias current flows through, the power consumption is comparable to that of a CE amplifier. 1. In addition, it can be shown that the input referred noise is comparable to the CE amplifier if the incremental gain is made to be the same. Therefore, there is no power or noise penalty in the amplifier circuit of FIG. 8, and the area penalty of the additional transistor is small.

(57) For the amplifier 80 to function properly, all transistors must be biased in the forward active region. In some applications, it may be beneficial to insert a level shifting voltage between the collector of QP2 and the base of QP1 to increase the output swing. The output swing increases by the level shift amount. A variety of level shifting method, for example, using a resistor, may be employed. FIG. 9A shows a level shifting circuit implemented by a resistor R.sub.2 and a current source I.sub.1, where the level shift amount is I.sub.1R.sub.2. FIG. 9B shows a level shifting circuit implemented using a PNP transistor QP3 and a current source I.sub.1. The base-to-emitter voltage of QP3 determines the level shift amount. FIG. 9C shows a level shifting circuit implemented by a V.sub.BE multiplier. The level shift amount is given by

(58) $\begin{array}{cc}{V}_1=\frac{R_2+R_3}{R_2}{V}_{\mathrm{BEn}2}& \left(21\right)\end{array}$
where V.sub.BEn2 is the base-to-emitter voltage of the transistor QN2.

(59) In cases where the base current of the transistor QP1 is large enough, the current source I.sub.1 may be omitted in the level shifting circuits shown in FIG. 9A, FIG. 9B, and FIG. 9C.

(60) FIG. 10 illustrates another embodiment of the present invention in a differential amplifier 85. The NMOS transistors MN1 and MN2 form the input differential pair. The PMOS transistors MP1 and MP3 function as the feedback transistors, and MP2 and MP4 function as the load transistors. The bias voltage VBIAS is preferably referenced to the ground potential for higher PSRR.

(61) A negative feedback loop from the gate of MP1 to the drain of MP2, and back to the gate of MP1 adjusts the gate voltage of MP1 so that the drain currents of MP1 and MP2 match the drain current of MN1. Likewise, another negative feedback loop from the gate of MP3 to the drain of MP4, and back to the gate of MP3 adjusts the gate voltage of MP3 so that the drain currents of MP3 and MP4 match the drain current of MN4. The outputs are obtained from the source terminals of the load transistors MP2 and MP4.

(62) The differential incremental gain of this circuit is shown to be

(63) $\begin{array}{cc}{a}_{\mathrm{vd}}=\frac{v_{\mathrm{od}}}{v_{\mathrm{id}}}\frac{g_{\mathrm{mn}1}}{g_{\mathrm{mp}2}}=\frac{g_{\mathrm{mn}2}}{g_{\mathrm{mp}4}}& \left(22\right)\end{array}$
where the differential input and output voltages v.sub.id and v.sub.od are defined as
v.sub.id=v.sub.1v.sub.2
v.sub.od=v.sub.o1v.sub.o2
Also, g.sub.mn1 and g.sub.mp2 are the transconductance of the transistor MN1 and MP2, respectively, and g.sub.mn2 and g.sub.mp4 are the transconductance of the transistor MN2 and MP4, respectively. The incremental gain is positive, thus this amplifier provides non-inverting amplification. The input resistance is infinite at low frequencies as desired.

(64) Since the circuit is fully-differential, the power supply noise affects both output voltages equally. For this reason, the PSRR is infinite if the two halves of the circuit are perfectly matched. In the presence of mismatch such as the threshold voltage mismatch and width or length mismatch of the devices, the amplifier 85 provides superior PSRR compared with prior art differential amplifiers for the same differential gain.

(65) In some application, higher gain is desired than is provided by Equation (22). FIG. 11 illustrates another embodiment of the present invention with gain enhancement by positive feedback in an amplifier 90. The PMOS transistors MP5 and MP7 as well as cascode transistors MP6 and MP8 are added. The PMOS transistors MP5 and MP7 provide positive feedback to increase the incremental gain. The cascode transistors MP6 and MP8 keep the drain voltages of MP5 and MP7 substantially equal to those of MP1 and MP3, respectively, for better matching of operating voltages between MP1/MP3 and MP5/MP7. The source terminals of the load transistor MP2 and MP4 serve as an output of the amplifier 90.

(66) The incremental gain of the amplifier 90 is given by

(67) $\begin{array}{cc}{a}_{\mathrm{vd}}=\frac{v_{\mathrm{od}}}{v_{\mathrm{id}}}\frac{g_{\mathrm{mn}1}}{g_{\mathrm{mp}1}-g_{\mathrm{mp}7}}=\frac{g_{\mathrm{mn}2}}{g_{\mathrm{mp}3}-g_{\mathrm{mp}5}}& \left(23\right)\end{array}$
As evident in Equation (23), if the sizes of MP5/MP7 are made equal to those of MP1/MP3, and the bias voltage VBIAS1 is adjusted such that the drain currents of MP5/MP7 are made equal to those of MP1/MP3, g.sub.mp1=g.sub.mp3=g.sub.mp5=g.sub.mp7, and the incremental gain becomes very large.

(68) While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the inventive teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. As a specific example, it may be desired to use PMOS input transistors in the amplifier circuits in FIG. 7, FIG. 10 and FIG. 11 instead of the NMOS input transistors as shown in the figures. Such flipped configurations are common and well known to those who are skilled in the art. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

(69) Also, the technology described herein may be embodied as a method, of which at least one example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

(70) All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.

(71) The indefinite articles a and an, as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean at least one.

(72) The phrase and/or, as used herein in the specification and in the claims, should be understood to mean either or both of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with and/or should be construed in the same fashion, i.e., one or more of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the and/or clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to A and/or B, when used in conjunction with open-ended language such as comprising can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

(73) As used herein in the specification and in the claims, or should be understood to have the same meaning as and/or as defined above. For example, when separating items in a list, or or and/or shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as only one of or exactly one of, or, when used in the claims, consisting of, will refer to the inclusion of exactly one element of a number or list of elements. In general, the term or as used herein shall only be interpreted as indicating exclusive alternatives (i.e. one or the other but not both) when preceded by terms of exclusivity, such as either, one of, only one of, or exactly one of Consisting essentially of, when used in the claims, shall have its ordinary meaning as used in the field of patent law.

(74) As used herein in the specification and in the claims, the phrase at least one, in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase at least one refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, at least one of A and B (or, equivalently, at least one of A or B, or, equivalently at least one of A and/or B) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

(75) In the claims, as well as in the specification above, all transitional phrases such as comprising, including, carrying, having, containing, involving, holding, composed of, and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases consisting of and consisting essentially of shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.