PHYSICAL TOPOLOGY FOR A POWER CONVERTER

Abstract

A physical topology for receiving top and bottom power electronic switches comprises a top collector trace connected to a positive voltage power supply tab and having a connection area for a collector of a top power electronic switch, a bottom emitter trace connected to a negative voltage power supply tab and having a connection area for an emitter of the bottom power electronic switch, and a middle trace connected to a load tab and having a connection area for an emitter of the top power electronic switch and a connection area for a collector of the bottom power electronic switch. Sampling points are provided on the traces for voltages on the emitters of the top and bottom power electronic switches, on the trace for voltage of the collector of the bottom power electronic switch, and on the negative voltage power supply tab. The topology defines parasitic inductances. Sample voltages can be supplied to gate driver references.

Claims

1. A physical topology for receiving top and bottom power electronic switches, each power electronic switch including a collector, a gate and an emitter, the topology comprising: a top collector trace connected to a positive voltage power supply tab, the top collector trace having a connection area for the collector of the top power electronic switch; a bottom emitter trace connected to a negative voltage power supply tab, the bottom emitter trace having a connection area for the emitter of the bottom power electronic switch; a middle trace connected to a load tab, the middle trace having a connection area for the emitter of the top power electronic switch and a connection area for the collector of the bottom power electronic switch; a top power electronic switch emitter voltage sampling point located on the middle trace within the connection area for the emitter of the top power electronic switch; a bottom power electronic switch collector voltage sampling point located within a connection area of the middle trace to the load tab; a bottom power electronic switch emitter voltage sampling point located on the bottom emitter trace within the connection area for the emitter of the bottom power electronic switch; and a negative voltage power supply tab sampling point located within a connection area of the bottom emitter trace to the negative voltage power supply tab.

2. The topology of claim 1, wherein: the top collector trace forms a top collector inductance; the bottom emitter trace forms a bottom emitter inductance; the middle trace forms a top emitter inductance between the connection area for the emitter of the top power electronic switch and the collector of the bottom power electronic switch; and the middle trace forms a bottom collector inductance between the load tab and the connection area for the collector of the bottom power electronic switch.

3. The topology of claim 2, wherein: the top emitter inductance is greater than the top collector inductance and greater than the bottom collector inductance; and the bottom emitter inductance is greater than the top collector inductance and greater than the bottom collector inductance.

4. The topology of claim 1, wherein: the connection area for the collector of the top power electronic switch and the connection area for the collector of the bottom power electronic switch are configured for direct contact with the collectors of the power electronic switches; and the connection area for the emitter of the top power electronic switch and the connection area for the emitter of the bottom power electronic switch are configured for connection to the emitters of the power electronic switches via wires.

5. The topology of claim 1, wherein: the top collector trace is configured for mounting a diode in parallel with the top power electronic switch; and the middle trace is configured for mounting of a diode in parallel with the bottom power electronic switch.

6. The topology of claim 1, wherein: the top collector trace is configured for mounting a plurality of parallelized top power electronic switches; and the middle trace is configured for mounting a plurality of parallelized bottom power electronic switches.

7. The topology of claim 6, wherein: the middle trace includes a groove leading from the top power electronic switch emitter voltage sampling point in a direction toward the load tab to substantially equalize currents in each of the parallelized top power electronic switches; and the bottom emitter trace includes a groove leading from the bottom power electronic switch emitter voltage sampling point in a direction toward the negative voltage power supply tab to substantially equalize currents in each of the parallelized bottom power electronic switches.

8. The topology of claim 1, wherein the top collector trace, the bottom emitter trace and the middle trace are on a direct bonded copper (DBC) substrate.

9. The topology of claim 8, wherein each of the top power electronic switch emitter voltage sampling point, the bottom power electronic switch collector voltage sampling point, the bottom power electronic switch emitter voltage sampling point and the negative voltage power supply tab sampling point is electrically connected to a respective gate driver connection extending from a plane of the DBC substrate and configured for connection to a separate circuit card.

10. The topology of claim 1, comprising: a top gate trace configured for connection to the gate of the top power electronic switch via one or more wires; and a bottom gate trace configured for connection to the gate of the bottom power electronic switch via one or more wires.

11. The topology of claim 10, comprising a pair of gate driver connections respectively extending from the top and bottom gate traces and configured for connection to respective top and bottom gate driver outputs.

12. The topology of claim 1, wherein the load tab is a phase tab.

13. The topology of claim 1, wherein the top and bottom power electronic switches include isolated gate bipolar transistors (IGBT).

14. A power converter, comprising: the topology and the top and bottom power electronic switches of claim 1; a top gate driver having a reference electrically connected to the top power electronic switch emitter voltage sampling point and to the bottom power electronic switch collector voltage sampling point; and a bottom gate driver having a reference electrically connected to the bottom power electronic switch emitter voltage sampling point and to the negative voltage power supply tab sampling point.

15. The power converter of claim 14, wherein: the reference of the top gate driver is connected to the top power electronic switch emitter voltage sampling point via a first turn-on diode in parallel with a first resistor, the first turn-on diode being polarized to short the first resistor when a voltage of the top power electronic switch emitter is higher than a voltage of the reference of the top gate driver; the reference of the top gate driver is connected to the bottom power electronic switch collector voltage sampling point via a second resistor; the reference of the bottom gate driver is connected to the bottom power electronic switch emitter voltage sampling point via a second turn-on diode in parallel with a third resistor, the second turn-on diode being polarized to short the third resistor when a voltage of the bottom power electronic switch emitter is higher than a voltage of the reference of the bottom gate driver; the reference of the bottom gate driver is connected to the negative voltage power supply tab sampling point via a fourth resistor.

16. A tri-phase power converter comprising three power converters as defined in claim 14.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Embodiments of the disclosure will be described by way of example only with reference to the accompanying drawings, in which:

[0030] FIG. 1 is an idealized circuit diagram of a conventional commutation cell such as those used in conventional power converter circuits;

[0031] FIG. 2 is another circuit diagram of the conventional commutation cell of FIG. 1, showing parasitic (stray) inductances;

[0032] FIG. 3 is a circuit diagram of an IGBT leg formed of two commutation cells;

[0033] FIG. 4 is a schematic representation of a typical topology for an IGBT module;

[0034] FIG. 5 is a top plan view of an actual IGBT module having the topology of FIG. 4, the IGBT module including a circuit card and a casing;

[0035] FIG. 6 is a top plan view of an IGBT module according to an embodiment, the IGBT module including a circuit card and a casing;

[0036] FIG. 7 is a perspective view of the IGBT module of FIG. 6;

[0037] FIG. 8 is a perspective view of the IGBT module of FIG. 6, showing the circuit card and connectors, without the casing; and

[0038] FIG. 9 is a circuit diagram of an IGBT leg adapted for use with the IGBT module of FIG. 6.

[0039] Like numerals represent like features on the various drawings.

DETAILED DESCRIPTION

[0040] Various aspects of the present disclosure generally address one or more of the problems of overvoltage present in power converters at the time of switching.

[0041] Circuits operable to limit overvoltage in commutation cells, especially at turn-off of IGBTs, are described in international patent publications no WO 2013/082705 A1, WO 2014/043795 and WO 2014/161080 A1, WO 2015/070344 A1, WO 2015/061901 A1, WO 2015/070347 A1 and WO 2015/139132 A1, all of which are authored by Jean-Marc Cyr et al. the disclosure of these being incorporated by reference herein.

[0042] The present technology provides control of overvoltage and switching losses at turn-off of a power electronic switch of a power module. Circuits and methods presented herein are generally compatible with other solutions to limit overvoltage at turn-off of power electronic switches.

[0043] In a power module, di/dt at turn-off of a power electronic switch generates a voltage across stray inductances of the high frequency loop of the power module. This voltage is applied across the power electronic switch in addition to a bus voltage providing power to the power module. A solution based on the injection of a sample of the overvoltage present across the power electronic switch to a gate driver of the power electronic switch has been proposed. In the case of a pair of power electronic switches connected in series, this solution efficiently controls the overvoltage on a bottom power electronic switch. However, a parasitic inductance present between an emitter of a top power electronic switch and a collector of the bottom power electronic switch may not be sufficient to provide a sufficient sample of the overvoltage present in the top power electronic switch. An improvement comprises defining a new physical topology for mounting power electronic switches, the topology providing a changed definition of parasitic inductances voltage and sampling points for voltages thereacross.

[0044] It is to be noted that the expression parasitic inductance is used herein and in the appended claims to refer to the inductance created by the connections between the various components of an actual commutation cell. As will be understood from the present disclosure, the voltage generated across some of the parasitic inductances is sampled and used to improve the operation of the commutation cell. Nevertheless, for clarity purpose, these inductances are referred to as parasitic inductances herein.

[0045] The techniques disclosed herein will mainly be described in relation to the use of isolated gate bipolar transistors (IGBT). Mentions of IGBTs in the following description are made for illustration purposes and are not meant to limit the present disclosure. The same techniques may equally be applied to power modules constructed using metal-oxide-semiconductor field-effect transistors (MOSFET), bipolar transistors and like controlled power electronic switches.

[0046] These techniques provide voltage samples for connection to gate drivers of an IGBT module. Voltages across top and bottom emitter inductances are injected in respective gate drivers to create negative voltages at the emitter of the IGBTs, slowing down the negative slope of V.sub.ge. The result is a direct action on the gate voltages without any delay in the di/dt limitations.

[0047] The present disclosure introduces an improved physical topology that defines parasitic inductances in power electronic switches, for example in an IGBT module. FIG. 6 is a top plan view of an IGBT module according to an embodiment, the IGBT module including a circuit card and a casing. FIG. 7 is a perspective view of the IGBT module of FIG. 6. FIG. 8 is a perspective view of the IGBT module of FIG. 6, showing the circuit card and connectors, without the casing.

[0048] Referring at once to FIGS. 6-8, a physical topology 200 is implemented in the form of a card, for example a direct bonded copper (DBC) substrate that can be mounted in a casing 202. The topology 200 is adapted for receiving a top power electronic switch, that optionally include a plurality of parallelized top IGBTs 204, and a bottom power electronic switch, that optionally include a plurality of parallelized bottom IGBTs 206. As expressed hereinabove, each IGBT includes a collector, a gate and an emitter. The topology 200 comprises a top collector trace 208, connected to a positive voltage power supply tab 210. The top collector trace 208 provides a connection area for the collectors of the top IGBTs 204. The topology 200 also comprises a bottom emitter trace 212 connected to a negative voltage power supply tab 214. The bottom emitter trace 212 provides a connection area for the emitters of the bottom IGBTs 206. Also included in the topology 200 is a middle trace 216 connected to a load tab 218 that may be a phase tab in the case of a multiphase embodiment. The middle trace 216 has a connection area for the emitters of the top IGBTs 204 and a connection area for the collectors of the bottom IGBTs 206. Collectors of the top IGBTs 204 are in direct contact with the top collector trace 208 while collectors of the bottom IGBTs 206 are in direct contact with the middle trace 216. Wires 220 connect the emitters of the top IBGTs 204 to the middle trace 216 and wires 221 connect emitters of the bottom IGBTs 206 to the bottom emitter trace 212. Top freewheel diodes 222 are mounted in parallel to the top IGBTs 204 on the top collector trace 208 and bottom freewheel diodes 224 are mounted in parallel to the bottom IGBTs 206 on the middle trace 216. Traces are made of a conductive material, using for example direct bound copper (DBC).

[0049] The topology 200 includes four (4) voltage-sampling points. These comprise a top IGBT emitter voltage sampling point 226 located on the middle trace 216 within the connection area for the emitters of the top IGBTs 204, a bottom IGBT collector voltage sampling point located 228 within a connection area of the middle trace 216 to the load tab 218, a bottom IGBT emitter voltage sampling point 230 located on the bottom emitter trace 212 within the connection area for the emitters of the IGBT 206, and a negative voltage power supply tab sampling point 232 located within a connection area of the bottom emitter trace 212 to the negative voltage power supply tab 214.

[0050] The sampling points 226, 228, 230 and 232 are respectively connected to pins 234, 236, 238 and 240 that extend from a plane of the card supporting the topology 200 to provide connections to gate drivers (on a later Figure) located on a separate circuit card (not shown). It may be noted that the pins 234 and 238 directly connect, for example by welding, to the sampling points 226 and 230, respectively. On the other hand, the pins 236 and 240 are respectively welded on edges of the middle trace 216 and of the bottom emitter trace 212 and connect to the sampling points 228 and 232 via portions of the middle trace 216 and of the bottom emitter trace 212. Grooves 242 and 244 are provided to isolate strong currents flowing between the bottom IGBTs 206 and the tabs 218 and 214 so that the voltages on the pins 236 and 242 effectively reflect the voltages at the tabs 218 and 214, respectively.

[0051] Within the topology 200, the top collector trace 208 forms a top collector inductance (L.sub.c-top), generally defined between the connection area for the positive voltage power supply tab 210 and points where the various top IGBTs 204 are mounted on the top collector trace. The bottom emitter trace 216 forms a bottom emitter inductance (L.sub.e-bot), generally between the connection area of the emitters of the bottom IGBTs 206, substantially at the bottom IGBT emitter voltage sampling point 230, and the connection area for the negative voltage power supply tab 214. The middle trace 216 forms a top emitter inductance (L.sub.e-top), generally between the connection area for the emitters of the top IGBTs 204, substantially at the top IGBT emitter voltage sampling point 226, and the connection area for the load tab 218. The middle trace 216 also forms a bottom collector inductance (L.sub.c-bot), generally between the connection area for the load tab 218 and points where the various bottom IGBTs 206 are mounted on the middle trace 216. Without limitation, the top emitter inductance (L.sub.e-top) and the bottom emitter inductance (L.sub.e-bot) may both be greater than the top collector inductance (L.sub.c-top).

[0052] The disclosed topology, when compared to earlier layouts, provides a reduction of the collector inductance values as well as an increase of the top emitter inductance value. An overall inductance in the high frequency loop of an IGBT leg built using the disclosed topology may, in some embodiments, remain similar to the overall inductance provided in earlier layouts, for example in the layout of FIGS. 4 and 5, so that, resulting switching losses and switching speeds are not significantly impacted. However, because the top emitter inductance is increased, it becomes much easier to configure the application of a voltage, sampled thereacross, to the gate driver of the top power electronic switch.

[0053] As shown on FIGS. 6, 7 and 8, emitters of the top IGBTs 204 and the bottom IGBTs 206 are respectively connected to the middle trace 216 and to the bottom emitter trace 212, via wires 220, over fairly broad connection areas. In order to substantially equalize currents in each of the parallelized IGBTs 204 and 206, the middle trace 216 includes a groove 246 leading from the top IGBT emitter voltage sampling point 226 in a direction toward the load tab 218 while the bottom emitter trace 212 includes a groove 248 leading from the bottom IGBT emitter voltage sampling point 230 in a direction toward the negative voltage power supply tab 214. Currents from the IGBT 204 and 206 emitters are driven toward the sampling points 226 and 230 before flowing further to the tabs 218 and 214.

[0054] FIGS. 6, 7 and 8 also show a top gate trace 250 configured for connection to the gate of the top IGBTs 204 via wires 223 and a bottom gate trace 252 configured for connection to the gate of the IGBTs 206, via wires 225. Pins 254 and 256 that extend from the plane of the card supporting the topology 200 provide connections to respective top and bottom gate driver outputs (shown on a next Figure).

[0055] The topology 200 can be used as a part of a power converter. FIG. 9 is a circuit diagram of an IGBT leg configured to be used with the IGBT module of FIG. 6. An IGBT leg 300 is schematically illustrated. Some of its elements are mounted on the physical topology 200 of FIGS. 6, 7 and 8 and some other elements of the IGBT leg 300 are mounted on a separate circuit card (not shown) that may for example be mounted atop the casing 202 that encloses the topology 200. The IGBT leg 300 includes the top IGBTs 204, the top freewheel diodes 222, the bottom IGBTs 206 and the bottom freewheel diodes 224, each of which is mounted on the topology 200 and may include a single device or a plurality of parallelized devices. The inductances L.sub.c-top, L.sub.e-top, L.sub.c-bot, and L.sub.e-bot are defined by the traces 208, 212 and 216 of the topology 200, as expressed hereinabove. The inductances L.sub.+Vbus, L.sub.Vbus and L.sub.phase are defined by the positive voltage power supply tab 210, the negative voltage power supply tab 214 and the load tab 218 (also called phase tab in the case of a multiphase embodiment), respectively.

[0056] The pins 234, 236, 238 and 240 that extend from the plane of the card supporting the topology 200 are connected on the IGBT leg 300 at the points shown on FIG. 9. A voltage across the top emitter inductance L.sub.e-top is present between pins 234 and 236 and a voltage across the bottom emitter inductance L.sub.e-bot is present between pins 238 and 240.

[0057] A top gate driver 302 is fed by a positive voltage supply +V.sub.cc and by a negative voltage supply V.sub.dd and has a reference 304. A control signal is fed at an input 303 of the top gate driver 302 to cause an output 305 to reach either of the +V.sub.cc above or V.sub.dd below the reference 304, forming signals applied to the gate 26 of the top IGBT 204 via a gate resistor R.sub.4. The reference 304 of the top gate driver 302 is connected across gate-emitter in series with the emitter inductance of the top IGBT 204 via a compensation circuit that includes resistors and an optional turn-on diode. The reference 304 is electrically connected to the top IGBT emitter voltage sampling point 226, either directly via the pin 234 or, optionally, via a turn-on diode D.sub.4 in series with a resistor R.sub.D4 and via the pin 234. If present, the turn-on diode D.sub.4 is polarized to become short when an emitter voltage of the top IGBT 204 is higher than a voltage of the reference 304. The reference 304 is also electrically connected to the bottom IGBT collector voltage sampling point 228 via a resistor R.sub.8 and via the pin 236. A resistor R.sub.7 is optionally placed in parallel with the series combination of the turn-on diode D.sub.4 with the resistor R.sub.D4. If the turn-on diode D.sub.4 is absent (or equivalently if the resistor R.sub.D4 has an infinite value), the compensation circuit operates similarly during turn-on and turn-off of the top IGBT 204. If the turn-on diode D.sub.4 is present and if the resistor R.sub.D4 is replaced by a short circuit, there is no compensation at turn-on. In the presence of the turn-on diode D.sub.4, selection of a proper value for the resistor R.sub.D4 allows to fine tune the turn-on of the top IGBT 204 independently from its turn-off, the compensation circuit forming a resistive divider between R.sub.D4 in parallel with R.sub.7, this parallel combination being in series with R.sub.8. It is to be noted that resistor R.sub.7 may have an infinite value. Resistor R.sub.7 is used to fine-tune the circuit, if necessary.

[0058] A bottom gate driver 308 is also fed by a positive voltage supply +V.sub.cc and by a negative voltage supply V.sub.dd and has a reference 310. A control signal is fed at an input 309 of the bottom gate driver 308 to cause an output 311 to reach either of the +V.sub.cc above or V.sub.dd below the reference 310, forming signals applied to the gate 26 of the bottom IGBT 206 via a gate resistor R.sub.1. The reference 310 of the bottom gate driver 308 is connected across the emitter inductance of the bottom IGBT 206 via a compensation circuit including resistors and an optional turn-on diode. The bottom gate driver 308 is connected to the bottom IGBT 206 via a compensation circuit including resistors and an optional turn-on diode. The reference 310 is electrically connected to the bottom IGBT emitter voltage sampling point 230, either directly via the pin 238 or, optionally, via a turn-on diode D.sub.3 in series with a resistor R.sub.D3 and via the pin 238. If present, the turn-on diode D.sub.3 is polarized to become short when an emitter voltage of the bottom IGBT 206 is higher than a voltage of the reference 310. The reference 310 is also electrically connected to the negative voltage power supply tab sampling point 232 via a resistor R.sub.10 and via the pin 240. A resistor R.sub.9 is optionally placed in parallel with the turn-on diode D.sub.3 in series with the resistor R.sub.D3. If the turn-on diode D.sub.3 is absent (or equivalently if the resistor R.sub.D3 has an infinite value), the compensation circuit operates similarly during turn-on and turn-off of the bottom IGBT 206. If the turn-on diode D.sub.3 is present and if the resistor R.sub.D3 is replaced by a short circuit, there is no compensation at turn-on. In the presence of the turn-on diode D.sub.3, selection of a proper value for the resistor R.sub.D3 allows to fine tune the turn-on of the bottom IGBT 206 independently from its turn-off, the compensation circuit forming a resistive divider between R.sub.D3 in parallel with R.sub.9, this parallel combination being in series with R.sub.10. It is to be noted that resistor R.sub.9 may have an infinite value.

[0059] Considering for example a commutation cell formed of the top IGBT 204, its top gate driver 302 and the compensation circuit including the optional turn-on diode D.sub.4 and the resistors R.sub.7 and R.sub.8. When the top IGBT 204 is already turned-on, the output 305 of the top gate driver 302 being at +V.sub.cc above the reference 304, it is essentially shorted and its emitter voltage present at the pin 234 is essentially equal to the +V.sub.bus voltage. This voltage equal to a voltage at the reference 304 and the turn-on diode D.sub.4 is shorted. When the input 303 provides a turn-off command to the gate driver 302, without the compensation circuit, the output 305 would quickly fall to V.sub.dd and the top IGBT 204 would rapidly become an open circuit. The rapid reduction of current flowing therethrough would cause an excessive voltage across the L.sub.e-top, with the polarity as shown on FIG. 9, causing overvoltage. With the compensation circuit and the present topology, the emitter voltage at the pin 234 reduces below the voltage of the reference 304 and the turn-on diode D.sub.4 becomes an open circuit. The voltage across the L.sub.e-top, between the pins 234 and 236 is divided between the resistors R.sub.7 and R.sub.8, providing a sample of the overvoltage applied at the reference 304. This sample of the overvoltage across the L.sub.e-top is added in series to the V.sub.dd value, effectively slowing down a drop of the voltage V.sub.ge between the gate 26 and the emitter 24 of the top IGBT 204 to slow down its di/dt, reducing the overvoltage between its collector 22 and emitter 24.

[0060] Upon turn-on of the top IGBT 204, because current starts flowing therethrough, the voltage across the L.sub.e-top has a reverse polarity and the emitter voltage at pin 234 increases above the voltage of the reference 304, shorting again the turn-on diode D.sub.4, if present. While the output 305 of the top gate driver 302 tends to reach +V.sub.cc, this rise of voltage applied to the gate 26 is slowed down by application on the reference 304 of the emitter voltage present at the pin 234. This slows down a rise of the voltage V.sub.ge between the gate 26 and the emitter 24 and, consequently, of the di/dt through the top IGBT 204. In turn, this reduces the recovery current in the bottom freewheel diode 224.

[0061] A commutation cell formed of the bottom IGBT 206, its gate drive 208 and a compensation circuit including the turn-on diode D.sub.3, if present, and the resistors R.sub.9 and R.sub.10 operate in the same manner.

[0062] The foregoing describes solutions applicable to DC-DC power converters, AC-DC power converters and to DC-AC power converters, for example power modules using a full leg of semiconductors, opposite pairs of power electronic switches and freewheel diodes, to provide alternative current to a connected load such as a motor of an electric vehicle, as well as tri-phase power converters built using three physical layouts as disclosed herein and three pairs of power electronic switches.

[0063] Those of ordinary skills in the art will realize that the description of the physical topology for a power converter is illustrative only and are not intended to be in any way limiting. Other embodiments will readily suggest themselves to such persons with ordinary skill in the art having the benefit of the present disclosure. Furthermore, the topology may be customized to offer valuable solutions to existing needs and problems of overvoltage occurring in power electronic switches.

[0064] As a non-limiting example, one skilled in the art will understand that the position of the sampling points 226 and 230 onto the trace 216 and 212 could be changed depending on the values of the parasitic inductances required for a particular application.

[0065] In the interest of clarity, not all of the routine features of the implementations of the topology are shown and described. It will, of course, be appreciated that in the development of any such actual implementation of the topology, numerous implementation-specific decisions may need to be made in order to achieve the developer's specific goals, such as compliance with application, system, and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the field of power electronics having the benefit of the present disclosure.

[0066] It is to be understood that the topology is not limited in its application to the details of construction and parts illustrated in the accompanying drawings and described hereinabove. The proposed topology is capable of other embodiments and of being practiced in various ways. It is also to be understood that the phraseology or terminology used herein is for the purpose of description and not limitation.

[0067] The topology has been described hereinabove by way of illustrative embodiments thereof. The scope of the claims should not be limited by the embodiments set forth in the examples, but should be given the broadest interpretation consistent with the description as a whole.