ALUMINUM-GALLIUM-NITRIDE COMPOUND/GALLIUM-NITRIDE HIGH-ELECTRON-MOBILITY TRANSISTOR

Abstract

A nitride high electron mobility transistor having a strain balance of an aluminum gallium nitride insertion layer is described. The transistor sequentially includes: a substrate and a GaN buffer layer located on the substrate; an AlyGa1-yN insertion layer located on the GaN buffer layer; an AlxGa1-xN barrier layer located on the AlyGa1-yN insertion layer opposite to the GaN buffer layer; a GaN cap layer located on the AlxGa1-xN barrier layer; a -shaped source electrode and drain electrode provided in recesses formed by the removal of the GaN cap layer and some thickness of the AlxGa1-xN barrier layer; and a gate electrode located between the source electrode and the drain electrode. An AlzGa1-zN insertion layer may be further included between the AlxGa1-xN barrier layer and the GaN cap layer.

Claims

1. An aluminum gallium nitride/gallium nitride high electron mobility transistor, comprising, sequentially from bottom to top, a substrate (21); a GaN buffer layer (22); an Al.sub.yGa.sub.1-yN insertion layer (23), wherein 0.35y0.5; an Al.sub.xGa.sub.1-xN barrier layer (24), wherein 0.2x0.28; a GaN cap layer (25); a source electrode (26) and a drain electrode (27) disposed at both ends of the GaN cap layer, wherein the GaN cap layer and some thickness of the Al.sub.xGa.sub.1-xN barrier layer where the source electrode (26) and the drain electrode (27) are located are removed to form recesses, and the source electrode (26) and the drain electrode (27) are disposed in the recesses; and a gate electrode (28) located between the source electrode (26) and the drain electrode (27).

2. An aluminum gallium nitride/gallium nitride high electron mobility transistor according to claim 1, further comprising an Al.sub.zGa.sub.1-zN insertion layer (35) located on the Al.sub.xGa.sub.1-xN barrier layer (24), wherein 0.30z0.4, and the thickness of the Al.sub.zGa.sub.1-zN insertion layer (35) is preferably 1-3 nm.

3. An aluminum gallium nitride/gallium nitride high electron mobility transistor according to claim 1, wherein the GaN buffer layer (22) is subjected to Fe doping, with the doping concentration being no more than 410.sup.18 cm.sup.3 and the doping thickness being between 500-1000 nm upward from the substrate.

4. An aluminum gallium nitride/gallium nitride high electron mobility transistor according to claim 1, wherein the substrate (21) is one of silicon carbide, silicon or sapphire.

5. An aluminum gallium nitride/gallium nitride high electron mobility transistor according to claim 1, wherein the thickness of the GaN buffer layer (22) is 1500-2000 nm.

6. An aluminum gallium nitride/gallium nitride high electron mobility transistor according to claim 1, wherein the source electrode (26) and the drain electrode (27) are partially located on the GaN cap layer (25) to form a shape.

Description

BRIEF OF THE DRAWINGS

[0008] FIG. 1 is a schematic view of a general structure of an AlGaN/GaN HEMT.

[0009] FIG. 2 is a schematic view of the structure of an AlGaN/GaN HEMT according to one embodiment of the present invention.

[0010] FIG. 3 is a schematic view of the structure of an AlGaN/GaN HEMT according to another embodiment of the present invention.

DETAILED OF THE INVENTION

[0011] The present invention is described below in further detail with reference to the accompanying drawings.

[0012] FIG. 2 shows one embodiment of an AlGaN/GaN HEMT according to the present invention. The AlGaN/GaN HEMT according to the present invention has a substrate 21. The substrate 21 is any one of sapphire, Si and SiC, and preferably, semi-insulating 4H-SiC and semi-insulating 6H-SiC are used as the substrate. Because of their properties such as high thermal conductivity and small lattice mismatch with GaN, the use semi-insulating 4H-SiC (0001) and semi-insulating 6H-SiC (0001) as the substrate is beneficial for growth of a high-quality GaN epitaxial material and also facilitates heat dissipation of the device. Currently, 4H-SiC and 6H-SiC substrates are commercially available from Cree and II-VI in USA.

[0013] A GaN buffer layer 22 is located on the substrate 21 and has a thickness of preferably 1500-2000 nm. The GaN buffer layer 22 generally has a high background carrier concentration that is unfavorable for improvement of the device breakdown. For this reason, Fe doping may be contemplated and in this respect, reference may be made to relevant literatures, but doping concentration and thickness of Fe doping must be controlled. The doping concentration is generally within 410.sup.18 cm.sup.3 and the doping thickness is no more than 500-1000 nm upward from the substrate, that is, the thickness of about 1000 nm on the top of the GaN buffer layer remains undoped. In order to obtain a GaN buffer layer with good quality, a nucleation layer is generally located between the GaN buffer layer 22 and the substrate 21. The nucleation layer is mainly used as a transition so as to reduce the stress caused by the lattice mismatch between the GaN buffer layer 22 and the substrate 21. The selection of the nucleation layer is related to the substrate material, which is well known in the art and is not further described.

[0014] An Al.sub.yGa.sub.1-yN insertion layer 23 is located on the GaN buffer layer, wherein 0.35y0.5 and the thickness of the Al.sub.yGa.sub.1-yN insertion layer 23 is most preferably 1-3 nm. The band gap at the interface of the Al.sub.yGa.sub.1-yN insertion layer 23 and the GaN buffer layer 22 is larger than that of the GaN buffer layer, such that a triangular potential well is formed at the interface of the GaN buffer layer 22 and the Al.sub.yGa.sub.1-yN insertion layer 23 in close proximity to the GaN buffer layer. This triangular potential well, together with strong spontaneous and piezoelectric polarization effects of Group III nitrides themselves, leads to formation of a two-dimensional electron gas with a high areal density near the interface of the GaN buffer layer 22 and the Al.sub.yGa.sub.1-yN insertion layer 23.

[0015] An Al.sub.xGa.sub.1-xN barrier layer 24 is located on the Al.sub.yGa.sub.1-yN insertion layer 23 opposite to the GaN buffer layer 22, wherein 0.2x0.28 and the thickness of the Al.sub.xGa.sub.1-xN barrier layer 24 is most preferably 10-20 nm. By use of spontaneous and piezoelectric polarization effects of the Al.sub.xGa.sub.1-xN barrier layer 24, the triangle potential well formed at the interface of the GaN buffer layer 22 and the Al.sub.yGa.sub.1-yN insertion layer 23 in close proximity to the GaN buffer layer may be deeper, thus obtaining a 2DEG with a higher areal density and facilitating the improvement of device performance.

[0016] A GaN cap layer 25 is located on the Al.sub.xGa.sub.1-xN barrier layer 24, wherein the thickness of the GaN cap layer is most preferably 1-3 nm. The GaN cap layer 25 serves to balance the strain force caused by the Al.sub.yGa.sub.1-yN insertion layer 23 and the Al.sub.xGa.sub.1-xN barrier layer 24, and also enables inhibition of current collapse effect prevalent in the AlGaN/GaN HEMT, thus improving the microwave performance of the device.

[0017] The GaN buffer layer 22 (along with the nucleation layer between the GaN buffer layer 22 and the substrate 21), the Al.sub.yGa.sub.1-yN insertion layer 23, the Al.sub.xGa.sub.1-xN barrier layer 24, and the GaN cap layer 25 may be obtained by epitaxial growth sequentially on the substrate 21 using any suitable growing method such as MOCVD, RF-MBE, preferably MOCVD.

[0018] The GaN cap layer 25 and some thickness of the Al.sub.xGa.sub.1-xN barrier layer 24 below a source electrode 26 and a drain electrode 27 are removed to form recesses. The recesses are formed by dry etching. The removal of both compounds GaN and AlGaN by dry etching is well known in the art and reference may be made to relevant literatures. The source electrode and the drain electrode are provided in the recesses and are partially located on the GaN cap layer to form a -shaped source electrode and drain electrode. The source electrode 26 and the drain electrode 27 use the same metal layer, including, but not limited to, a multi-layer metal system such as Ti/Al/Ni/Au, Ti/Al/Mo/Au, and require a high-temperature alloy process to form an ohmic contact with the 2DEG, wherein the alloy temperature is preferably 680-780 C.

[0019] A gate electrode 28 is provided between the source electrode 26 and the drain. electrode 27. The gate electrode 28, on one hand, serves to form a schottky contact with the GaN cap layer 25 such that changes in voltage on the gate electrode 28 can modulate the two-dimensional electron gas in the channel when the device is in operation; and on the other hand, serves to decrease the gate resistance of the device and improve the frequency characteristics of the device. The gate electrode 28 may use metals including, but not limited to, a multi-layer metal system such as Ni/Au/Tior Ni/Pt/Au/Pt/Ti or Ni/Pt/Au/Ni.

[0020] FIG. 3 shows another embodiment of the AlGaN/GaN HEMT according to the present invention, in which an Al.sub.zGa.sub.1-zN insertion layer 35 is added on the basis of the first embodiment. The Al.sub.zGa.sub.1-zN insertion layer 35 is located on the Al.sub.xGa.sub.1-xN barrier layer 34, wherein 0.3z0.4 and the thickness of the Al.sub.zGa.sub.1-zN insertion layer 35 is 1-3 nm. By use of spontaneous and piezoelectric polarization effects of the Al.sub.zGa.sub.1-zN insertion layer 35, areal density of the 2DEG formed at the interface of the GaN buffer layer 32 and the Al.sub.yGa.sub.1-yN insertion layer 33 in close proximity to the GaN buffer layer may be further increased and device performance is further improved.

[0021] It should be noted that the AlGaN insertion layer with a high Al content located on the GaN buffer layer in both embodiments of the present invention is aimed to increase the areal density and mobility of the 2DEG in the channel so as to achieve the effect of the AlN insertion layer shown in FIG. 1. Also, as compared to the AlN insertion layer, the AlGaN insertion layer with a high Al content has a smaller lattice mismatch with the GaN buffer layer, the AlGaN insertion layer may be designed to be thicker, facilitating more precise control in the process. In addition, the GaN cap layer mainly serves to balance the stress caused by the lattice mismatch between the AlGaN insertion layer and the AlGaN barrier layer below it and the GaN buffer layer. As incorporation of the GaN cap layer will lead to decrease of areal density of the 2DEG in the channel, the thickness of the GaN cap layer must not be too thick. The GaN cap layer has a large lattice mismatch with the AlGaN insertion layer and the AlGaN barrier layer and thus is subjected to a large compression stress, such that its effect of decreasing the 2DEG concentration in the channel is further enhanced. By incorporation of the -shaped source electrode and drain electrode, some stress on the GaN cap layer may be released and the effect of decreasing the 2DEG concentration in the channel by incorporation of the GaN cap layer may be alleviated, thereby making a compromise between the performance and reliability of the device. The incorporation of the -shaped source electrode and drain electrode is more favorable for electrons in the channel to enter the source electrode or drain electrode through the tunneling effect, and vice versa, so as to reduce the ohmic contact resistance of the device, thereby facilitating further improvement of device performance.