LIGHT EMITTING ELEMENT DRIVE DEVICE AND LIGHT EMITTING SYSTEM
20230099245 · 2023-03-30
Inventors
Cpc classification
Y02B20/30
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
International classification
Abstract
A light emitting element drive device includes a driving circuit that supplies a variable drive current to a light emitting unit having one or more light emitting elements so that the light emitting unit can emit light, a drive reference voltage generation circuit that generates a drive reference voltage defining the upper limit value of the drive current and supplies the same to the driving circuit, and a specific external terminal capable of connecting to an external resistor. The drive reference voltage generation circuit operates selectively in a first mode to generate the drive reference voltage regardless of the state of the specific external terminal, or a second mode to generate the drive reference voltage in accordance with a second mode current through the specific external terminal.
Claims
1. A light emitting element drive device comprising: a driving circuit configured to supply a variable drive current to a light emitting unit including one or more light emitting elements, so that the light emitting unit can emit light; a drive reference voltage generation circuit configured to generate a drive reference voltage defining an upper limit value of the drive current, and supply the same to the driving circuit; and a specific external terminal, wherein the drive reference voltage generation circuit operates selectively in a first mode to generate the drive reference voltage regardless of the state of the specific external terminal, or a second mode to generate the drive reference voltage in accordance with a second mode current through the specific external terminal.
2. The light emitting element drive device according to claim 1, wherein an external resistor is connected or not between the specific external terminal and ground, outside the light emitting element drive device.
3. The light emitting element drive device according to claim 2, wherein when the drive reference voltage generation circuit operates in the second mode in a state where the external resistor is connected between the specific external terminal and the ground, the drive reference voltage generation circuit supplies the second mode current to the external resistor through the specific external terminal, so as to generate the drive reference voltage in accordance with a magnitude of the second mode current or the voltage generated by the external resistor.
4. The light emitting element drive device according to claim 3, wherein when the drive reference voltage generation circuit operates in the second mode in the state where the external resistor is connected between the specific external terminal and the ground, the drive reference voltage is higher than that in the first mode, depending on the resistance value of the external resistor, and the driving circuit increases the upper limit value of the drive current along with increase in the drive reference voltage.
5. The light emitting element drive device according to claim 1, wherein the drive reference voltage generation circuit includes a reference current generation circuit configured to generate a reference current commonly in the first mode and in the second mode, a current superimposing circuit configured to generate the second mode current only in the second mode out of the first and second modes, and a current mirror circuit configured to generate an output side current proportional to an input side current, so as to generate the drive reference voltage in proportion to the output side current, and in the first mode the input side current is equal to the reference current, while in the second mode the input side current is equal to the reference current plus the second mode current.
6. The light emitting element drive device according to claim 5, wherein the drive reference voltage generation circuit includes a switch inserted in series between an input terminal of the current mirror circuit and the specific external terminal, the light emitting element drive device further includes a switch control circuit configured to control the switch, and in the first mode the switch control circuit turns off the switch, while in the second mode it turns on the switch so as to superimpose the second mode current flowing through the specific external terminal on the input side current.
7. The light emitting element drive device according to claim 6, further comprising an abnormality detection circuit configured to detect whether or not the second mode current has an abnormality, on the basis of a magnitude of the second mode current flowing through the specific external terminal in the second mode, wherein if the abnormality detection circuit does not detect an abnormality in the second mode, the switch control circuit keeps turning on the switch, and if the abnormality detection circuit detects an abnormality in the second mode, the switch control circuit switches the switch from on to off, so that operation mode of the drive reference voltage generation circuit is changed from the second mode to the first mode.
8. The light emitting element drive device according to claim 1, wherein the drive reference voltage generation circuit includes a current generation circuit configured to generate a predetermined current, and an internal resistor, in the first mode the drive reference voltage generation circuit supplies the predetermined current to the internal resistor, so as to supply a voltage generated by the internal resistor as the drive reference voltage to the driving circuit, and in the second mode the drive reference voltage generation circuit supplies the predetermined current as the second mode current to the specific external terminal, so as to supply a voltage generated at the specific external terminal as the drive reference voltage to the driving circuit.
9. The light emitting element drive device according to claim 8, wherein the drive reference voltage generation circuit includes a first switch inserted in series between an output terminal of the current generation circuit and the internal resistor, and a second switch inserted in series between the output terminal of the current generation circuit and the specific external terminal, the light emitting element drive device further includes a switch control circuit configured to control the first switch and the second switch, and in the first mode the switch control circuit turns on the first switch and turns off the second switch, so that the predetermined current is supplied to the internal resistor, while in the second mode the switch control circuit turns off the first switch and turns on the second switch, so that the predetermined current is supplied as the second mode current to the specific external terminal.
10. The light emitting element drive device according to claim 9, further comprising an abnormality detection circuit configured to detect whether or not the drive reference voltage has an abnormality, on the basis of a voltage at the specific external terminal in the second mode, wherein if the abnormality detection circuit does not detect an abnormality in the second mode, the switch control circuit keeps turning off the first switch and keeps turning on the second switch, and if the abnormality detection circuit detects an abnormality in the second mode, the switch control circuit switches the first switch from off to on and switches the second switch from on to off, so that operation mode of the drive reference voltage generation circuit is changed from the second mode to the first mode.
11. The light emitting element drive device according to claim 1, wherein the driving circuit is disposed for each of a plurality of channels, and the drive reference voltage generation circuit generates the drive reference voltage for each channel.
12. A light emitting system comprising: the light emitting element drive device according to claim 1; and a light emitting unit to be driven and controlled by the light emitting element drive device.
Description
BRIEF DESCRIPTION OF DRAWINGS
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DESCRIPTION OF EMBODIMENTS
[0039] Hereinafter, an example of an embodiment of the present disclosure is described specifically with reference to the drawings. In the drawings to be referred to, the same part is denoted by the same numeral or symbol, and overlapping description of the same part is omitted as a rule. Note that in this specification, for simple description, a name of information, a signal, a physical quantity, an element, a part, or the like may be omitted or shortened by referring to a numeral or symbol representing the same. For instance, a drive reference voltage generation circuit denoted by 20A (see
[0040] First, some terms used for description of the embodiments of the present disclosure are defined below. A ground means a reference conductive part having a potential of 0 V (zero volts) to be a reference, or means the potential of 0 V itself. The reference conductive part is made of a conductor such as metal. The potential of 0 V may be referred to as a ground potential. In the embodiment of the present disclosure, a voltage without a specific reference means a potential from the ground. A level means a potential level, and high level has a higher potential than low level of any signal or voltage. For any signal or voltage, if the signal or voltage is at high level, it means that a level of the signal or voltage is at high level, and if the signal or voltage is at low level, it means that a level of the signal or voltage is at low level. A level of a signal may be referred to as a signal level, and a level of a voltage may be referred to as a voltage level. For any signal that can have a signal level at high level or low level, a period during which the signal level is at high level is referred to as a high level period, and a period during which the signal level is at low level is referred to as a low level period. The same is true for any voltage that can have a voltage level at high level or low level.
[0041] For any transistor constituted as a field effect transistor (FET) including a MOSFET, an ON state means a state where the transistor is conducting between drain and source, while an OFF state means a state where the transistor is not conducting between drain and source (a cutoff state). The same is true for other transistors that are not classified into the FET. The MOSFET is understood as an enhancement type MOSFET unless otherwise noted. The MOSFET is abbreviation of metal-oxide-semiconductor field-effect transistor.
[0042] Any switch can be constituted using one or more field effect transistors (FETs). If a switch is in the ON state, the switch is conducting between its terminals. If a switch is in the OFF state, the switch is not conducting between its terminals. In the following description, for any transistor or switch, the ON state and the OFF state may be simply referred to as ON and OFF, respectively.
[0043]
[0044] Each of the light emitting units LL is constituted of one or more light emitting diodes (LEDs). For instance, the light emitting unit LL is constituted of a plurality of LEDs connected in series. However, the light emitting unit LL may be a plurality of LEDs connected in parallel. Further, connections in series and in parallel of a plurality of LEDs may be mixed in the single light emitting unit LL. It may be possible that a single LED constitute the single light emitting unit LL. Each of the light emitting units LL has a high potential terminal and a low potential terminal, and each LED constituting the light emitting unit LL has a forward direction from the high potential terminal to the low potential terminal.
[0045] The LED driver 1 has n terminals CH. Each terminal CH is a light emitting unit connection terminal to be connected to the light emitting unit LL. The high potential terminal of each light emitting unit LL is applied with a power supply voltage V.sub.POW that is a positive DC voltage, and the low potential terminal of each light emitting unit LL is connected to the corresponding terminal CH. A current flowing in each light emitting unit LL is referred to as a drive current I.sub.LED.
[0046] The LED driver 1 is an electronic component (semiconductor device) formed by sealing a semiconductor integrated circuit in a case (package) as illustrated in
[0047] An input voltage V.sub.IN is supplied to the terminal IN from outside of the LED driver 1. The input voltage V.sub.IN is supposed to be a positive DC voltage. The LED driver 1 is driven based on the input voltage V.sub.IN. The terminal GND is connected to the ground. The terminal FAILB is connected to the MPU 2 via the wiring 3. The MPU 2 operates based on a power supply voltage VCC that is a predetermined positive DC voltage. The wiring 3 that connects the terminal FAILB and the MPU 2 is connected to an application terminal of the power supply voltage VCC (a terminal applied with the power supply voltage VCC) via the pull-up resistor R.sub.PU. In addition, the MPU 2 is connected to the terminal COM as a communication terminal via the communication wiring 4. The LED driver 1 and the MPU 2 can communicate with each other in a bidirectional manner via the communication wiring 4. Although
[0048] With reference to
[0049] Note that the LED driver 1 may have a DC/DC converter function of generating the power supply voltage V.sub.POW from the input voltage V.sub.IN. The DC/DC converter may control the voltage value of the power supply voltage V.sub.POW based on voltages at the terminals CH[1] to CH[n], for example. The circuit that generates the power supply voltage V.sub.POW may be another circuit disposed separately from the LED driver 1.
[0050]
[0051] The driving circuits 10[1] to 10[n] are connected to the terminals CH[1] to CH[n], respectively. Drive control signals including control signals S.sub.PWM[1] to S.sub.PWM[n] and S.sub.DC[1] to S.sub.DC[n] are supplied to the driving circuits 10[1] to 10[n] from the control circuit 30, and the driving circuits 10[1] to 10[n] can drive the light emitting units LL[1] to LL[n] by PWM drive or DC drive, respectively, on the basis of the drive control signals.
[0052] When performing the PWM drive, the driving circuit 10[i] drives the corresponding light emitting unit LL[i] to emit pulse light by PWM control based on the control signal S.sub.PWM[i], and controls the magnitude of the drive current I.sub.LED[i] when the drive current I.sub.LED[i] is flowing, in a plurality of steps based on the control signal S.sub.DC[i]. When performing the DC drive, the driving circuit 10[i] continuously supplies the drive current I.sub.LED[i] to the light emitting unit LL[i], so that the light emitting unit LL[i] continuously emit light, and in this case, controls the magnitude of the drive current I.sub.LED[i] in a plurality of steps based on the control signal S.sub.DC[i].
[0053] The drive reference voltage generation circuit 20 supplies a drive reference voltage V.sub.DREF to each driving circuit 10. The drive reference voltage V.sub.DREF determines the upper limit value of the drive current I.sub.LED[i]. In other words, the driving circuit 10[i] controls the magnitude of the drive current I.sub.LED[i] when the drive current I.sub.LED[i] is flowing in a plurality of steps based on the control signal S.sub.DC[i], and the upper limit of the magnitude of the drive current I.sub.LED[i] is determined depending on the drive reference voltage V.sub.DREF (a specific structural example to realize this control is described later). The drive reference voltage V.sub.DREF may be generated for each driving circuit 10, or the single common drive reference voltage V.sub.DREF may be generated for the driving circuits 10[1] to 10[n].
[0054] The control circuit 30 controls the drive reference voltage generation circuit 20 and each driving circuit 10. The control circuit 30 generates the drive control signals including the control signals S.sub.PWM[1] to S.sub.PWM[n] and S.sub.DC[1] to S.sub.DC[n] based on a signal from the MPU 2. Specifically, for example, the MPU 2 supplies a drive condition setting signal to the LED driver 1 through the communication wiring 4, and drive setting data based on the drive condition setting signal is stored in the data holding unit 50 (see
[0055]
[0056] When the driving circuit 10[i] performs the DC drive, the drive current I.sub.LED[i] having the current value I.sub.VAL[i] flows continuously. The DC drive by the driving circuit 10[i] is equivalent that the ON duty ratio of the i-th channel is 100%. When the driving circuit 10[i] performs the DC drive, it can be considered that the control signal S.sub.PWM[i] is continuously maintained at high level.
[0057] The abnormality detection circuit 40 detects presence or absence of an abnormality related to the LED driver 1. Abnormalities to be detected by the abnormality detection circuit 40 include a temperature abnormality that the LED driver 1 has too high temperature, an input voltage abnormality that the input voltage V.sub.IN is too low or too high, and an abnormality related to the terminal EX.sub.ISET (details are described later). If no abnormality is detected by the abnormality detection circuit 40, the abnormality detection circuit 40 makes the terminal FAILB be in a high impedance state so as to maintain the level of the wiring 3 at high level. If the abnormality detection circuit 40 detects any abnormality, the abnormality detection circuit 40 cooperates with the pull-up resistor R.sub.PU to make the terminal FAILB be at low level. For instance, an open drain FET is provided to the LED driver 1, and the drain of the FET is connected to the terminal FAILB. Then, the abnormality detection circuit 40 controls a gate potential of the FET based on the result of detection of presence or absence of an abnormality. The MPU 2 can determine presence or absence of an abnormality related to the LED driver 1 by monitoring the level of the wiring 3.
[0058] As illustrated in
[0059] The internal voltage generation circuit 60 generates one or more predetermined internal voltage based on the input voltage V.sub.IN. Each circuit constituting the LED driver 1 operates based on the voltage generated by the internal voltage generation circuit 60.
[0060] Hereinafter, in a plurality of examples, some specific structural examples, applied techniques, modified techniques, and the like about the light emitting system SYS are described. The matters described above in the embodiment are applied to the examples described below unless otherwise noted and as long as no contradiction occurs. If there is a contradiction between the matter described above and description in the following example, the description in the following example may be prioritized. In addition, as long as no contradiction occurs among the plurality of examples described below, a matter described in any example can be applied to any other example (i.e. any two or more examples can be combined among the plurality of examples).
First Example
[0061] A first example is described.
[0062] In the LED driver 1A, the driving circuits 10[1] to 10[n] have the same internal structure, and each driving circuit 10 includes a transistor 11 constituted as an N-channel MOSFET, an amplifier 12 as an operational amplifier, and a resistor 13. The driving circuit 10[i] is connected to the terminal CH[i]. Note that, to avoid complicated illustration,
[0063] In each driving circuit 10, a drain of the transistor 11 is connected to the corresponding terminal CH. Therefore, the drain of the transistor 11 in the driving circuit 10[i] is connected to the terminal CH[i]. In each driving circuit 10, a source of the transistor 11 is connected to the ground through the resistor 13, an output terminal of the amplifier 12 is connected to a gate of the transistor 11, and a noninverting input terminal of the amplifier 12 is applied with the drive reference voltage V.sub.DREF supplied from the circuit 20A. In each driving circuit 10, a connection node between the source of the transistor 11 and the resistor 13 is connected to an inverting input terminal of the amplifier 12.
[0064] In each driving circuit 10, the resistor 13 is constituted as a variable resistor. In the driving circuit 10[i], the resistance of the resistor 13 connected to the inverting input terminal of the amplifier 12 is set in a variable manner based on the control signal S.sub.DC[i], and hence the magnitude of the drive current I.sub.LED[i] when the transistor 11 is not in the OFF state is set in a variable manner, via gate potential control of the transistor 11 by the amplifier 12. Note that in this embodiment, resistors other than the resistor 13 can be understood to be fixed resistors each of which has a fixed resistance value, unless otherwise noted.
[0065] In addition, although not clear in
[0066] In order to realize this control, for example, in the driving circuit 10[i], a switch (not shown) is inserted between the output terminal of the amplifier 12 and the gate of the transistor 11, and only during the high level period of the control signal S.sub.PWM[i], the switch between the output terminal of the amplifier 12 and the gate of the transistor 11 is turned on. Note that in reality, the transistor 11 can be constituted of a plurality of FETs, and the resistor 13 can be constituted of a plurality of resistors. In this way, the resistance of the resistor 13 disposed between the source of the transistor 11 and the ground can be variable.
[0067] When the output voltage of the amplifier 12 is supplied to the gate of the transistor 11 in the driving circuit 10[i], the amplifier 12 controls the gate potential of the transistor 11 so that a voltage difference between the noninverting input terminal and the inverting input terminal thereof will be zero, and hence the light emitting unit LL[i] is supplied with the drive current I.sub.LED[i] depending on the resistance of the resistor 13 connected to the inverting input terminal of the amplifier 12.
[0068] When the driving circuit 10[i] performs the DC drive, the current value I.sub.VAL[i] of the drive current I.sub.LED[i] (see
[0069] In the driving circuit 10[i], the resistance of the resistor 13 is set in a variable manner in a plurality of steps within a predetermined variable resistance range, and in conjunction with this, the current value I.sub.VAL[i] is set in a variable manner in a plurality of steps within a predetermined variable current range. In the driving circuit 10[i], when the resistance of the resistor 13 is equal to the minimum value of the variable resistance range, the current value I.sub.VAL[i] is maximized, and the current value I.sub.VAL[i] decreases along with increase in the resistance of the resistor 13.
[0070] When the minimum value of the variable resistance range is denoted by R13.sub.MIN, the upper limit value of the drive current I.sub.LED[i] (i.e. the current value I.sub.VAL[i] when the resistance of the resistor 13 is equal to the minimum value of the variable resistance range) depends on the drive reference voltage V.sub.DREF and is expressed by V.sub.DREF/R13.sub.MIN. When the driving circuit 10[i] performs the DC drive, the upper limit value of the drive current I.sub.LED[i] indicates the upper limit of the value of the drive current I.sub.LED[i] that flows continuously. When the driving circuit 10[i] performs the PWM drive, the upper limit value of the drive current I.sub.LED[i] indicates the upper limit of the instantaneous value of the drive current I.sub.LED[i] when the drive current I.sub.LED[i] is flowing (i.e. the upper limit of the instantaneous value of the drive current I.sub.LED[i] during the high level period of the control signal S.sub.PWM[i]).
[0071] The drive reference voltage generation circuit 20A has a variable setting function of the drive reference voltage V.sub.DREF that defines the upper limit value of the drive current I.sub.LED[i]. The drive reference voltage generation circuit 20A includes a resistor 100 that is an internal resistor for generating the drive reference voltage, a reference current generation circuit 110, a current superimposing circuit 120, a current mirror circuit 130, a reference voltage generation unit 140, and a switch 150.
[0072] The reference current generation circuit 110 includes a transistor 111 constituted as an N-channel MOSFET, an amplifier 112 that is an operational amplifier, and a resistor 113. A drain of the transistor 111 is connected to an input terminal 131 of the current mirror circuit 130, and a source of the transistor 111 is connected to the ground through the resistor 113. A gate of the transistor 111 is connected to an output terminal of the amplifier 112. The connection node between the source of the transistor 111 and the resistor 113 is connected to an inverting input terminal of the amplifier 112. A noninverting input terminal of the amplifier 112 is applied with a predetermined reference voltage V.sub.REF (e.g. 0.6 V). Therefore, a reference current I.sub.REF determined by the resistance of the resistor 113 and the voltage value of the reference voltage V.sub.REF flows between drain and source of the transistor 111.
[0073] The current superimposing circuit 120 includes a transistor 121 constituted as an N-channel MOSFET, and an amplifier 122 that is an operational amplifier. A drain of the transistor 121 is connected to one terminal of the switch 150, and the other terminal of the switch 150 is connected to the input terminal 131 of the current mirror circuit 130. In other words, the switch 150 is inserted in series between the drain of the transistor 121 and the input terminal 131. A source of the transistor 121 is connected to the terminal EX.sub.ISET through the sense resistor R.sub.SNS. A gate of the transistor 121 is connected to the output terminal of the amplifier 122. The source of the transistor 121 is connected to an inverting input terminal of the amplifier 122. A noninverting input terminal of the amplifier 122 is applied with the predetermined reference voltage V.sub.REF.
[0074] The current mirror circuit 130 has an input terminal 131 and an output terminal 132, and outputs from the output terminal 132 an output side current I.sub.OUT_A that is k.sub.A times an input side current I.sub.IN_A flowing through the input terminal 131. Here, k.sub.A is any real number and may be 1. The output terminal 132 is connected to one end of the resistor 100, and the other end of the resistor 100 is connected to the ground. In addition, the output terminal 132 is connected to the noninverting input terminal of the amplifier 12 in each of the driving circuits 10[1] to 10[n]. Therefore, the voltage generated across the resistor 100 when the output side current I.sub.OUT_A flows through the resistor 100 becomes the drive reference voltage V.sub.DREF.
[0075] The reference voltage generation unit 140 generates the reference voltage V.sub.REF having a predetermined positive DC voltage value. The reference voltage generation unit 140 can be understood to be a component of the circuits 110 and 120, which is shared between the circuits 110 and 120.
[0076] The mode control circuit 30A is a part of the control circuit 30 illustrated in
[0077] When the external resistor abnormality flag has a value of 0, the mode control circuit 30A operates the circuit 20A in a mode MD.sub.A1 if the mode setting value is 1, while it operates the same in a mode MD.sub.A2 if the mode setting value is 2. When the external resistor abnormality flag has a value of 1, the mode control circuit 30A operates the circuit 20A in the mode MD.sub.A1 regardless of the mode setting value.
[0078] When operating the circuit 20A in the mode MD.sub.A1, the mode control circuit 30A maintains the switch 150 in the OFF state. When operating the circuit 20A in the mode MD.sub.A2, the mode control circuit 30A maintains the switch 150 in the ON state. Therefore, the mode control circuit 30A can be said to be a switch control circuit that controls the state of the switch 150 based on the mode setting value.
[0079] The mode MD.sub.A1 is a mode to generate the drive reference voltage V.sub.DREF regardless of the state of the terminal EX.sub.ISET. In other words, in the mode MD.sub.A1, the switch 150 is turned off, and hence the constant drive reference voltage V.sub.DREF is generated regardless of whether or not the terminal EX.sub.ISET is connected to the external resistor R.sub.EX_A, or whether or not the terminal EX.sub.ISET is short-circuited to the ground, or whether or not the terminal EX.sub.ISET is applied with any voltage.
[0080] The mode MD.sub.A2 is a mode that functions significantly in the state with the external resistor, and is a mode to generate the drive reference voltage V.sub.DREF in accordance with the current flowing through the terminal EX.sub.ISET (a second mode current).
[0081] The abnormality detection circuit 40A is a part of the abnormality detection circuit 40 illustrated in
[0082] The mode control circuit 30A controls the value of the external resistor abnormality flag (see
[0083] The case where the circuit 20A operates in the mode MD.sub.A1 is referred to as a case CS.sub.A1. In the case CS.sub.A1, the switch 150 is turned off, and hence the input side current I.sub.IN_A is equal to the reference current I.sub.REF. The case where the circuit 20A operates in the mode MD.sub.A2 in the state with the external resistor is referred to as a case CS.sub.A2. In the case CS.sub.A2, the switch 150 is turned on, and hence the input side current I.sub.IN_A is equal to the sum of the reference current I.sub.REF and the current I.sub.EX_A that flows through the terminal EX.sub.ISET and the external resistor R.sub.EX_A. Therefore, the drive reference voltage V.sub.DREF in the case CS.sub.A2 is higher than that in the case CS.sub.A1. As a result, the upper limit value of the drive current I.sub.LED[i] in each driving circuit 10 is higher in the case CS.sub.A2 than that in the case CS.sub.A1. The upper limit value of the drive current I.sub.LED[i] in the case CS.sub.A2 is determined depending on the magnitude of the current I.sub.EX_A (therefore depending on the resistance value of the external resistor R.sub.EX_A).
[0084] Hereinafter, the operation of the LED driver 1A is summarized. The drive reference voltage generation circuit 20A operates selectively in the mode MD.sub.A1 to generate the drive reference voltage V.sub.DREF regardless of the state of the terminal EX.sub.ISET, or in the mode MD.sub.A2 to generate the drive reference voltage V.sub.DREF in accordance with the current I.sub.EX_A through the terminal EX.sub.ISET (the second mode current).
[0085] As described above, outside the LED driver 1A, the external resistor R.sub.EX_A is connected or not between the terminal EX.sub.ISET and the ground. When the circuit 20A operates in the mode MD.sub.A2 in the state where the external resistor R.sub.EX_A is connected between the terminal EX.sub.ISET and the ground, the circuit 20A supplies the current I.sub.EX_A to the external resistor R.sub.EX_A through the terminal EX.sub.ISET, and generates the drive reference voltage V.sub.DREF in accordance with the magnitude of the current I.sub.EX_A at that time. In this case, the drive reference voltage V.sub.DREF when the circuit 20A operates in the mode MD.sub.A2 in the state where the external resistor REXA is connected between the terminal EX.sub.ISET and the ground depends on the resistance value of the external resistor R.sub.EX_A, and is higher than the drive reference voltage V.sub.DREF in the mode MD.sub.A1. Along with the increase in the drive reference voltage V.sub.DREF, the driving circuit 10[i] increases the upper limit value of the drive current I.sub.LED[i]. In this way, the upper limit value of the drive current I.sub.LED[i] can be increased in the mode MD.sub.A2.
[0086] The drive reference voltage generation circuit 20A includes the reference current generation circuit 110 that generates the reference current I.sub.REF commonly in the mode MD.sub.A1 and in the mode MD.sub.A2, the current superimposing circuit 120 that generates the current I.sub.EX_A only in the mode MD.sub.A2 out of the mode MD.sub.A1 and the mode MD.sub.A2, and the current mirror circuit 130 that generates the output side current I.sub.OUT_A proportional to the input side current I.sub.IN_A, and it generates the drive reference voltage V.sub.DREF in proportion to the output side current I.sub.OUT_A. In the mode MD.sub.A1, the input side current I.sub.IN_A is equal to the reference current I.sub.REF, while in the mode MD.sub.A2, the input side current I.sub.IN_A is equal to the reference current I.sub.REF plus the current I.sub.EX_A.
[0087] The drive reference voltage generation circuit 20A includes the switch 150 inserted in series between the input terminal 131 of the current mirror circuit 130 and the terminal EX.sub.ISET. The LED driver 1A further includes the switch control circuit (30A) that controls the switch 150. The switch control circuit (30A) turns off the switch 150 in the mode MD.sub.A1, while it turns on the switch 150 in the mode MD.sub.A2, so as to superimpose the current I.sub.EX_A flowing through the terminal EX.sub.ISET on the input side current I.sub.IN_A.
[0088] The abnormality detection circuit 40A detects whether or not the current I.sub.EX_A has an abnormality based on the magnitude of the current I.sub.EX_A flowing through the terminal EX.sub.ISET in the mode MD.sub.A2. The switch control circuit (30A) keeps turning on the switch 150 if the abnormality detection circuit 40A does not detect an abnormality in the mode MD.sub.A2 (if the value of the external resistor abnormality flag is 0). If the abnormality detection circuit 40A detects an abnormality in the mode MD.sub.A2 (if the value of the external resistor abnormality flag is 1), the switch control circuit (30A) switches the switch 150 from on to off, so that the operation mode of the circuit 20A transfers from the mode MD.sub.A2 to the mode MD.sub.A1.
[0089] When considering heating or the like of the light emitting unit LL or the transistor 11, an appropriate upper limit of the drive current I.sub.LED[i] should be determined. On the other hand, if the external resistor R.sub.EX_A is essential for setting the upper limit, the number of components of the light emitting system SYS is increased. Therefore, in order to avoid the increase in the number of components, the mode MD.sub.A1 is provided, in which the appropriate upper limit of the drive current I.sub.LED[i] is determined without requiring the external resistor R.sub.EX_A.
[0090] However, depending on the light emitting system SYS, it may be requested to increase the upper limit of the drive current I.sub.LED[i]. Considering this, the LED driver 1A adopts the structure that supports the request that requires the external resistor R.sub.EX_A. The operation in the mode MD.sub.A2 with the external resistor R.sub.EX_A can realize increase in the upper limit of the drive current I.sub.LED[i]. In this way, to satisfy a request in the light emitting system SYS, the single LED driver 1A can be used both as a LED driver having the upper limit value of the drive current I.sub.LED[i] that is a first upper limit value (e.g. 60 mA), and as a LED driver having the upper limit value of the drive current I.sub.LED[i] that is a second upper limit value (e.g. 125 mA) higher than the first upper limit value. In other words, it is possible to provide the LED driver having high versatility in the upper limit of the drive current.
[0091] However, in such a case where the terminal EX.sub.ISET is short-circuited to the ground in the mode MD.sub.A2, if the current I.sub.EX_A becomes too large, the upper limit value of the drive current I.sub.LED[i] also becomes too large, and the light emitting unit LL[i] and the transistor 11 may be in an overcurrent state. By providing the abnormality detection circuit 40A, they can be prevented from being in the overcurrent state.
[0092] As the light emitting system SYS, it is possible to realize selectively a first light emitting system that operates in the mode MD.sub.A1 without the external resistor R.sub.EX_A, or a second light emitting system that operates in the mode MD.sub.A2 with the external resistor R.sub.EX_A. In the first light emitting system, the operation of the current superimposing circuit 120 is not necessary. Therefore, when the circuit 20A operates in the mode MD.sub.A1, the mode control circuit 30A cuts off power supply to the amplifier 122 in conjunction with the switch 150 turned off, so as to stop the operation of the current superimposing circuit 120. Therefore, wasteful power consumption does not occur in the light emitting system SYS operated as the first light emitting system. On a circuit board where electronic components of the first light emitting system are mounted, the terminal EX.sub.ISET may be short-circuited to the ground depending on the design thereof. However, as long as it operates in the mode MD.sub.A1, the switch 150 and the transistor 121 are both turned off, and hence leak current through them is so small that it can be ignored, and there is no problem. In the current superimposing circuit 120, a pull-down resistor may be disposed between the gate of the transistor 121 and the ground.
Second Example
[0093] A second example is described. In the second example, a modified technique that can be applied to the first example is described. In the structure of
[0094] The generation of the drive reference voltage V.sub.DREF for each channel in the LED driver 1A can be performed as follows. Specifically, as illustrated in
[0095] Note that it may be possible to group the first to n-th channels into two or more blocks in the LED driver 1A, and to generate the drive reference voltage V.sub.DREF for each of the blocks. Each block includes two or more channels.
Third Example
[0096] A third example is described.
[0097] The internal structure and operation of each driving circuit 10 in the LED driver 1B are the same as those in the LED driver 1A (i.e. the same as described above in the first example). The matter described above for the driving circuit 10 and the drive current I.sub.LED in the first example is all applied to the third example. Note that to avoid complicated illustration,
[0098] The drive reference voltage generation circuit 20B has the variable setting function of the drive reference voltage V.sub.DREF that defines the upper limit value of the drive current I.sub.LED[i]. The drive reference voltage generation circuit 20B includes a resistor 200 that is an internal resistor for generating the drive reference voltage, a reference current generation circuit 210, a current mirror circuit 230, a reference voltage generation unit 240, and switches 251 and 252.
[0099] The reference current generation circuit 210 includes a transistor 211 constituted as an N-channel MOSFET, an amplifier 212 that is an operational amplifier, and a resistor 213. A drain of the transistor 211 is connected to an input terminal 231 of the current mirror circuit 230, and a source of the transistor 211 is connected to the ground through the resistor 213. A gate of the transistor 211 is connected to an output terminal of the amplifier 212. The connection node between the source of the transistor 211 and the resistor 213 is connected to an inverting input terminal of the amplifier 212. A noninverting input terminal of the amplifier 212 is applied with the predetermined reference voltage V.sub.REF (e.g. 0.6 V). Therefore, the reference current I.sub.REF determined by the resistance of the resistor 213 and the voltage value of the reference voltage V.sub.REF flows between drain and source of the transistor 211.
[0100] The current mirror circuit 230 has an input terminal 231 and an output terminal 232, and outputs from the output terminal 232 an output side current I.sub.OUT_B that is k.sub.B times an input side current I.sub.IN_B flowing through the input terminal 231. Here, k.sub.B is any real number and may be 1. In the LED driver 1B, the input side current I.sub.IN_B is always equal to the reference current I.sub.REF by the reference current generation circuit 210. The output terminal 232 is connected commonly to one end of the switch 251 and to one end of the switch 252. The other end of the switch 251 is connected to the ground through the resistor 200, and the other end of the switch 252 is connected to the terminal EX.sub.ISET. In addition, the output terminal 232 is connected to the noninverting input terminal of the amplifier 12 in each of the driving circuits 10[1] to 10[n].
[0101] The reference voltage generation unit 240 generates the reference voltage V.sub.REF having a predetermined positive DC voltage value. The reference voltage generation unit 240 can be understood to be a component of the reference current generation circuit 210.
[0102] The mode control circuit 30B is a part of the control circuit 30 illustrated in
[0103] When the external resistor abnormality flag has a value of 0, the mode control circuit 30B operates the circuit 20B in a mode MD.sub.B1 if the mode setting value is 1, while it operates the same in a mode MD.sub.B2 if the mode setting value is 2. When the external resistor abnormality flag has a value of 1, the mode control circuit 30B operates the circuit 20B in the mode MD.sub.B1 regardless of the mode setting value.
[0104] When operating the circuit 20B in the mode MD.sub.B1, the mode control circuit 30B maintains the switch 251 in the ON state and the switch 252 in the OFF state. When operating the circuit 20B in the mode MD.sub.B2, the mode control circuit 30B maintains the switch 251 in the OFF state and the switch 252 in the ON state. Therefore, the mode control circuit 30B can be said to be a switch control circuit that controls the states of the switches 251 and 252 based on the mode setting value.
[0105] The mode MD.sub.B1 is a mode to generate the drive reference voltage V.sub.DREF regardless of the state of the terminal EX.sub.ISET. In other words, in the mode MD.sub.B1, the switch 251 is turned on while the switch 252 is turned off, and hence the constant drive reference voltage V.sub.DREF is generated regardless of whether or not the terminal EX.sub.ISET is connected to the external resistor R.sub.EX_B, or whether or not the terminal EX.sub.ISET is short-circuited to the ground, or whether or not the terminal EX.sub.ISET is applied with any voltage. In the mode MD.sub.B1, the drive reference voltage V.sub.DREF is a voltage generated across the resistor 200 when the output side current I.sub.OUT_B flows through the resistor 200.
[0106] The mode MD.sub.B2 is a mode that functions significantly in the state with the external resistor, and is a mode to generate the drive reference voltage V.sub.DREF in accordance with the current flowing through the terminal EX.sub.ISET (a second mode current). In the mode MD.sub.B2, the drive reference voltage V.sub.DREF is a voltage at the terminal EX.sub.ISET. If the external resistor R.sub.EX_B is disposed between the terminal EX.sub.ISET and the ground in the mode MD.sub.B2, the drive reference voltage V.sub.DREF is a voltage generated across the external resistor R.sub.EX_B when the output side current I.sub.OUT_B flows through the external resistor R.sub.EX_B.
[0107] The abnormality detection circuit 40B is a part of the abnormality detection circuit 40 illustrated in
[0108] The mode control circuit 30B controls the value of the external resistor abnormality flag (see
[0109] The case where the circuit 20B operates in the mode MD.sub.B1 is referred to as a case CS.sub.B1. In the case CS.sub.B1, the switch 251 is turned on while the switch 252 is turned off, and hence the drive reference voltage V.sub.DREF is determined by the values of the output side current I.sub.OUT_B and the resistor 200. The case where the circuit 20B operates in the mode MD.sub.B2 in the state with the external resistor is referred to as a case CS.sub.B2. In the case CS.sub.B2, the switch 251 is turned off while the switch 252 is turned on, and hence the drive reference voltage V.sub.DREF is determined by the values of the output side current I.sub.OUT_B and the external resistor R.sub.EX_B. In the case CS.sub.B2, except for an abnormal state, the external resistor R.sub.EX_B having a resistance value larger than that of the resistor 200 is used. Therefore, the drive reference voltage V.sub.DREF in the case CS.sub.B2 is higher than that in the case CS.sub.B1. As a result, the upper limit value of the drive current I.sub.LED[i] in each driving circuit 10 in the case CS.sub.B2 is higher than that in the case CS.sub.B1. The upper limit value of the drive current I.sub.LED[i] in the case CS.sub.B2 is determined depending on the resistance value of the external resistor R.sub.EX_B.
[0110] Hereinafter, the operation of the LED driver 1B is summarized. The drive reference voltage generation circuit 20B operates selectively in the mode MD.sub.B1 to generate the drive reference voltage V.sub.DREF regardless of the state of the terminal EX.sub.ISET, or in the mode MD.sub.B2 to generate the drive reference voltage V.sub.DREF in accordance with the current I.sub.EX_B through the terminal EX.sub.ISET (the second mode current).
[0111] As described above, outside the LED driver 1B, the external resistor R.sub.EX_B is connected or not between the terminal EX.sub.ISET and the ground. When the circuit 20B operates in the mode MD.sub.B2 in the state where the external resistor R.sub.EX_B is connected between the terminal EX.sub.ISET and the ground, the circuit 20B supplies the current I.sub.EX_B to the external resistor R.sub.EX_B through the terminal EX.sub.ISET, and generates the drive reference voltage V.sub.DREF in accordance with the voltage generated by the external resistor R.sub.EX_B at that time. In this case, the drive reference voltage V.sub.DREF when the circuit 20B operates in the mode MD.sub.B2 in the state where the external resistor R.sub.EX_B is connected between the terminal EX.sub.ISET and the ground depends on the resistance value of the external resistor R.sub.EX_B, and is higher than the drive reference voltage V.sub.DREF in the mode MD.sub.B1. Along with increase in the drive reference voltage V.sub.DREF, the driving circuit 10[i] increases the upper limit value of the drive current I.sub.LED[i]. In this way, the upper limit value of the drive current I.sub.LED[i] can be increased in the mode MD.sub.B2.
[0112] The drive reference voltage generation circuit 20B includes the current mirror circuit 230 that generates the output side current I.sub.OUT_B proportional to the input side current I.sub.IN_B, and the resistor 200 that is an internal resistor. In the mode MD.sub.B1, it supplies the output side current I.sub.OUT_B to the resistor 200 so as to supply the voltage generated by the resistor 200 as the drive reference voltage V.sub.DREF to the driving circuit 10[i]. In the mode MD.sub.B2, it supplies the output side current I.sub.OUT_B as the current I.sub.EX_B to the terminal EX.sub.ISET so as to supply the voltage at the terminal EX.sub.ISET as the drive reference voltage V.sub.DREF to the driving circuit 10[i]. The current mirror circuit 230 is an example of the current generation circuit, and the output side current I.sub.OUT_B is an example of the predetermined current generated by the current generation circuit. In the present disclosure, the current generation circuit is not necessarily the current mirror circuit.
[0113] The drive reference voltage generation circuit 20B includes the switch 251 inserted in series between the output terminal 232 of the current mirror circuit 230 (the output terminal of the current generation circuit) and the resistor 200, and the switch 252 inserted in series between the output terminal 232 of the current mirror circuit 230 (the output terminal of the current generation circuit) and the terminal EX.sub.ISET. The LED driver 1B further includes the switch control circuit (30B) that controls the switch 251 and the switch 252. In the mode MD.sub.B1, the switch control circuit (30B) turns on the switch 251 and turns off the switch 252, so as to supply the output side current I.sub.OUT_B to the resistor 200. In the mode MD.sub.B2, it turns off the switch 251 and turns on the switch 252, so as to output the side current I.sub.OUT_B as the current I.sub.EX_B to the terminal EX.sub.ISET.
[0114] In addition, the LED driver 1B further includes the abnormality detection circuit 40B that detects whether or not the drive reference voltage V.sub.DREF has an abnormality, on the basis of the voltage at the terminal EX.sub.ISET in the mode MD.sub.B2. If the abnormality detection circuit 40B does not detect an abnormality in the mode MD.sub.B2 (if the value of the external resistor abnormality flag is 0), the switch control circuit (30B) keeps turning off the switch 251 and turning on the switch 252. If the abnormality detection circuit 40B detects an abnormality in the mode MD.sub.B2 (if the value of the external resistor abnormality flag is 1), it switches the switch 251 from off to on and switches the switch 252 from on to off, so as to transfer the operation mode of the circuit 20B from the mode MD.sub.B2 to the mode MD.sub.B1.
[0115] The structure of the third example can provide the same action and effect as the structure of the first example. In other words, to satisfy the request in the light emitting system SYS, the single LED driver 1B can function both as the LED driver having the upper limit value of the drive current I.sub.LED[i] that is the first upper limit value, and as the LED driver having the upper limit value of the drive current I.sub.LED[i] that is the second upper limit value higher than the first upper limit value. In other words, it is possible to provide the LED driver having high versatility in the upper limit of the drive current.
[0116] However, if the drive reference voltage V.sub.DREF becomes too small or too large in such a case where the terminal EX.sub.ISET is short-circuited or opened in the mode MD.sub.B2, the upper limit value of the drive current I.sub.LED[i] becomes inappropriate. By disposing the abnormality detection circuit 40B, it is possible to prevent the light emitting unit LL[i] from being operated in such an inappropriate state.
Fourth Example
[0117] A fourth example is described. In the fourth example, a modified technique that can be applied to the third example is described. In the structure of
[0118] Generation of the drive reference voltage V.sub.DREF for each channel in the LED driver 1B can be performed as follows. Specifically, as illustrated in
[0119] Then, the first to n-th channels of the output terminals 232 are connected to one ends of the first to n-th channels of the resistors 200 through the first to n-th channels of the switches 251, respectively. The other ends of the first to n-th channels of the resistors 200 are all connected to the ground. The first to n-th channels of the resistors 200 have the same resistance value. In addition, the first to n-th channels of the output terminals 232 are connected to the first to n-th channels of the terminals EX.sub.ISET through the first to n-th channels of the switches 252, respectively.
[0120] When operating the circuit 20B in the mode MD.sub.B1, the mode control circuit 30B turns on the first to n-th channels of the switches 251 and turns off the first to n-th channels of the switches 252. When operating the circuit 20B in the mode MD.sub.B2, it turns off the first to n-th channels of the switches 251 and turns on the first to n-th channels of the switches 252. When the circuit 20B operates in the mode MD.sub.B2, the first to n-th channels of the external resistors R.sub.EX_B are connected between the ground and the first to n-th channels of the terminals EX.sub.ISET, respectively, outside the LED driver 1B (the external resistor R.sub.EX_B is not illustrated in
[0121] In this way, in the mode MD.sub.B1, the first to n-th channels of the resistors 200 generate the first to n-th channels of the drive reference voltages V.sub.DREF, respectively. In the mode MD.sub.B2, the voltages at the first to n-th channels of the terminals EX.sub.ISET (i.e. the voltages generated by the first to n-th channels of the external resistors R.sub.EX_B) are the first to n-th channels of the drive reference voltages V.sub.DREF, respectively. The noninverting input terminals of the amplifiers 12 in the driving circuits 10[1] to 10[n] (i.e. the first to n-th channels of the driving circuits 10) are connected to the first to n-th channels of the output terminals 232, respectively. In this way, the noninverting input terminals of the amplifiers 12 in the driving circuits 10[1] to 10[n] are supplied with the first to n-th channels of the drive reference voltages V.sub.DREF, respectively.
[0122] As illustrated in
[0123] Note that in the LED driver 1B, it may be possible to group the first to n-th channels into two or more blocks, and to generate the drive reference voltage V.sub.DREF for each block. Each block includes two or more channels.
Fifth Example
[0124] A fifth example is described. The light emitting system SYS may be mounted in a vehicle such as an automobile. In this case, any lighting device mounted in a vehicle can be constituted of the light emitting system SYS. The lighting device constituted of the light emitting system SYS can be any lighting device mounted in a vehicle, such as a headlamp, a tail lamp, a brake lamp (stop lamp), or a direction indicator of the vehicle.
[0125] For instance, when constituting a brake lamp of a vehicle using the light emitting system SYS, it is considered to use the mode MD.sub.A2 or MD.sub.B2 described in one of the first to fourth examples, in order to improve luminance of the brake lamp. In this case, suppose that an abnormality has occurred in a part of the terminal EX.sub.ISET, and hence the high level detection result signal S.sub.DET_A or S.sub.DET_B is output from the abnormality detection circuit 40A or 40B. When the abnormality has occurred, to continue setting the drive reference voltage V.sub.DREF in the mode MD.sub.A2 or MD.sub.B2 is not appropriate. However, even if a part of the terminal EX.sub.ISET has an abnormality, to set the drive current I.sub.LED[i] to complete zero is not appropriate. If braking is performed, even if the original luminance is lowered, it is preferred that the light emitting system SYS turns on the brake lamp for safety.
[0126] Therefore, in the LED driver 1A according to the first or second example, when the high level detection result signal S.sub.DET_A is derived in the mode MD.sub.A2, the operation mode of the circuit 20A is changed from the mode MD.sub.A2 to the mode MD.sub.A1, so that supplying the drive current I.sub.LED[i] to the light emitting unit LL[i] can be continued. The same is true for the LED driver 1B according to the third or fourth example.
Sixth Example
[0127] A sixth example is described. In the LED driver 1A illustrated in
[0128] It may be possible that the shutdown process can be enabled or disabled on the basis of a signal supplied from the MPU 2 to the LED driver 1A or 1B. For instance, the data holding unit 50 stores a shutdown setting value, and the shutdown setting value is set to 0 or 1 based on the signal supplied from the MPU 2 to the LED driver 1A or 1B. In the LED driver 1A or 1B, when the value of the external resistor abnormality flag is set to 1, the control circuit 30 refers to the value of the shutdown setting value. Then, if the shutdown setting value is 0, the control circuit 30 controls the circuit 20A or 20B to perform the operation described above in the first or third example, while if the shutdown setting value is 1, it performs the shutdown process.
Seventh Example
[0129] A seventh example is described. In the LED driver 1A illustrated in
[0130] The MPU 2 can determine whether or not the LED driver 1 has an abnormality by monitoring the level of the wiring 3 that is equal to the level of the terminal FAILB. When recognizing that the level of the wiring 3 is low level, the MPU 2 can request the LED driver 1 (1A or 1B) to send data stored in the data holding unit 50 via the communication wiring 4. Here, the data requested to send includes the external resistor abnormality flag described above, a temperature abnormality flag indicating whether or not a temperature abnormality has occurred, an input voltage abnormality flag indicating whether or not an abnormality of the input voltage V.sub.IN has occurred, and the like. The MPU 2 can recognize which type of abnormality is detected in the LED driver 1, on the basis of the data received from the LED driver 1.
Eighth Example
[0131] An eighth example is described. In the above description, it is supposed that the operation mode of the drive reference voltage generation circuit 20 (20A or 20B) is set by the mode setting value, but the operation mode of the circuit 20 (20A or 20B) may be set based on the voltage at the external terminal for mode setting. In this case, the following structure can be adopted.
[0132] The external terminal for mode setting is included in the plurality of external terminals provided to the LED driver 1 (1A or 1B).
[0133] Further, the mode control circuit 30A illustrated in
[0134] Similarly, the mode control circuit 30B illustrated in
[0135] However, when the high level detection result signal S.sub.DET_A or S.sub.DET_B is derived and the value of the external resistor abnormality flag is set to 1 in the mode MD.sub.A2 or MD.sub.B2, the process as described above in one of the examples may be performed.
Ninth Example
[0136] A ninth example is described.
[0137] As described above, the number of channels, i.e. the value of n in the LED driver 1 may be 1. If n is 1, [i] indicating the channel number in the above description is [1].
[0138] The light emitting unit LL is constituted of one or more light emitting elements that emit light when current is supplied. The LED as a light emitting element may be any type of light emitting diode, or may be an organic LED that realizes an organic electro-luminescence (EL). In addition, the light emitting element may be one that is not classified into LED, such as a laser diode, for example.
[0139] The light emitting element drive device embodied as the LED driver and the light emitting system SYS in this embodiment can be used not only in the in-vehicle application but also in various applications such as a backlight for a liquid crystal display panel, a laser imaging detection and ranging (LIDAR) system using a laser diode, or a head up display.
[0140] For any signal or voltage, a relationship between high level and low level may be inverted in a form that does not spoil the spirit of the above description.
[0141] The channel types of the field effect transistors (FETs) in the embodiments described above are merely examples, and the circuit configuration including FETs can be modified, in such a manner that an N-channel type FET is replaced with a P-channel type FET, or that a P-channel type FET is replaced with an N-channel type FET.
[0142] As long as no inconvenience occurs, any transistor in the above description may be any type of transistor. For instance, any MOSFET as a transistor in the above description can be replaced with a junction-type FET, an insulated gate bipolar transistor (IGBT), or a bipolar transistor, as long as no inconvenience occurs. Any transistor has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is a drain, the other electrode is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other electrode is an emitter, and the control electrode is a gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is a collector, the other electrode is an emitter, and the control electrode is a base.
[0143] The embodiment of the present disclosure can be appropriately and variously modified within the scope of the technical concept recited in the claims. The embodiments described above are merely examples of the embodiment of the present disclosure, and meanings of terms of the present disclosure or the components thereof are not limited to those described in the above embodiments. Specific numeric values in the above description are merely examples, and as a matter of course, they can be changed to various values.