Wideband digitally controlled injection-locked oscillator

Abstract

A novel and useful digitally controlled injection-locked RF oscillator with an auxiliary loop. The oscillator is injection locked to a time delayed version of its own resonating voltage (or its second harmonic) and its frequency is modulated by manipulating the phase and amplitude of injected current. The oscillator achieves a narrow modulation tuning range and fine step size of an LC tank based digitally controlled oscillator (DCO). The DCO first gets tuned to its center frequency by means of a conventional switched capacitor array. Frequency modulation is then achieved via a novel method of digitally controlling the phase and amplitude of injected current into the LC tank generated from its own resonating voltage. A very linear deviation from the center frequency is achieved with a much lower gain resulting in a very fine resolution DCO step size and high linearity without needing to resort to oversampled noise shaped dithering.

Claims

1. A frequency tuning circuit, comprising: a frequency oscillator incorporating an LC tank circuit and an amplifier for maintaining oscillation, said oscillator operative to generate an oscillator signal; an oscillator buffer adapted to receive said oscillator signal and operative to generate a clock signal therefrom; an auxiliary feedback loop coupled to said oscillator buffer, said auxiliary feedback loop operative to generate an injection signal having a phase and amplitude; said auxiliary feedback loop incorporating a phase delay circuit operative to delay said clock signal in accordance with one or more control codes to generate two substantially orthogonal currents that are vector summed to yield said injection signal, wherein a frequency of said clock signal is determined by values of said one or more control codes; wherein said phase delay circuit is operative to delay said clock signal without any mixing by a mixer other than with a delayed version of said clock signal; wherein said auxiliary feedback loop is operative to inject said injection signal into said LC tank circuit to injection lock said frequency oscillator thereby providing frequency tuning thereof in a controlled manner; and wherein a resonating waveform is generated across said LC tank circuit in response to a vector sum of said oscillator signal and said injection signal.

2. The frequency tuning circuit according to claim 1, wherein a free running frequency of said oscillator signal is controlled by a tunable element in said LC tank circuit.

3. The frequency tuning circuit according to claim 1, wherein said auxiliary feedback loop comprises two paths substantially orthogonal to each other.

4. The frequency tuning circuit according to claim 1, wherein said auxiliary feedback loop further comprises a frequency multiplier.

5. The frequency tuning circuit according to claim 4, wherein said frequency oscillator is operative to downconvert said injection signal.

6. The frequency tuning circuit according to claim 1, wherein said auxiliary feedback loop comprises: a phase generator operative to generate a coarse delayed version of said oscillator signal; and a digital phase rotator (DPR) circuit operative to generate a fine delayed version of said oscillator signal by interpolating said coarse delayed version of said oscillator signal.

7. The frequency tuning circuit according to claim 1, wherein the vector sum of injection currents are interpolated by said LC tank such that the vector sum is injected at a phase with respect to an oscillator current.

8. A method of modulating an oscillator incorporating an LC tank circuit, comprising: first generating an oscillator signal across said LC tank, said LC tank coupled to a transconductance amplifier for sustaining oscillations of said oscillator; converting said oscillator signal to a clock signal utilizing an oscillator buffer; second generating from said clock signal an injection signal having a phase and amplitude; said second generating including delaying said clock signal in accordance with one or more control codes to generate said injection signal, wherein the frequency of said injection signal is determined by values of said one or more control codes, wherein said clock signal is delayed without any mixing by a mixer other than with a delayed version of said clock signal; injecting said injection signal into said LC tank circuit; and third generating an output oscillator signal across said LC tank circuit in accordance with a vector sum of said oscillator signal and said injection signal thereby injection locking said oscillator in a controlled manner.

9. The method according to claim 8, wherein a free running frequency of said output oscillator signal is controlled by a tunable element in said LC tank circuit.

10. The method according to claim 8, wherein second generating comprises generating two substantially orthogonal signals that are injected into said LC tank circuit and interpolated thereby.

11. The method according to claim 8, further comprising converting said oscillator signal to a clock signal for input to a phase generator.

12. The method according to claim 8, wherein said method further comprises mixing a second injection signal at twice the frequency of said oscillator signal with said injection signal before injection into said LC tank circuit.

13. The method according to claim 8, wherein said injection signal comprises one or more injection currents.

14. The method according to claim 8, wherein second generating comprises fourth generating a coarse delayed version of said clock signal.

15. The method according to claim 14, wherein second generating comprises fifth generating a fine delayed version of said clock signal by interpolating said coarse delayed version of said clock signal.

16. An oscillator circuit, comprising: a digitally controlled oscillator (DCO) incorporating an LC tank circuit and operative to generate a resonating waveform; a phase generator operative to generate a coarse delayed version of said resonating waveform; a digital phase rotator (DPR) circuit operative to generate a fine delayed version of said resonating waveform by interpolating said coarse delayed version of said resonating waveform; a feedback loop coupled to said digitally controlled oscillator and said digital phase rotator circuit, said feedback loop operative to inject said fine delayed version of said resonating waveform back into said LC tank circuit; and wherein frequency of said oscillator circuit is determined by a duration said resonating waveform is delayed by said phase generator and said digital phase rotator circuit.

17. The oscillator circuit according to claim 16, wherein frequency of said resonating waveform of said digitally controlled oscillator is controlled by a tunable element in said LC tank circuit.

18. The oscillator circuit according to claim 16, further comprising an oscillator buffer operative to convert the resonating waveform generated by said digitally controlled oscillator to a square wave clock for input to said phase generator.

19. The oscillator circuit according to claim 16, wherein said phase generator is operative to generate first and second output clocks having an approximately quadrature phase relationship.

20. The oscillator circuit according to claim 16, wherein said coarse delayed version of said resonating waveform is doubled in frequency compared to said fine delayed version of said resonating waveform.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:

(2) FIG. 1 is a diagram illustrating an example nonlinear oscillator tuning range;

(3) FIG. 2 is a high level schematic diagram illustrating a first example self injection locked oscillator of the present invention;

(4) FIG. 3 is a diagram illustrating an example oscillator tuning range including linear portions;

(5) FIG. 4A is a schematic diagram illustrating an example numerical model of an injection locked oscillator;

(6) FIG. 4B is a diagram illustrating the phasor representation of the signals in the model of FIG. 4A;

(7) FIG. 4C is a graph illustrating versus injection frequency for various settings of I.sub.r;

(8) FIG. 4D is a graph illustrating (t) and (t) versus injection frequency;

(9) FIG. 5A is a block diagram illustrating an example numerical model of an injection locked oscillator with an auxiliary loop;

(10) FIG. 5B is a graph illustrating simulation results of injected signal phase and resulting DCO frequency;

(11) FIG. 6A is a schematic diagram illustrating an example DCO core with second-harmonic filtering of the present invention;

(12) FIG. 6B is a schematic diagram illustrating an example DCO core without the second-harmonic filtering of the present invention;

(13) FIG. 6C is a schematic diagram illustrating an example VCO core of the present invention;

(14) FIG. 7A is a block diagram illustrating a first example auxiliary loop time and frequency domain representation of various signals thereof;

(15) FIG. 7B is a block diagram illustrating a second example auxiliary loop time and frequency domain representation of various signals thereof;

(16) FIG. 7C is a block diagram illustrating a third example auxiliary loop time and frequency domain representation of various signals thereof;

(17) FIG. 8A is a block diagram illustrating an example phase generator of the present invention;

(18) FIG. 8B is a diagram illustrating the phase relationships between various signals of the circuit of FIG. 8A;

(19) FIG. 9A is a block diagram illustrating an example digital phase rotator (DPR) circuit and signal flow for the current control word a;

(20) FIG. 9B is a schematic diagram illustrating the DPR core circuit and related unit cell structure;

(21) FIG. 10A is a block diagram illustrating an example K.sub.DCOT calibration engine for monitoring the PHE signal to optimize .sub.c1;

(22) FIG. 10B is a diagram illustrating calibration of the .sub.c1 delay line for proper timing between VI0/90 and V.sub.osc+;

(23) FIG. 10C is a diagram illustrating calibration of the .sub.c1 delay line when VI0/90 leads V.sub.osc+;

(24) FIG. 10D is a diagram illustrating calibration of the .sub.c1 delay line when VI0/90 lags V.sub.osc+;

(25) FIG. 10E is a diagram illustrating K.sub.DCOT as a function of .sub.c1;

(26) FIG. 10F is a flow diagram illustrating an example K.sub.DCOT calibration method for monitoring the PHE signal to optimize .sub.c1;

(27) FIG. 11 is a block diagram illustrating an example phase generator of the present invention;

(28) FIG. 12 is a graph illustrating injection locking range or linear FM range versus injection strength I.sub.r;

(29) FIG. 13A is a high level schematic diagram illustrating an example DCO core circuit of a second example self injection locked oscillator of the present invention;

(30) FIG. 13B is a high level schematic diagram illustrating a second example self injection locked oscillator of the present invention;

(31) FIG. 14 is a block diagram illustrating an example phase locked loop incorporating the oscillator of the present invention;

(32) FIG. 15 is a block diagram illustrating an example all digital phase locked loop incorporating the oscillator of the present invention;

(33) FIG. 16 is a block diagram illustrating an example polar transmitter incorporating the oscillator of the present invention;

(34) FIG. 17 is a block diagram illustrating an example wireline transceiver incorporating the oscillator of the present invention;

(35) FIG. 18 is a block diagram illustrating an example mobile device incorporating the oscillator of the present invention; and

(36) FIG. 19 is a block diagram illustrating an example IoT node incorporating the oscillator of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Digital to Frequency Converters

(37) In an example embodiment, a high-performance DFC system comprises a digitally controlled oscillator (DCO) where the frequency is modulated by digitally controlling the LC-tank capacitance C. This architecture splits the tracking tuning word, which controls the finest capacitor bank, into integer and fractional parts. The integer part comprises an array of unit-weighted MOS capacitors (unit cells) selected by thermometer row and column decoders. The integer tuning word drives these capacitors directly, after the binary-to-thermometer encoding, while the fractional tuning word is input to a multi-stage noise shaping (MASH) modulator, which drives one or several unit cells in the capacitor array. The FM tuning range is 5 MHz at 4 GHz while the finest frequency step size without and with is 40 kHz and 200 Hz, respectively, given the 8-bit fractional tuning word input to the and an OSR16.

(38) In the above switched capacitor implementations, the challenging aspect is keeping the DCO quantization noise low while achieving moderately wide linear FM range. One approach in addressing this challenge is to increase the number of smallest capacitor cells in the array. This complicates the array implementation because increasing the matrix size requires high-order decoders, which in turn would increase routing complexity and would also impact the Q of the LC-tank.

(39) Another approach is to increase the unit cell size while shifting the quantization noise away from the carrier into far-out frequencies using a modulator. In this scenario, the peak of the quantization noise (noise bump) at the DCO output is located at f.sub./2 which is half the clock frequency. This noise bump may end up in the receive band or, worst case, at the duplex receiver channel if implemented for a full duplex system, and therefore will limit the local receiver sensitivity. Because the noise bump increases with the unit cell or the smallest capacitor size, this issue will only get exacerbated.

(40) One solution to this challenge is to apply pulse width modulation (PWM) to the capacitor on/off control signal. In this topology, the effective capacitance seen by the LC tank can be reduced by controlling the duty cycle of the control signal. This architecture can achieve wider FM tuning range with fewer cells in the capacitor array, thus reducing the impact on Q of the LC tank while the extra resolution gained with the PWM scheme can eliminate the need for a dithering of the unit capacitor. The reported frequency resolution of 270 kHz, however, is not adequate for most wireless applications.

(41) A resolution finer than 1 kHz can be achieved without dithering through capacitive degeneration. Increasing the FM tuning range penalizes the DCO phase noise, however, which also suffers from the increase in the size of the capacitor array. In addition, the DCO transfer function is highly nonlinear over the usable FM range, such as shown in FIG. 1. The minimum frequency step size is 150 Hz while total the tuning range is 12 MHz.

(42) In another embodiment, reasonable DFC quantization and total FM range is achieved through segmented capacitor banks. In this embodiment, the capacitor bank for FM is split into three segments. The most significant bit (MSB) of the coarse segment consists of 128 thermometer coded capacitors each having a step size of 1.95 MHz/LSB. These capacitors are laid out in a 16 by 8 array and cover a frequency range of 250 MHz. The next segment has 16 thermometer coded elements that are 1/16.sup.th the size of the coarse unit cell and therefore have a step size of 120 kHz/LSB. The last segment has three additional capacitors driven by a 6-bit MASH to increase the resolution of the frequency modulator to 1.875 kHz. Although this embodiment provides a DCO capable of achieving wide FM range, it also exhibits high differential non-linearity (DNL) among capacitors and between coarse and fine segments of the capacitor banks. If not designed properly, the DCO frequency step can be non-monotonic (or overlap) over the segment boundary. All these impairments will impact the spectral purity of the FM signal.

(43) The differential non-linearity (DNL) issue between the coarse and fine capacitor banks is addressed in an embodiment that is a variant of a switched-capacitor array implementation which uses incrementally sized capacitors instead of binary or thermometer weighted capacitors. This topology uses one-hot coding in the fine capacitor bank to select only one capacitor at a time. The capacitor bank comprises 32 unit cells with capacitance of C.sub.0+i.Math.C and transistor size of W.sub.0+i.Math.W where i is the capacitor index. The limit on the smallest transistor size W.sub.0 is far stringent than the limit on the increment to a transistor size W and therefore the capacitor bank can be designed to achieve a very small step size. The coarse capacitor bank is also designed by incrementally changing capacitance in the LC-tank by a factor N.Math.C. Therefore, between the consecutive tuning codes, the capacitance increases monotonically and any discontinuity or overlap between the coarse and fine bank is avoided. The fine frequency step size is 5 kHz with a total tuning range of 10.24 MHz. Although the fine frequency step size is good, DNL is lacking between the fine and coarse banks over various frequency ranges.

(44) The embodiments described supra have been focused around DCOs with the switched capacitor array. In another embodiment, another class of digital frequency converter (DFC) uses an injection locking technique to generate FM modulation. In one embodiment, a quadrature VCO includes two oscillators cross coupled such that once the system is injection locked, the pair generates quadrature phases. In this implementation, the FM modulation is generated by modulating the coupling strength between the two oscillator cores through an analog voltage. This continuous time and amplitude architecture can achieve linear modulation range of 60 MHz. Any mismatches in the two oscillators, however, also limit performance by introducing quadrature phase error. In another embodiment, a DFC employs injection locking for frequency generation at millimeter wave frequencies. This solution, however, is not practical for digitally intensive transmitters operating at much lower RF frequencies.

Self Injection Locked Digitally Controlled Oscillator

(45) In another embodiment, injection locking of an oscillator is exploited using an auxiliary loop to perform the frequency modulation. A high level schematic diagram illustrating an example inverter ring oscillator of the present invention is shown in FIG. 2. The circuit, generally referenced 10, comprises a digitally controlled oscillator (DCO) 12, oscillator buffer 26 (e.g., signal squarer), phase generator 28 and digital phase rotator (DPR) 14. The DCO 12 also comprises the equivalent of a well-known transconductance amplifier g.sub.m stage, including squarer block 16 labeled with a square wave symbol (e.g., transistors M1 and M2 in FIG. 6A) and buffer component labeled I.sub.osc (i.e. amplifier) 18 (e.g., transistor M3 in FIG. 6A). The squarer block functions to square up the sinusoidal signal input thereto. The amplifier is needed to maintain oscillation in the DCO.

(46) The LC-tank of the digitally controlled oscillator (DCO), consisting of inductor 20, tunable capacitor 22 and equivalent parallel resistor 24, whose free-running frequency .sub.o is set by the switched capacitor C 22, is injected with a delayed version of its own resonating waveform. The resulting frequency .sub.out under such conditions is given by Adler's equation below:

(47) $\begin{array}{cc}{}_{\mathrm{out}}\left[n.Math.t_{\mathrm{sH}}\right]=-\frac{{}_0}{2.Math.Q}\frac{I_{\mathrm{inj}}}{I_{\mathrm{osc}}}.Math.\sin \left(\left[n.Math.t_{\mathrm{sH}}\right]\right)+{}_0& \left(1\right)\end{array}$
where, Q is the LC-tank quality factor, I.sub.osc is the peak oscillator current, I.sub.inj is the peak injected current into the LC-tank, and t.sub.sH is the sampling time of the DFC (determined by f.sub.sH). is the steady-state phase between I.sub.osc and I.sub.inj which implies that the system is injection locked. By manipulating the delay of the injected signal (and consequently ) the steady-state oscillator frequency .sub.out varies according to Equation 1. The current I.sub.TANK into the tank is the vector sum of the oscillator current I.sub.osc and the injection current I.sub.inj. Within a reasonable range of around 0, .sub.out increases linearly with . The maximum variation of .sub.out about .sub.o for which the DCO is injection locked is limited by the injection locking range .sub.L given by the following equation:

(48) $\begin{array}{cc}{}_L=\frac{{}_0}{2.Math.Q}\frac{I_{\mathrm{inj}}}{I_{\mathrm{osc}}}& \left(2\right)\end{array}$

(49) The phase adjustment of the injected signal is performed in two steps. The first step is coarse and performed by the phase generator block represented by .sub.c in the block diagram in FIG. 2. This circuitry also generates approximate quadrature signals that are used by the digital phase rotator (DPR) circuit, represented by .sub.f, to perform a fine phase adjustment. The DPR generates two orthogonal currents I.sub.inj1 and I.sub.inj2 that are injected directly into the oscillator core while the interpolation is performed by the LC-tank such that I.sub.inj, the Euclidean vector sum of I.sub.inj1 and I.sub.inj2 is injected at a phase with respect to the DCO current I.sub.osc. The phase delay due to .sub.f varies from 0 to 90 about a mean phase which is determined by the blocks in the auxiliary feedback path including .sub.c and is typically set to 0 (i.e. equivalent to 360 or multiples thereof). The signals that steer the injected currents are derived from the DCO, so the system is fully synchronous to .sub.out. The interpolated phase is a function of the ratio of currents I.sub.inj1 and I.sub.inj2, which is controlled by the digital codes a and b. The magnitude of the injected current I.sub.inj is controlled by the unit cell current I.sub.u and the digital codes a and b. The linear frequency modulation range 38, 39 shown in FIG. 3 is determined by the injection locking range, which is proportional to I.sub.r=I.sub.inj/I.sub.osc. Both I.sub.osc and I.sub.inj are digitally controlled and therefore the DCO gain (Hz/LSB) and the linear FM tuning range can be scaled according to the desired application.

FM Modulation Using Injection Locking

(50) A numerical model of a conventional injection locked oscillator will now be described. The various modes of an oscillator tank under the influence of an external signal can be analyzed by numerically modeling the circuit shown in FIG. 4A. This model is used to analyze trends before describing the oscillator in more detail. Of particular interest is the behavior of the oscillator phasor signals, shown in FIG. 4B, when the injected signal is within the injection-locking range. The model was developed in Simulink, a graphical programming environment for modeling available from The MathWorks Inc., Natick, Mass., USA. The following parameters were used: I.sub.osc=1 mA, f.sub.o=4.5 GHz, Q=10.6, L=0.85 nH, C=1.5 pF.

(51) In that regime, the oscillator injection locks to the incident signal causing (t) and (t) to become constant after a short settling time. In FIG. 4D, the phases (t) and (t) are plotted as the injection frequency f.sub.inj is varied over and beyond the injection-locking range. The injection strength I.sub.r is set to 0.8. The regions when the oscillator is injection-locked or injection-pulled are annotated on the plot. Notice that when the oscillator is injection locked, the phases (t) and (t) vary linearly as a function of f.sub.inj. Both (t) and (t) cross the origin around .sub.0/2=4.5 GHz which is the resonance frequency of the LC tank. The oscillator is injection locked over a range of 400 MHz around 4.5 GHz.

(52) As shown in FIG. 4C, varies linearly with f.sub.inj. The range of f.sub.inj in FIG. 4C is the injection locking range, which is proportional to I.sub.r. The slope of with respect of f.sub.inj decreases with increasing I.sub.r. The injection lock range varies from 200 MHz, 400 MHz, and 600 MHz for I.sub.r values of 0.5, 0.8, and 1.0, respectively. Note that this plot is useful in understanding the operation of the invention. In FIG. 4C, f.sub.inj is the independent variable that determines , while in the oscillator of the present invention, is the independent variable or forcing condition that determines the steady-state frequency of the oscillator. The values for I.sub.r and Q are chosen arbitrarily to show the extent of FM bandwidth theoretically possible with an injection locked oscillator. The trends observed from this model are the same for the targeted value of I.sub.r of 0.15 which results in a narrower linear FM range.

Numerical Model of a Self Injection Locked Oscillator

(53) A numerical model of the self injection locked oscillator of the present invention will now be described. After briefly describing injection locking theory, the self injection locked oscillator of the present invention is described in more detail.

(54) FIG. 5A is a Simulink model of an injection locked oscillator, generally referenced 530, comprising an LC tank 532, g.sub.m differential pair 534 and auxiliary loop 536. Four currents are summed at the input of block R.sub.tank 540. These currents are from the capacitor 546, inductor 550, commutating transistor pair 548 and injecting circuit 544. This model exploits the injection locking phenomenon as a way to generate FM. Instead of using an independent signal source, the injected signal is directed from the oscillator output and phase delayed by a certain time interval. This essentially creates an auxiliary feedback path in the oscillator, the delay of which is varied in order to change the oscillating frequency. I.sub.r in FIG. 5A scales the peak injection current I.sub.inj with respect to I.sub.osc and can also be used to vary the linear FM range or the injection locking range.

(55) Simulation results from the numerical model will now be described. Given that the oscillator is injection locked, the final oscillating frequency is given by Equation 1. The argument [k] in this equation is modulated in the model shown in FIG. 5A. A transient simulation with 500 k samples was run in small increments over a range of [k] that exceeds 100. In this simulation, I.sub.osc is 1 mA, Q.sub.tank is 10.6, L.sub.tank is 0.9 nH, and C.sub.tank is 1.4 pF.

(56) FIG. 5B shows the simulation results with I.sub.r=0.5. Several observations are noted and discussed below. First, the oscillating peak voltage V.sub.osc,pk (normalized peak voltage) decreases as the oscillator is steered away from the free resonant frequency .sub.0. This loss of amplitude results in a degradation of the DCO phase noise. The variation in V.sub.osc,pk increases with the injection strength. The auxiliary feedback path that is phase delayed by in FIG. 5A acts as positive feedback and hence augments or amplifies the oscillation signal only when is 0. At other values of , the feedback impedes the main oscillation. When approaches 180, this feedback becomes negative and, if strong enough, can stop the oscillation altogether. This is especially true for cases when I.sub.r is close to 1. This limitation, however, is not a cause for concern here for two main reasons. First, the I.sub.r targeted here is around 0.15. Also, the target range for is 45, which, according to FIG. 5B, is where the oscillator tuning range is linear and the variation in V.sub.osc,pk is small. The output of the DCO is sourced from the proceeding buffer stage which acts like a hard limiter and therefore any parasitic amplitude modulation (AM) due to the peak voltage trace (dashed line 582) in FIG. 5B will be removed.

Oscillator Core Embodiments

(57) Several oscillator cores may be used with the present invention. Three examples of possible oscillator cores are provided and described below. They include a DCO with filtering of the second harmonic, DCO without such filtering and a voltage controlled oscillator (VCO).

(58) A high-level circuit diagram of an example embodiment of the digitally controlled oscillator (DCO) with filtering, generally referenced 130, is shown in FIG. 6A. The DCO core supply is 1.1V. The differential tank inductance 132 is 2 nH while the differential tank capacitance 134 is digitally controlled between 1.6 pF and 4.6 pF. The M3 NMOS transistor operates in a triode region with channel resistance digitally controllable between 5 to 105. The fact that M3 operates in triode necessitates the placement of L2. Capacitor C1 is maximized in order to filter any noise from the current sink that can upconvert due to the switching action of M1 and M2 and degrade oscillator phase noise. The LC tank comprises the inductor 132 and binary weighted MOM capacitors 134 controlled via a digital input (e.g., 8-bit).

(59) A schematic diagram illustrating an example DCO core without filtering of the present invention is shown in FIG. 6B. In this circuit, the DCO 640 operates without the filtering circuit of FIG. 6A, also known as 2.sup.nd harmonic trap and M3 operates in saturation. The core supply of the DCO is 1.1V. The differential tank inductance 644 is 2 nH while the differential tank capacitance 642 is digitally controlled between 1.6 pF and 4.6 pF. The M3 NMOS transistor operates in a triode region with channel resistance digitally controllable between 5 to 105. The LC tank comprises the inductor 644 and binary weighted MOM capacitors 642 controlled via a digital input (e.g., 8-bit). Note that the filtering circuit including L2 of FIG. 6A is not present in the circuit 540 of FIG. 6B.

(60) A high-level circuit diagram of an example embodiment of a voltage controlled oscillator (VCO), generally referenced 650, is shown in FIG. 6C. This circuit operates as a voltage controlled oscillator (VCO) rather than a DCO. The tail current source 568 provides the operating bias for the cross coupled transistors M1 and M2 while the analog tuning voltage V.sub.tune 652 controls the LC tank resonance frequency. The VCO core supply is 1.1V. The differential tank inductance 656 is 2 nH while the differential tank capacitance 654 is voltage controlled via the V.sub.tune signal.

Phase Generator

(61) A block diagram illustrating a first example phase injection mechanism and related waveforms of the I.sub.inj1 and I.sub.inj2 injection currents is shown in FIG. 7A. The auxiliary loop, generally referenced 560, comprises the phase generator 564 and the digital phase rotator (DPR) 566. Proper design of the auxiliary loop is essential for the frequency tuning of the DCO. The principle function of this auxiliary path is to generate a phase delayed version of the oscillator output such that I.sub.inj forms an angle with I.sub.osc as shown in FIGS. 5A and 5B. The angle is generated by the delay stages in the phase generator block and the DPR and is described by the following equations:

(62) $\begin{array}{cc}\left(n.Math.t_{\mathrm{sH}}\right)={}_c\left({}_c\right)+{}_f\left(n.Math.t_{\mathrm{sH}}\right)& \left(3\right)\\ \left(n.Math.t_{\mathrm{sH}}\right)={}_c\left({}_c\right)+{\tan }^{-1}\left(\frac{b\left(n.Math.t_{\mathrm{sH}}\right)}{a\left(n.Math.t_{\mathrm{sH}}\right)}\right)& \left(4\right)\end{array}$
where coarse phase .sub.c is generated by the delay stage .sub.c in the phase generator block and the fine phase .sub.f is adjusted by the DPR through control words a and b as described in more detail infra. As shown in FIG. 7A, the oscillator voltage V.sub.osc is converted to a square wave clock by the oscillator buffer 562. The clock is controllably delayed by the coarse delay circuit .sub.c, which produces two output clocks VI0 and VI90 with approximately quadrature phase relationship.

(63) These two clocks are then fed to the DPR 566, which creates synchronous current pulses I.sub.inj1 and I.sub.inj2 with gains controlled by the digital steering signals a and b. The two currents are summed (via summer 568) and injected as I.sub.inj with phase , back into the oscillator tank. The pedestal in I.sub.inj=I.sub.inj1+I.sub.inj2 is due to the phase shift between the VI0 and VI90 signals. The level of the pedestal is determined by the number of current cells turned on in the DPR array via a and b. The current injected into the DCO is band-pass filtered by the LC tank. Therefore, higher harmonics injected into the DCO do not severely impact the circuit's operation. The LC tank also serves as the interpolator that averages between the VI0 and VI90 phases based on the weights determined by controls a and b.

(64) Assume that the LC tank of the oscillator is tuned to a frequency of 4.2 GHz. According to FIG. 7A, the auxiliary path delay comprises the oscillator buffer, phase generator, DPR and interconnects. The delay due to interconnecting wires can be ignored since the entire circuitry is located within a small area. At a frequency of 4.2 GHz, the simulated oscillator buffer delay is 17.3 ps (26.2). The delay of the phase generator is 72 ps (108.8). A 180 phase arises due to inversion inside the DPR current steering cell. At a mid code setting of the DPR DAC, the current controls a and b are equal and therefore .sub.f from Equation 4 is 45. This brings the total phase delay in the auxiliary path to 360. Consequently, is zero and I.sub.inj is in phase with I.sub.osc and according to Equation 1 the oscillator frequency (.sub.out) is .sub.o. In order to vary .sub.out around .sub.o, .sub.f is tuned between 0 to 90 by adjusting control words a and b in the DPR while the maximum possible variation of .sub.out is defined by .sub.L in Equation 2. Under such a condition, .sub.c is considered to be properly set and it also ensures that the low-to-high transitions on VI0 and VI90 occur around the 0 phase of oscillator output voltage V.sub.osc+ as shown in FIG. 8B. The upper and lower limit of the interpolated phase (.sub.f) is determined by the VI0 and VI90 signals and with the proper setting of .sub.c, the injected phase lands in the linear to .sub.out conversion region shown in FIG. 5B. Also note that the discussion so far has been in the context of narrowband FM (NBFM) modulation because is a linear function of .sub.f only under such condition.

(65) A block diagram illustrating a second example phase injection mechanism and related waveforms of the injection currents is shown in FIG. 7B. This architecture, generally referenced 590, utilizes a divider circuit 592 in the feedback loop. The output of the divider is at half the frequency of the DCO 591 and is input to the pulse generator block 594 which essentially adjusts the duty cycle of the input signal. The reduction in duty cycle depends on the division ratio. For a division ratio of two, the duty cycle must be set around 25% to maximize the 2.sup.nd harmonic component which is equal to the oscillation frequency. For a division ratio of four, the duty cycle must be set around 12.5% to maximize the 4.sup.th harmonic component which is equal to the oscillation frequency. Also note that the 90 and 270 phases from the divider are not useful at all. This is because a 90 phase shift at the divider output will translate into 180 phase shift for the 2.sup.nd harmonic component which is at f.sub.o. Therefore the VI90 and VI270 signals must be derived from the D0 and D180 outputs of the divider 592 using the same technique as shown in FIG. 7A. The DPR current waveforms will have components at the fundamental and harmonics. In the case shown in FIG. 7B, the 2.sup.nd harmonic component will be the dominant signal after the LC tank filtering.

(66) A block diagram illustrating a third example phase injection mechanism and related waveforms of the injection currents is shown in FIG. 7C. This architecture, generally referenced 600, utilizes a frequency doubler 604 in the feedback loop followed by a frequency divider 606. In this manner, the VI0 and VI90 signals are at frequency f.sub.o of the DCO 612. The signals D0 and D180 output of the frequency doubler are at twice the oscillator frequency due to the XOR operation between the phase delayed versions of the DCO signal. The duty cycle of D0 and D180 may not be 50%. The divider, however, compensates for this issue. The quadrature phases at the DCO frequency are generated without using any DCD blocks. This is a key advantage of this architecture over the one shown in FIG. 7A.

(67) Details of the coarse delay line, generally referenced 570, are shown in FIG. 8A. The delay line comprises oscillator buffer 572 and two cascaded digitally controlled coarse delay lines .sub.c1 574 and .sub.c2 576. The phase delay in the auxiliary feedback loop has to be 360 across the DCO LC tank tuning range. If the LC tank is tuned for lower frequencies, additional delay stages within .sub.c1 are engaged and vice versa. .sub.c2 is designed to generate the 90 phase shift between VI0 and VI90 signals. The phase delay will vary over the oscillator's frequency range, process, supply and temperature. Therefore .sub.c1 is preferably calibrated. A well regulated circuit supply will ensure limited voltage variation over time. Simulations show a 2 ps delay variation in each stage over temperature (40 C. to 85 C.) which implies according to Equation 2 that will have an offset when the DPR DACs are at mid code. Consequently, the linear FM range may be reduced. The behavior of inverter delay with respect to temperature, however, is linear and well characterized. Therefore such offsets can be removed by monitoring the IC temperature and adjusting the number of delay stages .sub.c1 based on an empirical model. Table 1 below presents the simulated phase difference between VI0/VI90 and V.sub.osc+ signals.

(68) TABLE-US-00001 TABLE 1 Simulated Phase Difference Between VI0/VI90 and V.sub.OSC+ Signals .sub.c1 .sub.1 .sub.2 .sub.1 + .sub.2 Delays [deg] [deg] [deg] 1 194.6 100.5 94.1 2 129.7 35.5 94.1 3 65.8 28.4 94.2 4 2.0 92.1 94.2

(69) Note that for proper operation of the DPR, the phase difference between VI0 and VI90 should be approximately 90. The aforementioned conditions are satisfied according to the simulation results in Table 1 when three delay stages at 4 GHz are engaged in the .sub.c1 block.

Digital Phase Rotator

(70) A simplified high-level block diagram of the DPR block is shown in FIG. 9A. The digital phase rotator (DPR) functions to interpolate between the signals generated by the phase generator block discussed supra. The DPR circuit is essentially two interleaved current steering DACs with mutually exclusive selection of current sources. Interleaving the current cells minimizes the mismatch between the two DACs but, however, makes the routing more complex. In one example embodiment, the DPR array comprises 64 unit cells controlled by coarse control words a.sub.c and b.sub.c and seven unit cells controlled by fractional control words a.sub.f and b.sub.f through a MASH stage. Each unit cell contains two current steering cells, one for each interpolating vector VI0 and VI90 and their respective differential phases. The output currents are summed at nodes V.sub.osc+ and V.sub.osc and injected into the LC tank of the DCO.

(71) The current control word a is split into 6-bit integer word a.sub.c and 6-bit fractional word a.sub.f. The control word a.sub.c is further split in the DPR array into three bits for row selection and three bits for column selection. These portions are thermometer encoded and passed through a level shifter before being passed into the unit cell U of the DPR array. The fractional word a.sub.f is applied to a MASH converter. The 7-bit output of the converter is level shifted and then applied to the DPR unit cells. Current control word b is configured in the same manner. For the NBFM case, if the DCO frequency resolution is high enough to meet the spectral mask requirements, the converter may not be needed. Therefore, any impairments originating from processing such as mismatch between coarse and fine unit cells etc. may not be relevant.

(72) The digital portion of DPR block samples the current control settings a and b from the SPI registers. The SPI registers are latched by an external clock, which is asynchronous to any clocks derived from the DCO. Therefore, in the first stage, the a and b integer and fractional words are sampled by f.sub.sL which is derived from the DCO clock. The integer control bits are then split and thermometer encoded. In the next stage, the integer and fractional words are up-sampled by f.sub.sH. This clock also drives the MASH sigma-delta converters and the DPR array.

DPR Unit Cell

(73) The DPR unit current cell, illustrated in FIG. 9B, comprises a cascode current source (M3, M4), differential pair (M5, M6), enable switch (M7, M8), selection logic 120, 124 and bypass capacitors 118, 122. A current reference circuit 116 supplies bias to the cascode current mirror in each cell. The typical current in each unit cell is 30 A. The cascode current source topology increases the output impedance looking into node X. This is important because the remaining transistors in that cell, M5, M6, M7 and M8, operate in a triode region when turned on and offer very little resistance to ground. The differential output node of each current cell is connected to the DCO. This will result in some loading of the DCO output.

Calibration

(74) As discussed supra, the quadrature phases for the DPR block generated by the phase generator are preferably aligned with the oscillator voltage waveform V.sub.osc, as shown in FIG. 10B. A misalignment of DPR signal phase with DCO signal phase will result in an injected signal whose phase is not in the linear frequency tuning range as shown in FIG. 3. The proper alignment of DPR signal phases with the DCO can be achieved by setting the .sub.c1 coarse delay line.

(75) The mechanism of calibrating the .sub.c1 delay line is illustrated in FIG. 10A. The method applies a small time varying FM signal y[k] 42, 46 which is then translated into the DPR current control word (tuning word 54) through a normalization factor represented by the term f.sub.R/K.sub.DCOT (block 52). The extent of current control word variation is such that the injected signal phase into the LC tank varies between 5 around a mean phase set by .sub.c1 delay line code. K.sub.DCOT can be determined using an algorithm illustrated in FIG. 10F and described in more detail infra, while the DCO is frequency locked by the all digital PLL (ADPLL).

(76) Using a well-known LMS based DCO gain estimation algorithm, due to the closed-loop operation of the ADPLL, any mismatches between the digitally estimated DCO gain K.sub.DCOT and the actual DCO gain will result in perturbation on the filtered digital phase error (PHE) signal. In the oscillator of the present invention, K.sub.DCOT is adjusted until the variance of the PHE signal is minimized and the final value is then stored in a local memory. FIGS. 10B, 10C and 10D show the relationship of the oscillator signal with respect to VI0 and VI90 signals at the DPR input for three different settings of .sub.c1. The resulting K.sub.DCOT for each value of .sub.c1 is plotted in FIG. 10E. FIGS. 10C and 10D illustrate a scenario where .sub.c1 is not set to the optimal value, which results in the average phase between VI0 and VI90 signals to be far away from the zero crossing of the V.sub.osc+ signal. Consequently, the K.sub.DCOT is low. FIG. 10B illustrates the scenario where .sub.c1 is properly calibrated and K.sub.DCOT is maximum. Therefore, the optimum setting of .sub.c1 is determined by performing the calibration algorithm over all settings of .sub.c1 and then storing the setting of the maximum K.sub.DCOT to be used during payload transmission.

Calibration Algorithm

(77) A flow diagram illustrating an example method of calibrating the .sub.c1 delay line is illustrated in FIG. 10F. First, the PLL is locked to channel FTX (step 620). The .sub.c1 delay line is then set (step 622). is then modulated with a square wave with an extent of 5 (step 624). The estimated DCO gain K.sub.DCOT is adjusted while the variance of the PHE signal is monitored (step 626). The modulation of is stopped and the value of K.sub.DCOT is frozen (step 628). If it is not the last .sub.c1 setting (step 630), then the method loops back to step 622. Otherwise, .sub.c1 is stored with the maximum K.sub.DCOT result and is then used for payload transmission (step 632).

Performance Results

(78) An example narrowband DCO of the present invention was implemented and fabricated by the inventors in 40-nm CMOS. In narrowband configuration, the dithering was turned off. The .sub.c1 delay line was manually calibrated according to the procedure described supra since the digital system required for automatic calibration was not implemented in the example fabricated silicon. The .sub.c2 setting was determined through simulations and was verified to be optimum through lab measurements. Like .sub.c1, an optimum .sub.c2 results in the highest DCO gain. The DCO step size is measured in units of Hz per degree change in since the transfer function is more conveniently expressed in this manner instead of the digital inputs a and b. Note that for a 6-bit word length of a and b, the approximate step size is 1, since tan.sup.1(1/63)<1.

(79) In the NB modulation configuration, the DPR unit cell current is 31 A which brings the total injected current to 1.97 mA. The ratio between injection current and oscillator current I.sub.r is 0.15. A more efficient way for generating FM in this configuration is to shut off one of the interleaved DACs in the DPR and one of the quadrature phases from the phase generator. In this configuration, the frequency of the DCO is varied by modulating the amplitude of the injected signal I.sub.inj instead of the phase . This results in a substantial current savings from the DPR and the phase generator. Since the DPR unit cell current is limited by design, in order to reduce the injection strength I.sub.r, I.sub.osc is increased to 12.8 mA. I.sub.inj can be varied through either control words a or b. The results with NB modulation and mean step size of 9 kHz is a total tuning range over all the DPR settings of 550 kHz. The tuning range measurement when I.sub.r is 0.32 is 80 MHz while the step size is 300 kHz. In this case both of the interleaved DACs are enabled in order to sweep the injected phase from 45 to 45 by setting appropriate values of the control words a and b.

(80) The DCO phase noise at 1 MHz is 118 dBc/Hz. The far out noise is limited by the output buffer and therefore a phase noise of better than 132 dBc/Hz cannot be measured at those frequencies. The measured 1/f.sup.3 corner (i.e. the point along the x-axis where the slope of phase noise changes from 30 dB/dec to 20 dB/dec) is around 600 kHz.

Wideband Configuration of the Oscillator

(81) The oscillator of the present invention was tested in wideband (WB) mode in addition to the NB mode. The results from the numerical model discussed supra show that injection locking range beyond 100 MHz is possible if the injection current is strong enough in spite of the high Q of the resonant tank required in order to meet the out-of-band noise requirements. The peak voltage V.sub.osc,pk curve in FIG. 5B represents a hurdle for such a task as it indicates an appreciable loss in oscillator amplitude as the oscillator is steered away from the resonant frequency of the LC tank which will consequently degrade the phase noise of the DCO. The extent, however, that degradation is somewhat dependent on the spectral density of the FM signal itself which for the WCDMA standard, for example, is somewhat Gaussian. This implies that a significant population of discrete frequencies of the modulated signal is concentrated around the carrier frequency. Therefore, the injection locked DCO, for the most part, operates close to the resonance frequency of the LC tank. Consequently, the system scarcely operates in the region of low V.sub.osc,pk. Operating in such a way reduces any risks and prevents additional distortions that would otherwise limit the performance of the DCO.

(82) In the wideband configuration, the DPR unit cell current is 61 A, which brings the total injected current to 3.9 mA. The oscillator current is 5.1 mA, therefore I.sub.r is 0.75. The results are captured in FIG. 15. The mean step size is 2.88 MHz while the minimum and maximum DCO frequency is 4.522 GHz and 4.729 GHz which brings the total linear range just over 200 MHz over the injected phase range of 70.

(83) In addition, processing is required in this configuration if the frequency resolution is not adequate. A 6-bit input of the is swept from 0 to 63 while the integer phase boundary is between 1 and 2. The integer step size is measured to be 1.71 MHz while the step size with is 24.8 kHz which is 2.sup.6 times the integer step size. The reduction of step size with also improves the in-band quantization noise by 37 dB.

(84) An explanation will be presented of how the injection strength I.sub.r can be scaled to attain a certain linear FM range that is proportional to the injection locking range. This is achieved by measuring the linear FM range over as a function of I.sub.r, as shown in FIG. 12. The measured step size labeled on the right y-axis represents the average step size measured by varying in 1 increments. The FM modulation in this measurement is strictly due to the modulation of injected phase . Using the NB modulation of the present invention utilizing the amplitude of injected signal, the linear FM range can be reduced to less than 1 MHz.

(85) The measured performance of the DFC of the present invention will now be described. The measured tuning range of the DFC ranges from 550 kHz to 200 MHz at the DCO output. The step size in the WB and NB configurations is 2.88 MHz and 9 kHz respectively without processing, and 45 kHz and 140 Hz with processing. Note that the frequency resolution in the WB configuration could be improved by increasing the DPR array size. For example increasing the DPR array size to 256 elements brings the step size down to 11 kHz.

Common Source Node Injection Embodiment

(86) The oscillator embodiment shown in FIG. 1 and described supra couples the injection signal directly into the LC tank (i.e. across the V.sub.osc+ and V.sub.osc terminals in FIG. 6, which yields the highest injection locking range and linear FM range. The downside of this topology, however, is the loading of the DCO LC tank as more current cells in the DPR are engaged, especially in the wideband configuration mode.

(87) An alternative topology is shown in FIGS. 13A and 13B where the signal is injected at the common source node X of the cross-coupled NMOS transistors M1 and M2. The principal advantage in this embodiment is that the LC tank (i.e. inductor 512 and tunable capacitor 514) is free from loading by the DPR circuit. The current I.sub.TANK into the tank is the vector sum of the oscillator current I.sub.osc and the injection current I.sub.INJe.sup.j(2.sup.INJ.sup.-.sup.osc.sup.)t. The transfer function from the common source node to the LC tank, however, is bandpass around 2.sub.o and therefore the DPR circuit has to operate at twice the original frequency. Therefore, a frequency doubler 488 is inserted at the DCO output to generate clocks for the DPR. Note that this topology does not require differential operation since the injected signal is single ended. The cross coupled NMOS pair acts as a mixer (494) to downconvert the injected signal into the injection locking range of the DCO.

Example Applications of the Current Switching Oscillator

(88) Several applications of the current switching oscillator of the present invention as a frequency generator will now be described.

(89) A block diagram illustrating an example phase locked loop (PLL) incorporating the oscillator of the present invention is shown in FIG. 14. The PLL purpose is to set the oscillator at the desired channel and its operation could be entirely independent from the FM modulation using injection locking. The PLL, generally referenced 160, comprises a reference oscillator 162, N divider 164, phase/frequency detector 166, charge pump 168, low pass filter 170, voltage controlled oscillator (VCO) 172 incorporating the oscillator of the present invention, programmable M divider 174 and modulator 176.

(90) A block diagram illustrating an example all digital phase locked loop (ADPLL) incorporating the oscillator of the present invention is shown in FIG. 15. The ADPLL purpose is to set the oscillator at the desired channel and its operation could be entirely independent from or shared with the FM modulation using injection locking. The frequency command word (FCW) 182 is split into its integer FCW.sub.I and fractional FCW.sub.F parts, with separate reference accumulators 184, 202 that generate the integer and fractional part of the reference phase, PHR.sub.I and PHR.sub.F, respectively. In order to properly accumulate the FCW as a whole, a carry is transferred to the integer accumulator whenever an overflow of the fractional part occurs. A synchronous 8-bit counter serves as the variable accumulator 189 and produces the variable phase PHV that is subtracted from PHR.sub.I via subtractor 186 to provide the integer part of the phase error PHE.sub.I. PHR.sub.F is used to calculate the look-ahead TDC delay code based on the estimated delay characteristic of the look-ahead TDC (i.e., a combination of a digital-to-time converter followed by a TDC), which in turn is applied to the look-ahead TDC 198 through a gain. A look-ahead TDC gain estimation block 200, based on an iterative adaptation algorithm, is implemented on chip to dynamically track delay estimation errors due to PVT variations. The digitized output of the TDC represents the fractional part of the phase error, PHE.sub.F that is combined with PHE.sub.I via summer 188 to yield the total fixed-point representation of the phase error PHE.

(91) The phase error PHE is then filtered via loop filter 190, in order to properly set the dynamics of the loop. A reconfigurable proportional integral controller within the loop filter block 190 is followed by a DCO decoder also within the loop filter block 190 to generate the oscillator tuning word (OTW). The DCO 192 comprises the oscillator described supra. In one embodiment, the DCO includes switched capacitor banks that are dithered using a 2.sup.nd-order MASH modulator in order to achieve a finer equivalent frequency resolution and push the quantization noise at higher offset frequencies where they are more easily filtered out and do not contribute significantly to the total jitter. The operation frequency of the modulators can be dynamically selected between different divider versions of the oscillator output in order to meet the required performance as a trade-off between power consumption and jitter.

(92) In one embodiment, the feedback path was chosen to operate at a maximum 2.5 GHz, which means that a divide-by-two version of the DCO output is fed back to the variable accumulator and the look-ahead TDC. Division by two is achieved using a current mode logic (CML) 4 divider cascaded with a CMOS digital divider. These dividers are represented in FIG. 15 by the N block 194. Since the loop feedback operates on a divided version of the output, the effective frequency command word is adjusted accordingly. Therefore, one half of the multiplication ratio is accumulated at the ADPLL.

(93) As mentioned supra, the retimer clock gating circuit 196 generates the clock signals for the ADPLL. The CKR clock is used as a global digital clock of the ADPLL loop (at the reference clock rate) to resample the output of the variable accumulator and to generate a gated version of the variable feedback clock CKV.sub.gtd.

(94) One application of the oscillator based ADPLL of FIG. 15 is in a wideband digital polar transmitter as shown in FIG. 16. In this transmitter, generally referenced 580, the switched capacitor bank in the DCO 582 is tuned to the desired channel while the self injection locked oscillator 586 of the invention is used to perform the wideband FM modulation. The digital frequency tuning word 588 is normalized according to the calibrated DCO gain and then converted into current control inputs a 590 and b 592 to the DPR circuit 584. The integer portion of the current control is applied to the DPR array while the fractional portion is applied to the array after going through a modulator 596, 598.

(95) A block diagram illustrating an example wireline transceiver incorporating the oscillator of the present invention is shown in FIG. 17. The transceiver, generally referenced 210, comprises a DSP/processor (including a baseband processor in one embodiment) 212, transmitter 214, receiver 224, PLL based frequency generator 222 and the channel (e.g., wireline) 234. Note that a person skilled in the art can modify the transceiver 210 to operate as a wireless transceiver. The transmitter 214 comprises a serializer 216, TX equalizer 218 and driver 220. The receiver 224 comprises a low noise amplifier (LNA) 226, RX equalizer 230, clock data recovery (CDR) 228 and deserializer 232.

(96) In this example embodiment, the frequency generator 222 comprises the self injection locked oscillator as described supra. In another embodiment, the frequency generator may comprise the ADPLL circuit described supra in connection with FIG. 15. The oscillator offers wideband frequency modulation with very fine resolution. It efficiently provides high resolution and high linearity while offering a wide tuning range which is highly desirable in wireline systems.

Mobile Device Incorporating the Injection Locked Oscillator Based DCO

(97) A block diagram illustrating an example tablet/mobile device incorporating a frequency generator that includes the self injection locked oscillator based DCO circuit of the present invention is shown in FIG. 18. The mobile device is preferably a two-way communication device having voice and/or data communication capabilities. In addition, the device optionally has the capability to communicate with other computer systems via the Internet. Note that the mobile device may comprise any suitable wired or wireless device such as multimedia player, mobile communication device, digital still or video camera, cellular phone, smartphone, iPhone, PDA, PNA, Bluetooth device, tablet computing device such as the iPad or other iOS device, Android device, Surface, Nexus, Google Glass, etc. For illustration purposes only, the device is shown as a mobile device, such as a cellular based telephone, smartphone or superphone. Note that this example is not intended to limit the scope of the mechanism as the invention can be implemented in a wide variety of communication devices. It is further appreciated the mobile device shown is intentionally simplified to illustrate only certain components, as the mobile device may comprise other components and subsystems beyond those shown.

(98) The mobile device, generally referenced 370, comprises one or more processors 400 which may comprise a baseband processor, CPU, microprocessor, DSP, etc., optionally having both analog and digital portions. The mobile device may comprise a plurality of cellular radios 430 and associated antennas 432. Radios for the basic cellular link and any number of other wireless standards and Radio Access Technologies (RATs) may be included. Examples include, but are not limited to, Third Generation (3G) Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Personal Communication Services (PCS), Global System for Mobile Communication (GSM)/GPRS/EDGE 3G; WCDMA; WiMAX for providing WiMAX wireless connectivity when within the range of a WiMAX wireless network; Bluetooth for providing Bluetooth wireless connectivity when within the range of a Bluetooth wireless network; WLAN for providing wireless connectivity when in a hot spot or within the range of an ad hoc, infrastructure or mesh based wireless LAN (WLAN) network; near field communications; UWB; GPS receiver for receiving GPS radio signals transmitted from one or more orbiting GPS satellites, FM transceiver provides the user the ability to listen to FM broadcasts as well as the ability to transmit audio over an unused FM station at low power, such as for playback over a car or home stereo system having an FM receiver, digital broadcast television, etc.

(99) The mobile device may also comprise internal volatile storage 436 (e.g., RAM) and persistent storage 440 (e.g., ROM) and flash memory 438. Persistent storage 436 also stores applications executable by processor(s) 400 including the related data files used by those applications to allow device 370 to perform its intended functions. Several optional user-interface devices include trackball/thumbwheel which may comprise a depressible thumbwheel/trackball that is used for navigation, selection of menu choices and confirmation of action, keypad/keyboard such as arranged in QWERTY fashion for entering alphanumeric data and a numeric keypad for entering dialing digits and for other controls and inputs (the keyboard may also contain symbol, function and command keys such as a phone send/end key, a menu key and an escape key), headset 388, earpiece 386 and/or speaker 384, microphone(s) and associated audio codec 390 or other multimedia codecs, vibrator for alerting a user, one or more cameras and related circuitry 420, 422, display(s) 434 and associated display controller 426 and touchscreen control 424. Serial ports include a micro USB port 378 and related USB PHY 376 and micro SD port 380. Other interface connections may include SPI, SDIO, PCI, USB, etc. for providing a serial link to a user's PC or other device. SIM/RUIM card 382 provides the interface to a user's SIM or RUIM card for storing user data such as address book entries, user identification, etc.

(100) Portable power is provided by the battery 374 coupled to power management circuitry 372. External power is provided via USB power or an AC/DC adapter connected to the power management circuitry that is operative to manage the charging and discharging of the battery. In addition to a battery and AC/DC external power source, additional optional power sources each with its own power limitations, include: a speaker phone, DC/DC power source, and any bus powered power source (e.g., USB device in bus powered mode).

(101) Operating system software executed by the processor 400 is preferably stored in persistent storage (i.e. ROM 440), or flash memory 438, but may be stored in other types of memory devices. In addition, system software, specific device applications, or parts thereof, may be temporarily loaded into volatile storage 436, such as random access memory (RAM). Communications signals received by the mobile device may also be stored in the RAM.

(102) The processor 400, in addition to its operating system functions, enables execution of software applications on the device 370. A predetermined set of applications that control basic device operations, such as data and voice communications, may be installed during manufacture. Additional applications (or apps) may be downloaded from the Internet and installed in memory for execution on the processor. Alternatively, software may be downloaded via any other suitable protocol, such as SDIO, USB, network server, etc.

(103) Other components of the mobile device include an accelerometer 418 for detecting motion and orientation of the device, gyroscope 417 for measuring or maintaining orientation, magnetometer 416 for detecting the earth's magnetic field, FM radio 412 and antenna 413, Bluetooth radio 408 and antenna 410, Wi-Fi radio 398 including antenna 402 and GPS 392 and antenna 394.

(104) In accordance with the invention, the mobile device 370 comprises one or more oscillator circuits, each incorporating the self injection locked oscillator circuit of the present invention. Numerous embodiments of the mobile device 370 may comprise an oscillator circuit 428 as described supra incorporated in the one or more cellular radios 430; as oscillator circuit 414 as described supra incorporated in the FM radio 412; an oscillator circuit 406 as described supra incorporated in the Bluetooth radio 408; an oscillator circuit 404 as described supra incorporated in the Wi-Fi radio 398; and an oscillator circuit 396 as described supra incorporated in the GPS radio 392.

Internet of Things (IoT) Node Incorporating the Current Switching Oscillator Based DCO

(105) The Internet of Things (IoT) is defined as the network of physical objects or things embedded with electronics, software, sensors and network connectivity, which enables these objects to collect and exchange data. The IoT allows objects to be sensed and controlled remotely across existing network infrastructure, creating opportunities for more direct integration between the physical world and computer-based systems, and resulting in improved efficiency, accuracy and economic benefit. Each thing is uniquely identifiable through its embedded computing system but is able to interoperate within the existing Internet infrastructure. Experts estimate that the IoT will consist of almost 50 billion objects by 2020.

(106) A block diagram illustrating an example IoT node incorporating the oscillator of the present invention is shown in FIG. 19. The example IoT, generally referenced 950, comprises a plurality of nodes 990. The architecture of an example IoT node 952 shown can be fully integrated as a System on Chip (SoC) on a single IC chip in nanoscale CMOS. It contains the radio subsystem to wirelessly communicate with other nodes and gateways 992, application processor to impart a certain amount of local intelligence, sensor and an optional actuator to interface with the environment and energy management to harvest energy (light, heat, vibration or RF power) from the environment and/or convert the voltage levels to those required by the functional circuitry. The RF and non-RF frequency synthesizers provide local oscillator and processor clocks, respectively. A frequency reference 994 provides a fixed clock with excellent long term stability to the frequency synthesizers. In one embodiment, the oscillator of the present invention described supra is incorporated in the RF synthesizer 954 as circuit block 968; non-RF synthesizer 964 as circuit block 966; and/or RF transceiver 958 as circuit block 970.

(107) The RF transceiver 958 interfaces with an antenna 956. The RF signals on the order of 100's of MHz up to several GHz are upconverted and downconverted there to the lower (i.e. baseband) frequencies, which are then processed in the analog baseband circuitry. The conversion from analog to digital (i.e. ADC), and vice versa (i.e. DAC), is also performed there. The digital baseband completes the physical layer of a chosen communication standard. The application processor performs various control and signal processing functions and is responsible for giving a level of intelligence to the IoT node.

(108) The RF frequency synthesizer 954 is realized as an all-digital PLL (ADPLL) and provides a local oscillator signal to the RF transceiver 958. The non-RF frequency synthesizer 964 provides clocks to the digital baseband 962 and application processors 974. The clock frequency has to be dynamically switchable in response to the changing computational load conditions. The energy management (EM) circuitry 972 provides energy conversion between the energy harvester 978 and/or low-capacity storage battery 980 and all the IoT functional circuits. The EM circuit carries out several functions. First, it boosts the voltage from the energy harvester (e.g., light, heat, vibration, RF electromagnetic, etc.) to that required by the nanoscale CMOS circuits, which is in the range of 0.7 to 1.0 V assuming 40 nm CMOS technology. This is performed by a dedicated DC-DC boost converter 976. Second, it down-shifts the energy from a battery, which is on the order of 1.5 to 3.6 V to that required by the nanoscale CMOS circuits. This is performed by a dedicated DC-DC buck converter 976. Third, both boost and buck converters use energy storage passive devices, i.e. capacitor or inductor for storing electrical and magnetic energy, respectively, in order to change the voltage level with high efficiency. The high conversion efficiency must be maintained across the entire range of the allowed loads. Fourth, the EM needs to provide many power supply domains. This is dictated by the different voltage level requirements during voltage scaling. Fifth, the EM supply domains preferably provide individually adjustable voltage levels. The supply voltage level of digital logic circuits widely vary depending on the fast changing real time computational load conditions, while the voltage level of digital RF and analog circuits experience less of such variance, and mainly due to temperature and operating frequency, as well as communication channel conditions. Moreover, the analog circuits have to be properly biased, which normally prevents them from operating at near-threshold conditions.

(109) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms a, an and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises and/or comprising, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(110) The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. As numerous modifications and changes will readily occur to those skilled in the art, it is intended that the invention not be limited to the limited number of embodiments described herein. Accordingly, it will be appreciated that all suitable variations, modifications and equivalents may be resorted to, falling within the spirit and scope of the present invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.