Semiconductor structure having a patterned surface structure and semiconductor chips including such structures

Abstract

A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

Claims

1. A semiconductor structure, comprising: a semiconductor substrate; a metal layer over the semiconductor substrate; a passivation layer over the metal layer, the passivation layer comprising at least one opening; a patterned surface structure comprising portions of the passivation layer located in the at least one opening of the passivation layer and comprising a supporting portion; and a conductive structure comprising a solder material located over the patterned surface structure and in direct contact with the metal layer through the at least one opening of the passivation layer, wherein portions of the conductive structure extend at least partially into the at least one opening of the passivation layer and contact substantially entire upper surfaces and sidewalls of the supporting portion of the patterned surface structure.

2. The semiconductor structure of claim 1, wherein the conductive structure comprises a solder bump or a solder ball.

3. The semiconductor structure of claim 1, wherein the supporting portion of the patterned surface structure comprises at least one of a mesh, regularly aligned pillars, or a concentric cylinder.

4. The semiconductor structure of claim 3, wherein the supporting portion of the patterned surface structure comprises the regularly aligned pillars having a cross section comprising at least one of a polygon, a circle, or an oval.

5. The semiconductor structure of claim 1, wherein the supporting portion of the patterned surface structure is made of at least one inorganic material such as silicon dioxide, silicon nitride, titanium dioxide, aluminum oxide, or at least one organic material such as polyimide, polybenzoxazole (PBO), or a combination thereof.

6. The semiconductor structure of claim 1, wherein the conductive structure comprises at least one of Sn, Ag, Cu, Au, an alloy thereof or a combination thereof.

7. The semiconductor structure of claim 1, wherein the opening of the passivation layer has a shape comprising at least one of a polygon, a circle, or an oval.

8. A semiconductor chip, comprising: a substrate; metal material over the substrate; passivation material over the metal material, the passivation material comprising openings, at least some openings exposing a patterned surface structure comprising portions of the passivation material; and conductive structures comprising a solder material located over the patterned surface structures, extending at least partially into the at least some openings of the passivation material, and in direct contact with the metal material, the conductive structure in contact with substantially entire upper surfaces and sidewalls of the patterned surface structure.

9. The semiconductor chip of claim 8, wherein each of the passivation material and the patterned surface structures comprises a dielectric material comprising silicon dioxide, silicon nitride, titanium dioxide, or a combination thereof.

10. The semiconductor chip of claim 8, wherein the patterned surface structures comprise at least one of a mesh, regularly aligned pillars, or at least one concentric cylinder.

11. The semiconductor chip of claim 10, wherein the patterned surface structures comprise the regularly aligned pillars having a cross section comprising at least one of a polygon, a circle, or an oval.

12. The semiconductor chip of claim 10, wherein the at least one concentric cylinder comprises two concentric cylinders.

13. The semiconductor chip of claim 8, wherein the conductive structures comprise a solder bump or a solder ball.

14. The semiconductor chip of claim 8, wherein the conductive structures comprise at least one of Sn, Ag, Cu, Au, an alloy thereof or a combination thereof.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The disclosure may be more fully understood by reading the following detailed description of the embodiments, with reference made to the accompanying drawings as follows:

(2) FIG. 1 is a cross-sectional view of a connector structure according to various embodiments of the present disclosure;

(3) FIGS. 2A-2C are bottom views along line A-A in FIG. 1 according to various embodiments of the present disclosure;

(4) FIG. 3 is a cross-sectional view of a connector structure according to various embodiments of the present disclosure;

(5) FIGS. 4A-4C are cross-sectional views of intermediate stages during the fabricating of a connector structure according to various embodiments of the present disclosure;

(6) FIGS. 5A-5D are cross-sectional views of intermediate stages during the fabricating of a connector structure according to various embodiments of the present disclosure;

(7) FIGS. 6A-6D are cross-sectional views of intermediate stages during the fabricating of a connector structure according to various embodiments of the present disclosure; and

(8) FIGS. 7A-7D are cross-sectional views of intermediate stages during the fabricating of a connector structure according to various embodiments of the present disclosure.

DETAILED DESCRIPTION

(9) Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

(10) The following embodiments are disclosed with accompanying diagrams for detailed description. For illustration clarity, many details of practice are explained in the following descriptions. However, it should be understood that these details of practice do not intend to limit the present invention. That is, these details of practice are not necessary in parts of embodiments of the present invention. Furthermore, for simplifying the drawings, some of the conventional structures and elements are shown with schematic illustrations.

(11) As mentioned above, the bump is crucial for the connection between the substrate and chip, as the reliability of the bump affects the operation of the whole flip-chip package structure. For better reliability and attachment to the metal pad, the bump is processed through the reflow process. However, the bump often causes chip warpage during reflowing. Accordingly, an improved connector structure and a manufacturing method thereof are required.

(12) The present disclosure provides a connector structure and a method of fabrication thereof. The connector structure has a patterned surface structure, which can improve chip warpage during reflowing. Therefore, the connector structure provided by the present disclosure can avoid chip crack, enhance reliability, and further lower the overall warpage level.

(13) FIG. 1 is a cross-sectional view of a connector structure according to various embodiments of the present disclosure. As shown in FIG. 1, a connector structure 100 includes a semiconductor substrate 110, a metal layer 120, a passivation layer 130, and a conductive structure 140. The semiconductor substrate 110 has a top metal layer 120 thereon. The passivation layer 130 with an opening is over the metal layer 120, and the conductive structure 140 is in contact with the metal layer 120 in a patterned surface structure 142 of the conductive structure 140 through the opening of the passivation layer 130. The patterned surface structure 142 of the conductive structure 140 includes a metal portion 142a and a supporting portion 142b. In some embodiments, it should be noted that the supporting portion 142b of the patterned surface structure 142 may be obtained from a remaining portion of the passivation layer 130, from newly added materials in the opening of the passivation layer 130, or by directly forming the supporting portion 142b in the conductive structure 140. The abovementioned options for obtaining the supporting portions will be discussed in greater detail hereafter (in FIGS. 4A-6D).

(14) In some embodiments, the conductive structure 140 includes a bump or a soldering ball. According to some embodiments, the opening of the passivation layer 130 has a shape comprising a polygon, a circle or an oval. When the shape of the opening is a polygon, examples of the polygon include, but are not limited to, triangle, rectangle, trapezoid, parallelogram, rhombus, pentagon, or hexagon. In some embodiments, the material of the supporting portion 142b of the conductive structure 140 includes, but is not limited to, at least one inorganic material such as silicon dioxide, silicon nitride, titanium dioxide, aluminum oxide, or at least one organic material such as polyimide, polybenzoxazole (PBO), or a combination thereof. In some embodiments, the material of the metal portion 142a of the patterned surface structure 142 is Sn, Ag, Cu, Au, alloy or a combination thereof. In some embodiments, the material of the passivation layer 130 is at least one inorganic material such as silicon dioxide, silicon nitride, titanium dioxide, aluminum oxide, or at least one organic material such as polyimide, polybenzoxazole (PBO), or a combination thereof.

(15) The present disclosure provides a connector structure 100, which has the conductive structure 140 in contact with the metal layer 120 through the patterned surface structure 142. Further, the supporting portion 142b of the patterned surface structure 142 can reduce stress during a reflow process to improve chip warpage. Therefore, the patterned surface structure 142 of conductive structure 140 in the connector structure 100 can avoid chip crack, enhance reliability, and further lower the overall warpage level.

(16) FIGS. 2A-2C are the bottom views along line A-A in FIG. 1 according to various embodiments of the present disclosure. Referring to FIG. 2A, the supporting portion 142b of the patterned surface structure 142 is a mesh in an embodiment. According to another embodiment, FIG. 2B illustrates the supporting portion 142b of the patterned surface structure 142 as regularly aligned pillars. For example, the pillars have a cross section including a polygon, a circle or an oval. In addition, examples of the polygon include, but are not limited to, triangle, rectangle, trapezoid, parallelogram, rhombus, pentagon, or hexagon. FIG. 2B illustrates the pillars with a circular cross section. In some embodiments, the supporting portion 142b of the patterned surface structure 142 is one or more concentric cylinder. FIG. 2C illustrates that the supporting portion 142b of the patterned surface structure 142 is two concentric cylinders.

(17) FIG. 3 is a cross-sectional view of a connector structure according to various embodiments of the present disclosure. As shown in FIG. 3, a connector structure 200 includes a semiconductor substrate 210, a metal layer 220, a passivation layer 230, a conductive structure 240 and an under-bump metallurgy (UBM) layer 250. The semiconductor substrate 210 has a top metal layer 220 thereon. The passivation layer 230 with an opening is over the metal layer 220, and the conductive structure 240 is contacted with the metal layer 220 in a patterned surface structure 242 of the conductive structure 240 through the opening of the passivation layer 230. The patterned surface structure 242 of the conductive structure 240 includes a metal portion 242a and a supporting portion 242b. The UBM layer 250 is disposed between the metal layer 220 and the conductive structure 240, and examples of the material of the UBM layer 250 include, but are not limited to, TiN, Ti, WN, Sn, Ag, Cu, Au, Ni, alloy or a combination thereof. However, FIG. 3 illustrates the embodiments corresponding to the embodiments shown in FIG. 1, and hence the details are not repeated herein. Therefore, similar materials and any details, such as those discussed above with reference to FIG. 1 may be utilized according to some embodiments.

(18) FIGS. 4A-4C are cross-sectional views of intermediate stages during the fabricating of a connector structure according to various embodiments of the present disclosure.

(19) In some embodiments, the present disclosure provides a method of manufacturing a connector structure, such as connector structure 300 (see FIG. 4C). Referring first to FIG. 4A, a metal layer 320 is formed over a semiconductor substrate 310, and then a passivation layer 330 is formed over the metal layer 320. Next, as illustrated in FIG. 4B, the passivation layer 330 is recessed to form an opening 332. As discussed below in greater detail, a photoresist (not shown) is applied onto the passivation layer 330. The passivation layer 330 is subjected to lithography and etching to form the opening 332 with a remaining portion of passivation layer 330 as a supporting portion 334 therein. Continuing in FIG. 4C, metal is applied into the opening 332 (see FIG. 4B), and then the metal is reflowed to form a conductive structure 340 with a patterned surface structure 342. The patterned surface structure 342 includes a metal portion 342a and a supporting portion 334, and is in contact with the metal layer 320 through the opening 332 (see FIG. 4B) of the passivation layer 330. As discussed below in greater detail, examples of the means of applying metal into the opening 332 (FIG. 4B) include, but are not limited to, plating, thermal evaporation or sputtering. In some embodiments, the metal is reflowed by annealing through a reflow oven or under an infrared lamp.

(20) With continued reference to FIGS. 4A-4C, in some embodiments, the material of the supporting portion 334, which is the same as the passivation layer 330, is at least one inorganic material such as silicon dioxide, silicon nitride, titanium dioxide, aluminum oxide, or at least one organic material such as polyimide, polybenzoxazole (PBO), or a combination thereof. The metal portion 342a of the patterned surface structure 342 includes, but is not limited to, Sn, Ag, Cu, Au, alloy or a combination thereof according to some embodiments.

(21) FIGS. 5A-5D are cross-sectional views of intermediate stages during the fabricating of a connector structure according to various embodiments of the present disclosure.

(22) In some embodiments, the present disclosure provides a method of manufacturing a connector structure, such as connector structure 400 (see FIG. 5D). Referring first to FIG. 5A, a metal layer 420 is formed over a semiconductor substrate 410, and then a passivation layer 430 is formed over the metal layer 420. Next, as illustrated in FIG. 5B, the passivation layer 430 is recessed to form an opening 432. As discussed below in greater detail, a photoresist (not shown) is applied onto the passivation layer 430. The passivation layer 430 is subjected to lithography and etching to form the opening 432. Referring now to FIG. 5C, a supporting portion 440 is formed in the opening 432 (see FIG. 5B). According to some embodiments, the supporting portion 440 is made of dielectric material, such as silicon dioxide, silicon nitride, titanium dioxide, or a combination thereof. Continuing in FIG. 5D, metal is applied into the opening 432 (FIG. 5B), and then the metal is reflowed to form the conductive structure 450 with a patterned surface structure 452. The patterned surface structure 452 includes a metal portion 452a and a supporting portion 440, and is in contact with the metal layer 420 through the opening 432 (FIG. 5B) of the passivation layer 430. As discussed below in greater detail, examples of the means of applying metal into the opening 432 (FIG. 5B) include, but are not limited to, plating, thermal evaporation or sputtering. In some embodiments, the metal is reflowed by annealing through a reflow oven or under an infrared lamp. In addition, similar materials such as those discussed above with reference to FIGS. 4A-4C may be utilized according to some embodiments.

(23) FIGS. 6A-6D are cross-sectional views of intermediate stages during the fabricating of a connector structure according to various embodiments of the present disclosure.

(24) In some embodiments, the present disclosure provides a method of manufacturing a connector structure, such as connector structure 500 (see FIG. 6D). Referring first to FIG. 6A, a metal layer 520 is formed over a semiconductor substrate 510, and then a passivation layer 530 is formed over the metal layer 520. Next, as illustrated in FIG. 6B, the passivation layer 530 is recessed to form an opening 532. As discussed below in greater detail, a photoresist (not shown) is applied onto the passivation layer 530. The passivation layer 530 is subjected to lithography and etching to form the opening 532. Referring to FIG. 6C, a conductive structure 540 is formed independently, and has a patterned surface structure 542 with a metal portion 542a and a supporting portion 542b. Continuing in FIG. 6D, the patterned surface structure 542 of the conductive structure 540 is connected to the metal layer 520 through the opening 532 (see FIG. 6B) of the passivation layer 530. In addition, the similar materials such as those discussed above with reference to FIGS. 4A-4C may be utilized according to some embodiments.

(25) According to some embodiments, after recessing the passivation layer and before forming the conductive structure, the method further includes forming an under-bump metallurgy (UBM) layer between the metal layer and the conductive structure. Examples of the method of forming the UBM layer include, but are not limited to, the process as shown in FIGS. 7A-7D.

(26) FIGS. 7A-7D are cross-sectional views of intermediate stages during the fabricating of a connector structure according to various embodiments of the present disclosure.

(27) In some embodiments of the present disclosure provide a method of manufacturing a connector structure 600 (see FIG. 7D). Referring first to FIG. 7A, a metal layer 620 is formed over a semiconductor substrate 610, and then a passivation layer 630 is formed over the metal layer 620. Next, as illustrated in FIG. 7B, the passivation layer 630 is recessed to form an opening 632. As discussed below in greater detail, a photoresist (not shown) is applied onto the passivation layer 630. The passivation layer 630 is subjected to lithography and etching to form the opening 632 with a remaining portion of passivation layer 630 as a supporting portion 634 therein. The opening 632 with the supporting portion 634 has an upper surface. Continuing in FIG. 7C, a UBM layer 640 is formed conformally on the upper surface of the opening 632. Subsequently, referring to FIG. 7D, the metal is applied into the opening 632 (see FIG. 7B), and then the metal is reflowed to form the conductive structure 650 with a patterned surface structure 652. The patterned surface structure 652 includes a metal portion 652a and a supporting portion 634, and is in contact with the metal layer 620 through the opening 632 (FIG. 7B) of the passivation layer 630. As discussed below in greater detail, examples of the means of applying metal into the opening 632 (FIG. 7B) include, but are not limited to, plating, thermal evaporation or sputtering. In some embodiments, the metal is reflowed by annealing through a reflow oven or under an infrared lamp. In addition, similar materials such as those discussed above with reference to FIGS. 4A-4C may be utilized according to some embodiments.

(28) The embodiments of the present disclosure discussed above have advantages over existing connector structures and processes, and the advantages are summarized below. The bump often causes chip warpage during reflowing. Instead, the present disclosure provides an improved connector structure and a manufacturing method thereof. The conductive structure of the connector structure can contact with the metal layer through the patterned surface structure. Furthermore, the patterned surface structure includes a metal portion and a supporting portion. The supporting portion can reduce stress during reflowing, so as to improve the issue of chip warpage. To summarize the above points, the patterned surface structure of the conductive structure in the connector structure can improve chip warpage during reflowing to avoid chip crack, enhance reliability, and further lower the overall warpage level.

(29) Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

(30) It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the appended claims.