FAULT TOLERANT CONVERTER TOPOLOGY

Abstract

A power inverter topology for converting a DC input to one or more phases of AC output, and methods for operating the same. The power inverter includes a switching circuit, an input circuit and a freewheeling diode bridge arrangement. The switching circuit comprises switch arms extending between the upper and lower branches of the switching circuit. The input circuit includes upper and lower isolating switches that can be selectively operated to respectively isolate the upper and/or lower branches of the switching circuit.

Claims

1. A power inverter for converting a DC input to one or more phases of AC output, the power inverter comprising: a switching circuit comprising an upper branch, a lower branch, and a respective switch arm for each phase of the AC output, each switch arm extending between the upper and lower branches and comprising an upper branch switch and a lower branch switch, wherein the upper and lower branch switches are positioned on either side of the switch arm output; an input circuit comprising upper and lower isolating switches that can be selectively operated to respectively isolate the upper and/or lower branches of the switching circuit; and a respective one or more diode bridge arm for each switch arm of the switching circuit, the one or more diode bridge arm for a switch arm providing freewheeling paths to the upper branch for the respective upper and lower branch switches of the switch arm.

2. The power inverter of claim 1, wherein the upper and lower isolating switches are connected between the diode bridge arms' connections to the upper and lower branches and the switch arms.

3. The power inverter of claim 1, wherein each switch arm further comprises respective diodes connected in series with the upper and lower branch switches.

4. The power inverter of claim 1, wherein at least one of the upper and lower isolating switches comprises a desaturation protection circuit.

5. The power inverter of claim 4, wherein the switch arms are not provided with separate desaturation protection circuits.

6. The power inverter of claim 1, wherein the power inverter provides at least two phases of AC output.

7. The power inverter of claim 6, wherein the power inverter provides three phases of AC output.

8. A motor drive circuit comprising: a motor; and one or more power inverters according to claim 1.

9. The motor drive circuit of claim 8, comprising at least two power inverters, each power inverter associated with a separate power channel of the motor, the separate power channels providing redundancy.

10. The motor drive circuit of claim 8, wherein the motor is a permanent magnet motor.

11. A method of monitoring faults within a system comprising a power inverter as claimed in claim 1, the method comprising: in response to one or more of the switches within the switching circuit experiencing a short circuit fault; and operating at least one of the upper and/or lower isolation switches to manage the fault.

12. The method of claim 11, wherein operating at least one of the upper and/or lower isolation switches to manage the fault comprises opening the upper and/or lower isolation switches to isolate the fault.

13. The method of claim 11, wherein operating at least one of the upper and/or lower isolation switches to manage the fault comprises operating the upper and/or lower isolation switches to provide AC output.

14. The method of claim 13, wherein operating the upper and/or lower isolation switches to provide AC output comprises repeatedly switching at least one of the upper and/or lower isolation switches on and off over successive periods.

15. The method of claim 11, wherein operating at least one of the upper and/or lower isolation switches to manage the fault comprises operating the power inverter in a reverse power generation mode in which the power inverter produces DC power at its input.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0025] Various embodiments will now be described, by way of example only, with reference to the drawings.

[0026] FIG. 1 is a schematic diagram of an example of a duplex permanent magnet motor drive system.

[0027] FIG. 2 is a schematic diagram showing an example of an existing two-level three-phase inverter topology.

[0028] FIG. 3 is a schematic diagram showing an example OSSC fault in the inverter topology of FIG. 2.

[0029] FIG. 4 is a schematic diagram of an OSSC fault tolerance converter topology according to an embodiment.

[0030] FIGS. 5a-f show simulated results for a method of OSSC fault isolation according to an embodiment.

[0031] FIGS. 6a-f show simulated results for a method of OSSC fault management in a motoring mode according to an embodiment.

[0032] FIGS. 7a-f show simulated results for a method of OSSC fault management in a generating mode according to an embodiment.

[0033] FIG. 8 is a schematic diagram showing an example of a generalised n−-phase inverter topology according to an embodiment.

[0034] Like reference numerals are used for like components where appropriate in the Figures.

DETAILED DESCRIPTION

[0035] As briefly described above, FIG. 1 shows an example motor drive for a permanent magnetic motor 108. In the system 100 of FIG. 1, the duplex permanent magnet motor comprises two segregated windings, with each winding being driven by a respective, separate channel. The system controller 102 is therefore operably connected to the permanent magnetic motor 108 via two channels 104, 106, each channel comprising a respective inverter circuit 104a, 106a that provides one or more phases of AC output to its respective motor winding. The use of two separate inverters 104a, 106a each corresponding to one of the channels 104, 106 provides redundancy in the system, as the second inverter (e.g. 106a) is able to take over and control the motor torque in the event that the first inverter (e.g. 104a) develops a fault. This duplex arrangement is therefore particularly suitable for safety critical applications such as for driving electric motors within aircrafts, such as for High Lift Systems. However, different numbers of channels and inverters may of course be used, as desired.

[0036] FIG. 2 shows an example of a more conventional two-level three-phase inverter circuit 200 that could be used for the respective channels of the system 100 of FIG. 1. Thus, as shown in FIG. 2, the inverter output is operably connected to the windings 202a of the first channel which are wound about a permanent magnetic motor 108. Although not shown in FIG. 2, it will be understood that a second equivalent inverter system will be provided for the windings 202b of the second channel.

[0037] The inverter circuit 200 in FIG. 2 comprises six switches, including three top switches 204a,b,c and three bottom switches 206a,b,c. Each switch 204/206 is connected in parallel with a respective freewheeling diode 208. Under normal operating conditions, the switches are operable to control the inverter output, e.g. in the normal manner for a switching inverter.

[0038] FIG. 3 shows schematically the current flow in the inverter circuit 200 of FIG. 2 in the event of an OSSC fault. In this example, a short circuit 302 has occurred at top switch 204a. As a result, currents 304 flow via the short circuited path 302. The resulting waveforms from the flow of currents 304 will produce torque ripples and power losses in the motor, as well as drag torque. The inverter is thus no longer able to control the motor current.

[0039] An inverter topology according to an embodiment will now be described that provides a means to effectively manage OSSC and other short circuit fault conditions. As will be described below, in various operation modes the OSSC fault tolerant (OSSCFT) inverter topology of the present embodiment may substantially eliminate motor drag torque and/or allow the channel experiencing the OSSC fault to still produce at least some useful torque in order to assist the healthy channel, thereby allowing a reduction in the overall system size.

[0040] FIG. 4 shows an example of a channel for a permanent magnet motor drive system including a two-level three-phase inverter having an OSSCFT topology in accordance with an embodiment. It will be understood that the permanent magnetic motor drive system may further comprise one or more additional channels, each of which may comprise their own (corresponding) inverter circuits. These additional inverter circuits may each, and in the present embodiment do, have the same topology as inverter 400.

[0041] The inverter 400 comprises a switching circuit including three switch arms extending between upper and lower DC buses (generally, upper and lower ‘branches’) of the switching circuit, each switch arm providing a respective AC output phase. It will be understood that the number of switch arms in the inverter 400 correlates with the number of desired output phases (i.e. three, in this example), and that the inverter may comprise a different number of switch arms if desired, including but not limited to 1, 2, 3, 4 or more switch arms corresponding to respective single-, two-, three-, four-, etc. phase output topologies. A generalised n-phase inverter topology is shown in FIG. 8.

[0042] Each switch arm of inverter 400 comprises two switches, including an upper branch switch 404a,b,c and a lower branch switch 406a,b,c. The upper branch 404 and lower branch 406 switches are paired along respective their switch arms on different sides of the respective switch arm output 412. In inverter 400, each switch 404, 406 is paired in series with a reverse current blocking diode 408 to inhibit current flow in an undesired direction. Other arrangements would of course be possible. For example, some unidirectional switches, such as a Gate Turn-Off Thyristor (GTO) type switch, are operable to withstand a sufficient reverse voltage. As such, diodes 408 are not strictly essential.

[0043] The switches in the switching circuit may be designed in any suitable and desired way. For instance, in embodiments, the switches 404, 406 may comprise IGBT, MOSFET or GTO type switches. However, other arrangements would of course be possible. The switches 404, 406 are, in normal operation, controlled to generate the desired AC output phases. Thus, in normal (healthy) operation of the inverter, a DC voltage is applied across the upper and lower branches and the switching circuit is operated to convert the input DC voltage to one or more AC phases, e.g. in the normal manner for a switching inverter.

[0044] Thus, in normal (healthy) operation, the inverter according to the FIG. 4 embodiment acts similarly to the more conventional inverter that is shown in FIG. 2. However, and as will be explained further below, the inverter according to the present operation is able to better handle short circuit faults such as OSSC faults.

[0045] To facilitate this, in addition to the various switches 404, 406 within the switching circuit, the inverter 400 according to the present embodiment further comprises upper and lower isolation switches, 402a,b that are selectively operable to respectively isolate the upper and lower branches of the switching circuit. As such, the upper branch isolation switch 402a is operable to isolate all of the upper branch switches 404a,b,c for the switch arms, and the lower branch isolation switch 402b is correspondingly operable to isolate all of the lower branch switches 406a,b,c. The isolation switches 402a,b in embodiments are thus configured to act as Solid State Circuit Breakers. In embodiments, the isolation switches 402a,b are current overrated with wide safe operating area compared to the switches 404,406 of the switching circuit.

[0046] A controller for the system that the inverter is part of is thus operable to detect a short circuit of either the switch or the switch and the associate reverse blocking diode, such as OSSC faults, and in response to this, control the isolation switches 402a,b appropriately. Various examples of the OSSC fault management will be described further below.

[0047] In order to provide freewheeling paths to the upper branch (DC bus), the inverter further comprises, for each switch arm (phase), a respective diode bridge arm, such that the freewheeling diode bridge arms collectively form a freewheeling diode bridge. Thus, as shown in FIG. 4, each winding phase of the motor is operably connected to the inverter 400 via a respective switch arm and a respective freewheeling diode bridge arm 410a,b,c. In particular, in FIG. 4, the upper and lower branch switches of each switch arm (e.g. switch pairs 404a and 406a, 404b and 406b, etc.) share a corresponding freewheeling diode bridge arm (e.g. 410a, 410b, etc.). Thus, FIG. 4 shows a three-phase diode bridge arrangement, with each output phase (switch arm) having its own diode bridge arm providing a respective freewheeling path to the upper branch. Note that the diode bridge arms are connected to the upper branch upstream of the isolation switches so that when the isolation switches are open, the freewheeling current cannot flow back into the motor windings. Although in FIG. 4 each switch arm has a single corresponding diode bridge arm this is not strictly necessary and, for instance, each of the switches 404a, 404b, 406a, etc. could have its own diode bridge arm, so long as these provide suitable freewheeling paths to the upper branch for each of the switches.

[0048] That is, however the freewheeling paths are arranged in the present embodiment, all of the switches should have a freewheeling path (directly) to the upper branch, and upstream of the isolation switch. This helps to ensure that in the event of switch failure the freewheeling current can be handled appropriately, without generating motor drag. This is contrast to the more conventional arrangement shown in FIG. 2 where each switch has its own parallel freewheeling diode, which can lead to the issues illustrated in FIG. 3.

[0049] As shown in FIG. 4, the upper branch isolation switch 402a may be associated with a desaturation protection (Dsat) circuit. Alternatively/additionally, this could be provided on the lower branch isolation switch 402b. However, it is a benefit of the present embodiment that only a single desaturation protection circuit is required in order to be able detect the shoot-through current, in comparison to at least three such circuits (e.g. on at least one switch of each switch arm) that may be required in a topology without isolation switches 402a,b, such as that shown in FIG. 2. Thus, in the present embodiment, the switches 404,406 within the switching circuit can be protected only by the desaturation protection circuit associated with the isolation switch, and do not require their own, respective desaturation protection (and so in embodiments these are not provided).

[0050] The two-level three-phase inverter topology according to the present embodiment may thus generally be comprised of the following components:

[0051] Six discrete switches, (s.sub.1, s.sub.2, s.sub.3, s.sub.4, s.sub.5, s.sub.6). These may be unidirectional switches. As mentioned above, the switches may be based on either IGBT, MOSFET or GTO technologies. Other examples would however be possible.

[0052] Optionally six reverse blocking discrete diodes, (D.sub.1, D.sub.2, D.sub.3, D.sub.4, D.sub.5, D.sub.6) connected in series with the above-mentioned switches.

[0053] Two DC bus isolation switches, S.sub.T and S.sub.B, acting as Solid State Circuit Breaker (SSCB).

[0054] Respective diode bridge arms, for each switch arm (for each phase), that provide the freewheeling paths to the upper branch of the inverter.

[0055] A desaturation (Dsat) protection circuit associated with one of the isolation switches and arranged for detecting the shoot through current.

[0056] Under normal (active) operation conditions, the isolation switches 402a,b may generally be maintained in an always on state and as a result the inverter 400 may operate substantially in line with conventional two-level voltage source inverters.

[0057] However, in the event of a failure of one or more of the upper branch switches 404a,b,c and/or the associated reverse blocking diode resulting in either a unidirectional or bidirectional short circuit fault across the respective switch (e.g. an OSSC fault), the fault may be isolated and/or managed using the upper branch isolation switch 402a. Thus, in case, one of the upper branch switches fails, it may be sufficient to switch off the upper branch isolation switch to isolate and manage the fault. Similarly, a fault resulting from a failure of one or more of the lower branch switches 406a,b,c and/or the associated reverse blocking diode may be isolated and/or managed using the lower branch isolation switch 402b.

[0058] Moreover, in the event of a short circuit fault of any of switches 404, 406 and/or associated reverse blocking diodes (such as an OSSC fault), the presence of the isolation switches means that the OSSCFT inverter 400 according to the present embodiment is also still able to produce useful output for (assisting) motoring by controlling the remaining (operational) switches and isolation switches 402a,b. That is to say that, in contrast to existing motor inverter topologies, a faulty OSSCFT inverter 400 can be operated such that it continues producing useful motoring torque, and as a result the overall size of the motor drive system can be reduced. For instance, the isolation switches can be switched on and off in order to provide some useful AC output.

[0059] Indeed, a benefit of the present embodiment is that inverter can be operated in various different fault management modes using the isolation switches. That is, the novel topology shown in FIG. 4 allows for various novel operation modes that can provide improved performance in the event of an OSSC fault.

[0060] Simulated results of various operating modes for the inverter 400 under an OSSC fault condition are discussed below. It will be understood that these operation modes are provided as illustrative examples. The following examples are provided to demonstrate some of the advantages of the OSSCFT inverter topology of the present embodiment. In each of these simulations, one of the upper branch switches (e.g. 404a) associated with the upper isolation switch S.sub.T (e.g. 402a) develops or has developed an OSSC fault.

[0061] FIGS. 5a-f show simulated results of operating the OSSCFT inverter topology in an isolation mode. Prior to 0.03 seconds, the motor is operating in a motoring mode at a constant speed. As such, the phase current waveforms are sinusoidal and the motor power Pe is constant.

[0062] At time 0.03 seconds the OSSC fault is detected in a switch (e.g. 404a). In response, the top and bottom isolation switch (e.g. 402a,b) are opened, as shown in FIGS. 5c and d. Alternatively, in other operating modes only one of the top and bottom isolation switches may be opened. Any remaining operational switch arm switches (e.g. switches 404b,c and 406a,b,c) may also be switched off at this same time. After the isolation switches are opened, the switching circuit is isolated, and the transient motor phase currents freewheel through the diode bridge arms to the upper branch (DC bus) without causing any overvoltage to the switch arm switches. The motor phase currents, as well as the currents on the upper branch (DC bus) and in the upper branch isolation switch then decay quickly to zero, as shown in FIGS. 5a, b, e and f. The faulty channel therefore does not result in motor drag torque. The channel is therefore isolated and the control can be switched to the other (healthy) channel appropriately without the healthy channel having to compensate for motor drag due to the faulty channel.

[0063] As discussed above, in addition to allowing a channel to isolated, the OSSFT inverter topology of the present embodiment also enables the continued production of useful motoring power, even under OSSC fault conditions. For instance, even though one of the switches (and/or the associated reverse blocking diode) has short circuited, and so cannot be controlled to produce motoring power, some useful AC output can nonetheless be generated by appropriate switching of the isolation switches and the remaining inverter switches. That is, in the event of a fault within the switching circuit, that means the switching circuit switches cannot be controlled to produce AC output, the isolation switches can be operated with the remaining switches in an analogous manner in order to provide an AC output.

[0064] FIGS. 6a-f show the simulated results of operating the OSSCFT inverter topology in one such motoring assistance fault management operating mode. In this example, both of the top and bottom isolation switches are simultaneously switched on and off for successive 0.01 second periods, as shown in FIGS. 6c and d.

[0065] In this operating mode, the OSSCFT inverter topology thus enables a degree of control of the motor current and thereby assist in the production of motoring power via the extraction of positive torque during the periods in which the isolation switches are switched on, as shown in FIG. 6b. During the periods in which the isolation switches are switched off, the motor current freewheels to the DC bus and decays to zero relatively quickly, as shown in FIGS. 6a and e.

[0066] In some embodiments, the switch periods may be equal to 180° of the fundamental motor period, such that the isolation switches are switched on for 180° of the fundamental motor period and switched off for the other 180° of the fundamental motor period. This alternating 180° operating sequence therefore produces motoring power pulses with 50% duty cycle and with a repeating frequency equal to the fundamental frequency of the motor.

[0067] In any case, the OSSCFT inverter topology enables a faulty channel to continue producing at least some useful motoring torque to assist any remaining healthy channels, and/or enable at least partial operation of the motor.

[0068] The expected switching stress of this method may be reduced by operating the isolation switches at a frequency below the fundamental frequency of the motor. For example, for a motor designed for a fundamental frequency of 900 Hz, the switching frequency of the isolation switches may be less than 900 Hz.

[0069] A further example of a fault management operation mode is shown in FIGS. 7a-f. In this example, the OSSCFT inverter topology is operating in reverse as a converter under a generation assistance fault management operating mode, to provide high quality (i.e. constant) generating power to assist the healthy channel. For instance, it will be understood that inverter 400 may also be operated in reverse as a converter to generate power and/or torque, i.e. in a generating mode of operation.

[0070] As shown in FIGS. 7c and 7d, in this operating mode the upper isolation switch ST corresponding to the faulty switch (e.g. switch arm switch 404a) is switched off while the lower isolation switch SB remains switched on. The remaining operational switch arm switches can then be switched on and off in accordance with current controller command signals to thereby produce a constant generating power as shown in FIGS. 7a and 7b.

[0071] Under these conditions, the OSSCFT inverter topology may be operated to control the motor current to produce constant generating power for the entire 360° of the fundamental motor period (as shown by FIGS. 7b and e).

[0072] Hence, even after developing an OSSC fault, the OSSCFT inverter topology can still be operated as a converter to deliver high quality generating power, and therefore assist any remaining healthy channels with the generation of power. This operational mode assists in reducing overall system power losses and thermal stresses, and thereby may also increase the operational lifetime of the system.

[0073] Thus, the inverter topology according to the present embodiment provides full management and isolation capability to the most critical OSSC fault condition. It also provides full freewheeling functionality to the motor current and hence prevents overvoltage during switching of converter switches in normal and faulty operating conditions. Furthermore, this is achieved by the addition of only two additional switches and a diode bridge in comparison to a more conventional two-level converter topology. The present embodiment thus provides various benefits compared to more conventional approaches.

[0074] FIG. 8 shows a schematic of a generalised n-phase inverter topology 800 according to an embodiment. Inverter circuit 800 comprises n switch arms 802 and n corresponding diode bridge arms 804 collectively forming an n-phase freewheeling diode bridge arrangement.

[0075] The inverter topology according to the present embodiment is particularly suitable for improving reliability of PMM drive systems. For instance, in embodiments, the following advantages may be provided:

[0076] No drag torque under OSSC fault condition and hence no need to oversize the motor drive system; Capability of providing assistance motoring power/torque while under OSSC fault; Capability of providing high performance and high quality generating power/torque and sharing the load power while under OSSC fault condition; Simple shoot through protection, which can be achieved by deploying only one Dsat circuit to the gate drive of either S.sub.T or S.sub.B; and Potential of reducing the size of motor drive system for fault tolerant application.

[0077] While the above examples have been provided primarily with reference to example three-phase inverter topologies, embodiments of the invention extends to other configurations of inverter topologies, including but not limited to single-phase topologies (such as 1, 2, 3, 4, etc.-phase topologies) and multiple three-phase topologies (such as 3, 6, 9, etc.-phase topologies). In each case, it will be understood that the number of components such as switches and freewheeling diodes may be varied accordingly.

[0078] It will be further understood that while the above embodiments of the present invention have been described with reference to a single level inverter that provides power directly to the windings of a motor, the inverter may instead be incorporated into a multi-level system and instead be configured to receive and/or provide AC output current to another or other inverter(s).

[0079] Additionally, while the above examples have been provided primarily with reference to example dual channel systems, embodiments of the invention further extend to permanent magnet motor drive systems with different numbers of inverters and/or channels, including but not limited to single channel, dual channel, triple channel, etc. motor drive systems.

[0080] Variations on the examples described above fall within the scope of the claims.