LINEAR REGULATOR WITH REAL-TIME FREQUENCY COMPENSATION FUNCTION

Abstract

The present invention relates to a linear regulator with real-time frequency compensation function, which belongs to the technical field of analog integrated circuits. The part of frequency compensation of the present invention includes the dual-frequency compensation networks and compensation transfer switcher, and the pulse delay circuit. The dual-frequency compensation networks and compensation transfer switcher provide the corresponding frequency compensation for linear regulator under two different capacitive loads. The pulse delay circuit generates a set of signals which have a delay related to the switch-pulse signals to control the access of the compensation transfer switcher and capacitive load. The advantages of the present invention are that the circuit structure is simple, without complex feedback control circuits, the excessive power dissipation is extremely low, and it is applied to such special use of linear regulator with switched capacitive load that it can option the loop frequency compensation in real-time to ensure the linear regulator has the optimal stability and load transient response.

Claims

1. A linear regulator with real-time frequency compensation function, the linear regulator comprising: an error amplifier EA, a regulate transistor M.sub.P, a capacitive load C.sub.G controlled by switching pulse signals, dual-frequency compensation networks, a compensation transfer switcher, and a pulse delay circuit, the non-inverting input of the error amplifier EA connects to the output of the linear regulator V.sub.o, and the inverting input of the error amplifier EA connects to a reference voltage V.sub.REF, the output of the error amplifier EA connects to the gate of the regulate transistor M.sub.P, the source of the regulate transistor M.sub.P connects to a power source, and the drain of the regulate transistor M.sub.P connects to the output of the linear regulator V.sub.o, the capacitive load C.sub.G controlled by the switching signals is connected between the ground and the drain of the regulate transistor M.sub.P, one port of the dual-frequency compensation networks and compensation transfer switcher connects to the output of the error amplifier EA and the gate of the regulate transistor M.sub.P, and another port of the dual-frequency compensation networks connects to the output of the linear regulator or connects to ground, a control port of the dual-frequency compensation networks and compensation transfer switcher connects to switching pulse signals .sub.1, an input port P.sub.i of the pulse delay circuit connects to the switching pulse signals .sub.1, and an output port P.sub.o of the pulse delay circuit connects to the control switcher of the capacitive load C.sub.G.

2. A linear regulator according to claim 1, wherein the dual-frequency compensation networks and compensation transfer switcher includes a first compensation network, a second compensation network, and a compensation transfer switcher, wherein the compensation transfer switcher is used for controlling and real-time switching the connection ways of the first compensation network and the second compensation network which includes at least one of connecting one of the two compensation networks, connecting both of the two compensation networks in parallel, and connecting both of the two compensation networks in series.

3. A linear regulator according to claim 1 wherein the pulse delay circuit provides a fixed-delay time to make the compensation networks switch earlier than connecting to the switch of the capacitive load of the linear regulator.

4. A linear regulator according to claim 1 wherein the first compensation network and the second compensation network are used for providing the corresponding frequency compensation for the linear regulator under two different capacitive loads.

5. A linear regulator according to claim 2 wherein the first compensation network and the second compensation network are used for providing the corresponding frequency compensation for the linear regulator under two different capacitive loads.

Description

DESCRIPTION OF FIGURES

[0016] FIG. 1 is the structure diagram of traditional linear regulator, wherein (a) using P-type regulate transistor, (b) using N-type regulate transistor;

[0017] FIG. 2 illustrates the application of the linear regulator in half-bridge MOSFET driver circuit and the capacitive load thereof;

[0018] FIG. 3 is the relationship diagram of the state of the MOSFET and the capacitive load of the linear regulator;

[0019] FIG. 4 is the applied principle diagram of the frequency compensation technology of the present invention;

[0020] FIG. 5 is an implementation diagram of the frequency compensation technology of the present invention;

[0021] FIG. 6 shows other equivalence structures of the frequency compensation technology of the present invention;

[0022] FIG. 7 is a practical application circuit diagram of the frequency compensation technology of the present invention;

[0023] FIG. 8 is the diagram of improvement of the capacitive load transient response of the linear regulator with the technology of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0024] Based on the drawings and the embodiment, the specific implementation methods of the invention are described as follows:

[0025] A circuit of the technology of the present invention is shown in FIG. 7. It is the application of the technology in the linear regulator of the MOSFET driver. The structure of the circuit comprises the PMOS transistors M3, M4, M5, M.sub.P, M.sub.C, and the NMOS transistors M1, M2, M6, and the inverters X1, X2, X3, the current source I.sub.BIAS, the reference voltage source V.sub.REF, the resistors R.sub.C1, R.sub.C2, and the capacitors C.sub.C, C.sub.G. The gate of M1 connects to the positive pole of V.sub.REF, the source thereof connects to the negative pole of I.sub.BIAS and the drain thereof connects to the drain of M3. The negative pole of the reference voltage source connects to the ground. The positive pole of the current source I.sub.BIAS connects to the ground. The source of M2 connects to the negative pole of I.sub.BIAS and connects to the source of M1 at the same time, the gate thereof connects to the voltage-stabilized output node V.sub.o, and the drain thereof connects to the drain of M4. The gate of M3 connects to the gate of M4, and connects to the drain of M3 and the drain of M1, and the source thereof connects to the power source VDD. The source of M4 connects to the power source VDD and the drain thereof connects to the drain of M2 and connects to the gate of M.sub.P. The source of M.sub.P connects to the power source VDD and the drain thereof connects to the voltage-stabilized output node V.sub.o. R.sub.C1, R.sub.C2 and C.sub.C are connected in series. R.sub.C1 connects to the voltage-stabilized output node V.sub.o. The node of C.sub.C connects to the gate of M.sub.P, to the drain of M2 and M4. The source of M.sub.C connects to the voltage-stabilized output node V.sub.o, the drain thereof connects to the connection between R.sub.C1 and R.sub.C2, and the gate thereof connects to the switching pulse signal .sub.1. The inverters X1, X2, X3 connect in series, i.e. the output of X1 connects to the input of X2, the output of X2 connects to the input of X3, and the input of X1 connects to the switching pulse signal .sub.1, the output of X3 connects to the gate of M5 and M6. M5 and M6 form the last inverter of the MOSFET driver. Their gates and drains are connected. The source of M5 connects to the voltage-stabilized output node V.sub.o. The source of M6 connected to the ground. The gate capacitance of the power MOSFET is equal to C.sub.G, which is connected between the ground and the drain of M5 and M6.

[0026] In the embodiment, M1, M2, M3, M4, I.sub.BIAS constitute the error amplifier; R.sub.C1 constitutes the compensation network 1; C.sub.c constitutes the compensation network 2; M.sub.C is the compensation transfer switcher; X1, X2, X3 connection in series constitute the pulse delay circuit; M.sub.P is the regulate transistor of the linear regulator. C.sub.G is the equivalent gate capacitance of the MOSFET M.sub.N; M5, M6 and C.sub.G constitute the switched capacitive load of the output of the linear regulator.

[0027] The operating principle of the embodiment is:

[0028] M1M4 constitute a typical one stage error amplifier, wherein non-inverting input connects to the reference voltage source V.sub.REF and inverting input connects to the voltage-stabilized output node V.sub.o, And constitutes the linear regulator with the regulate transistor M.sub.P. It is possible to obtain the low-frequency gain of the regulator:

|A.sub.V|g.sub.m1r.sub.o3g.sub.mpr.sub.op

wherein g.sub.m1 and g.sub.mp separately indicate the transconductance of M1 and M.sub.P. And r.sub.ol, r.sub.op indicate the small-signal output impedance of M1 and M.sub.P. Considering the frequency characteristic of the regulator, there are two poles in the system before adding the compensation circuits and the AC small signal gain can be expressed as below:

[00001]$A_V\left(s\right)=\frac{.Math.A_V.Math.}{\left(\frac{s}{p_1}+1\right).Math.\left(\frac{s}{p_2}+1\right)}\frac{g_{m.Math..Math.1}.Math.r_{o.Math..Math.3}.Math.g_{\mathrm{mp}}.Math.r_{\mathrm{op}}}{\left(\frac{s}{p_1}+1\right).Math.\left(\frac{s}{p_2}+1\right)}$

[0029] Wherein, the pole 1 locates in the output node of the error amplifier, and the pole 2 locates in the output node V.sub.o of the linear regulator. After the pole 1 introducing the miller compensation, the pole 1 becomes the main pole and it introduces a zero at the same time:

[00002]${}_z\frac{1}{C_c\left(\frac{1}{g_{\mathrm{mp}}}-R_c\right)}$

[0030] The position of the zero is usually located in between the position of pole 1 and pole 2. Therefore, the system is stable before adding the capacitive load C.sub.G. When C.sub.G is added, the position of pole 2 has changed. The capacitance of the node of C.sub.G has increased more than 100 times. The position of the pole may near the pole 1 and zero, even between the position of pole 1 and zero, which results to the decrease of phase margin.

[0031] The formula of the position of pole 2 can be expressed as follow:

[00003]${}_{p.Math..Math.2}\frac{1}{C_G.Math.r_o}$

[0032] After introducing the compensation transfer switcher M.sub.C, when it turns off, it increases the value of zero compensation resistance R.sub.C without introducing C.sub.G. According to the formula, the increasing of R.sub.C can lower the position of the zero frequency. Therefore, the position of zero frequency will decrease with M.sub.C turning off and increase with M.sub.C turning on. By use of the signal .sub.1 to control M.sub.C can make the position of compensation zero move simultaneously with pole p.sub.2.

[0033] As the value of the gate capacitance C.sub.G of MOSFET is known, if the value of R.sub.C1 and R.sub.C2 can be designed accurately according to the changing of pole 2 which is introduced by C.sub.G, it can be ensured that the system will always have enough phase margin whether the C.sub.G has been introduced to the load of the regulator or not when the compensation zero is lower than or near the position of pole 2.

[0034] By use of the technology of the present invention, the capacitive load transient response of the circuit of the embodiment is improved to some extent. By comparing with the software simulation, the ware-form of the transient response is shown in FIG. 8. The time of transient response is a little longer without using the technology of the present application and it is about 6.6 s, while with applying the technology, the transient response is faster and its setup time is about 3.1 s. It can be seen that by use of the frequency compensation technology, the performance of the capacitive load transient response of the linear regulator can be improved more than 50% by comparing with the traditional frequency compensation technology.