Fully-differential two-stage operational amplifier circuit

Abstract

A fully-differential two-stage operational amplifier circuit is provided, and it includes a first-stage amplification circuit, a second-stage amplification circuit, a common-mode signal acquisition circuit, a common-mode feedback circuit and a bias circuit. The first-stage amplification circuit has a telescopic structure and receives differential input signals IN.sub.P and IN.sub.N. The second-stage amplification circuit has a common-source structure and outputs differential output signals OUT.sub.P and OUT.sub.N. The common-mode signal acquisition circuit receives differential output signals, and outputs an operational amplifier output common-mode signal V.sub.CMO. The common-mode feedback circuit outputs common-mode feedback signals VB.sub.1 and VB.sub.2 to the first-stage amplifier circuit and the second-stage amplifier circuit respectively; The bias circuit outputs a bias voltage VB.sub.3 to the first-stage amplifier circuit, and outputs bias voltages VB.sub.4 and VB.sub.5 to the first-stage amplifier circuit respectively.

Claims

1. A fully-differential two-stage operational amplifier circuit, comprising a first-stage amplification circuit, a second-stage amplification circuit, a common-mode signal acquisition circuit, a common-mode feedback circuit, and a bias circuit; wherein the first-stage amplification circuit has a cascade structure, and the first-stage amplification circuit receives differential input signals IN.sub.P and IN.sub.N; the second-stage amplification circuit has a common-source structure, and the second-stage amplification circuit outputs differential output signals OUT.sub.P and OUT.sub.N; the common-mode signal acquisition circuit receives the differential output signals OUT.sub.P and OUT.sub.N, and outputs an operational amplifier output common-mode signal V.sub.CMO; the first-stage amplification circuit is connected with the second-stage amplification circuit; the common-mode feedback circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, a source of the first PMOS transistor and a source of the second PMOS transistor being respectively connected with an external power supply VDD, and a gate of the first PMOS transistor being respectively connected with a drain of the first PMOS transistor and a drain of the first NMOS transistor, a gate of the second PMOS transistor being connected to a drain of the second PMOS transistor and a drain of the second NMOS transistor respectively, a source of the first NMOS transistor being connected to a source of the second NMOS transistor, a gate of the first NMOS transistor receiving an external input reference signal V.sub.CM, a gate of the second NMOS transistor receiving the operational amplifier output common-mode signal V.sub.CMO, and the drain of the second PMOS transistor and the drain of the first PMOS transistor respectively outputting common-mode feedback signals VB.sub.1 and VB.sub.2 to the first-stage amplification circuit and the second-stage amplification circuit; and the bias circuit comprises a resistor R.sub.0, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor and a sixth NMOS transistor, a positive terminal of the resistor R.sub.0 receiving a reference current i.sub.ref, and the positive terminal of the resistor R.sub.0 being connected with a gate of the third NMOS transistor and a gate of the fifth NMOS transistor respectively, a negative terminal of the resistor R.sub.0 being connected with a drain of the fifth NMOS transistor, a gate of the sixth NMOS transistor and a gate of the fourth NMOS transistor respectively, a source of the fifth NMOS transistor being connected with a drain of the sixth NMOS transistor, a drain of the third NMOS transistor being connected with the source of the first NMOS transistor and the source of the second NMOS transistor respectively, and a source of the third NMOS transistor being connected with a drain of the fourth NMOS transistor, a source of the fourth NMOS transistor and a source of the sixth NMOS transistor being both grounded, the drain of the third NMOS transistor outputting a bias voltage VB.sub.3 to the first-stage amplifier circuit, and the positive and negative terminals of the resistor R.sub.0 respectively outputting bias voltages VB.sub.4 and VB.sub.5 to the first-stage amplifier circuit.

2. The fully-differential two-stage operational amplifier circuit according to claim 1, wherein the first-stage amplifying circuit further comprises a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor and a tenth NMOS transistor, a source of the third PMOS transistor being connected with the external power supply VDD, a drain of the third PMOS transistor being connected with a source of the fourth PMOS transistor and a source of the fifth PMOS transistor respectively, a drain of the fourth PMOS transistor being connected to a source of the sixth PMOS transistor, a drain of the fifth PMOS transistor being connected with a source of the seventh PMOS transistor, a drain of the sixth PMOS transistor being connected with a drain of the seventh PMOS transistor, the drain of the seventh PMOS transistor being connected with a drain of the eighth NMOS transistor, the source of the seventh NMOS transistor being connected to a drain of the ninth NMOS transistor, a source of the eighth NMOS transistor being connected with a drain of the tenth NMOS transistor, and a source of the ninth NMOS transistor and a source of the tenth NMOS transistor being both grounded; and a gate of the fourth PMOS transistor and a gate of the fifth PMOS transistor being respectively connected with the differential input signals IN.sub.P and IN.sub.N, the drain of the second PMOS transistor outputting the common-mode feedback signal VB.sub.1 to a gate of the third PMOS transistor, and the drain of the third NMOS transistor outputting the bias voltage VB.sub.3 to a gate of the sixth PMOS transistor and a gate of the seventh PMOS transistor, the positive terminal of the resistor R.sub.0 outputting the bias voltage VB.sub.4 to a gate of the seventh NMOS transistor and a gate of the eighth NMOS transistor respectively, and the negative terminal of the resistor R.sub.0 outputting the bias voltage VB.sub.5 to a gate of the ninth NMOS transistor and a gate of the tenth NMOS transistor respectively.

3. The fully-differential two-stage operational amplifier circuit according to claim 2, wherein the second-stage amplifying circuit further comprises an eighth PMOS transistor, a ninth PMOS transistor, an eleventh NMOS transistor and a twelfth NMOS transistor, a source of the eighth PMOS transistor and a source of the ninth PMOS transistor being respectively connected with the external power supply VDD, a drain of the eighth PMOS transistor being connected with a drain of the eleventh NMOS transistor, and a drain of the ninth PMOS transistor being connected with a drain of the twelfth NMOS transistor, a source of the eleventh NMOS transistor and a source of the twelfth NMOS transistor being both grounded, the drain of the sixth PMOS transistor being connected with a gate of the eleventh NMOS transistor, and the drain of the seventh PMOS transistor being connected with a gate of the twelfth NMOS transistor; and the drain of the first PMOS transistor outputting the common-mode feedback signal VB.sub.2 to a gate of the eighth PMOS transistor and a gate of the ninth PMOS transistor respectively.

4. The fully-differential two-stage operational amplifier circuit according to claim 3, further comprising a frequency compensation circuit, the frequency compensation circuit comprising a first resistor, a second resistor, a first capacitor and a second capacitor, the first resistor and the first capacitor being connected in series, a terminal of the first resistor being connected with the drain of the eleventh NMOS transistor and a terminal of the first capacitor being connected with the drain of the sixth PMOS transistor; and the second resistor and the second capacitor being connected in series, a terminal of the second resistor being connected with the drain of the twelfth NMOS transistor and a terminal of the second capacitor being connected with the drain of the seventh PMOS transistor.

5. The fully-differential two-stage operational amplifier circuit according to claim 4, wherein the common-mode signal acquisition circuit further comprises a third resistor, a fourth resistor, a third capacitor and a fourth capacitor, the third resistor and the fourth resistor being connected in series between the differential output signals OUT.sub.P and OUT.sub.N; the third capacitor and the fourth capacitor being connected in series between the differential output signals OUT.sub.P and OUT.sub.N; the third resistor and the third capacitor being connected in parallel, the fourth resistor and the fourth capacitor being connected in parallel; and the operational amplifier output common-mode signal V.sub.CMO being output at a common connecting point of the third resistor, the fourth resistor, the third capacitor and the fourth capacitor.

6. The fully-differential two-stage operational amplifier circuit according to claim 1, wherein the first PMOS transistor and the second PMOS transistor are PMOS transistors of a same type, and the first NMOS transistor and the second NMOS transistor are NMOS transistors of a same type.

7. The fully-differential two-stage operational amplifier circuit according to claim 4, wherein the first resistor and the second resistor are of a same type, and the first capacitor and the second capacitor are of a same type.

8. The fully-differential two-stage operational amplifier circuit according to claim 5, wherein the third resistor and the fourth resistor are of a same type, and the third capacitor and the fourth capacitor are of a same type.

9. The fully-differential two-stage operational amplifier circuit according to claim 2, wherein the first PMOS transistor and the second PMOS transistor are PMOS transistors of a same type, and the first NMOS transistor and the second NMOS transistor are NMOS transistors of a same type.

10. The fully-differential two-stage operational amplifier circuit according to claim 3, wherein the first PMOS transistor and the second PMOS transistor are PMOS transistors of a same type, and the first NMOS transistor and the second NMOS transistor are NMOS transistors of a same type.

11. The fully-differential two-stage operational amplifier circuit according to claim 4, wherein the first PMOS transistor and the second PMOS transistor are PMOS transistors of a same type, and the first NMOS transistor and the second NMOS transistor are NMOS transistors of a same type.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic diagram of a main circuit of a two-stage operational amplifier with a telescopic structure in the prior art.

(2) FIG. 2 is a circuit schematic diagram of a traditional fully-differential two-stage operational amplifier with a telescopic structure.

(3) FIG. 3 is a schematic circuit diagram of a fully-differential two-stage operational amplifier according to an embodiment of the present disclosure.

(4) FIG. 4 is a schematic diagram of simulation of a common mode response frequency and a gain of a traditional fully-differential two-stage operational amplifier circuit with a telescopic structure.

(5) FIG. 5 is a schematic diagram of simulation of a common mode response frequency and a phase of a traditional fully-differential two-stage operational amplifier circuit with a telescopic structure.

(6) FIG. 6 is a schematic diagram of simulation of a common mode response frequency and a gain of a fully-differential two-stage operational amplifier circuit according to an embodiment of the present disclosure.

(7) FIG. 7 is a schematic diagram of simulation of a common mode response frequency and a phase of a fully-differential two-stage operational amplifier circuit according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

(8) In order to further understand contents of the present disclosure, the present disclosure will be described in detail with reference to drawings and examples.

(9) In description of this disclosure, it should be noted that unless otherwise specified and limited, terms “installing”, “coupling” and “connecting” should be understood broadly, for example, it can be “fixedly connecting”, “integrally connecting”, or “detachably connecting”; or it can be “mechanically connecting” or “electrically connecting”, or it can be “communicating within two elements”; or it can be “directly connecting” or “indirectly connecting through an intermediate medium”, and specific meanings of the above terms can be understood according to specific situations for ordinary skilled in the art.

(10) In combination with FIG. 3, a technical scheme of the present disclosure is a fully-differential two-stage operational amplifier circuit, which includes a first-stage amplifier circuit 1, a second-stage amplifier circuit 2, a common-mode signal acquisition circuit 5, a common-mode feedback circuit 3, a bias circuit 4 and a frequency compensation circuit 6.

(11) The first-stage amplifier circuit 1 has a telescopic structure and receives differential input signals IN.sub.P and IN.sub.N.

(12) The second-stage amplification circuit 2 has a common-source structure and outputs differential output signals OUT.sub.P and OUT.sub.N.

(13) The common-mode signal acquisition circuit 5 receives differential output signals OUT.sub.P and OUT.sub.N, and outputs an operational amplifier output common-mode signal V.sub.CMO.

(14) The common-mode feedback circuit 3 includes a first PMOS transistor MP.sub.1, a second PMOS transistor MP.sub.2, a first NMOS transistor MN.sub.1 and a second NMOS transistor MN.sub.2. The first PMOS transistor MP.sub.1 and the second PMOS transistor MP.sub.2 are PMOS transistors of a same type, and the first NMOS transistor MN.sub.1 and the second NMOS transistor MN.sub.2 are NMOS transistors of a same type. A source of the first PMOS transistor MP.sub.1 and a source of the second PMOS transistor MP.sub.2 are respectively connected with an external power supply VDD, and a gate of the first PMOS transistor MP.sub.1 is respectively connected with a drain of the first PMOS transistor MP.sub.1 and a drain of the first NMOS transistor MN.sub.1. A gate of the second PMOS transistor MP.sub.2 is connected to a drain of the second PMOS transistor MP.sub.2 and a drain of the second NMOS transistor MN.sub.2 respectively, a source of the first NMOS transistor MN.sub.1 is connected to a source of the second NMOS transistor MN.sub.2, a gate of the first NMOS transistor MN.sub.1 receives an external input reference signal V.sub.CM, a gate of the second NMOS transistor MN.sub.2 receives an operational amplifier output common-mode signal V.sub.CMO, and the drain of the second PMOS transistor MP.sub.2 and the drain of the first PMOS transistor MP.sub.1 respectively output common-mode feedback signals VB.sub.1 and VB.sub.2 to the first-stage amplification circuit 1 and the second-stage amplification circuit 2.

(15) The bias circuit includes a resistor R.sub.0, a third NMOS transistor MN.sub.3, a fourth NMOS transistor MN.sub.4, a fifth NMOS transistor MN.sub.5 and a sixth NMOS transistor MN.sub.6. A positive terminal of the resistor R.sub.0 receives a reference current i.sub.ref, and the positive terminal of the resistor R.sub.0 is connected with a gate of the third NMOS transistor MN.sub.3 and a gate of the fifth NMOS transistor MN.sub.5 respectively. A negative terminal of the resistor R.sub.0 is connected with a drain of the fifth NMOS transistor MN.sub.5, a gate of the sixth NMOS transistor MN.sub.6 and a gate of the fourth NMOS transistor MN.sub.4 respectively, a source of the fifth NMOS transistor MN.sub.5 is connected with a drain of the sixth NMOS transistor MN.sub.6, a drain of the third NMOS transistor MN.sub.3 is connected with the source of the first NMOS transistor MN.sub.1 and the source of the second NMOS transistor MN.sub.2 respectively, and a source of the third NMOS transistor MN.sub.3 is connected with a drain of the fourth NMOS transistor MN.sub.4, a source of the fourth NMOS transistor MN.sub.4 and a source of the sixth NMOS transistor MN.sub.6 are both grounded, the drain of the third NMOS transistor MN.sub.3 outputs a bias voltage VB.sub.3 to the first-stage amplifier circuit 1, and the positive and negative terminals of the resistor R.sub.0 respectively output bias voltages VB.sub.4 and VB.sub.5 to the first-stage amplifier circuit 1.

(16) The first-stage amplifying circuit 1 further includes a third PMOS transistor MP.sub.3, a fourth PMOS transistor MP.sub.4, a fifth PMOS transistor MP.sub.5, a sixth PMOS transistor MP.sub.6, a seventh PMOS transistor MP.sub.7, a seventh NMOS transistor MN.sub.7, an eighth NMOS transistor MN.sub.8, a ninth NMOS transistor MN.sub.9 and a tenth NMOS transistor MN.sub.10. A source of the third PMOS transistor MP.sub.3 is connected with the external power supply VDD, a drain of the third PMOS transistor MP.sub.3 is connected with a source of the fourth PMOS transistor MP.sub.4 and a source of the fifth PMOS transistor MP.sub.5 respectively, a drain of the fourth PMOS transistor MP.sub.4 is connected to a source of the sixth PMOS transistor MP.sub.6, a drain of the fifth PMOS transistor MP.sub.5 is connected with a source of the seventh PMOS transistor MP.sub.7, a drain of the sixth PMOS transistor MP.sub.6 is connected with a drain of the seventh PMOS transistor MN.sub.7, the drain of the seventh PMOS transistor MP.sub.7 is connected with a drain of the eighth NMOS transistor MN.sub.8, the source of the seventh NMOS transistor MN.sub.7 is connected to a drain of the ninth NMOS transistor MN.sub.9, a source of the eighth NMOS transistor MN.sub.8 is connected with a drain of the tenth NMOS transistor MN.sub.10, and a source of the ninth NMOS transistor MN.sub.9 and a source of the tenth NMOS transistor MN.sub.10 are both grounded.

(17) A gate of the fourth PMOS transistor MP.sub.4 and a gate of the fifth PMOS transistor MP.sub.5 are respectively connected with the differential input signals IN.sub.P and IN.sub.N, the drain of the second PMOS transistor MP.sub.2 outputs the common-mode feedback signal VB.sub.1 to a gate of the third PMOS transistor MP.sub.3, and the drain of the third NMOS transistor MN.sub.3 outputs the bias voltage VB.sub.3 to a gate of the sixth PMOS transistor MP.sub.6 and a gate of the seventh PMOS transistor MP.sub.7. The positive terminal of the resistor R.sub.0 outputs the bias voltage VB.sub.4 to a gate of the seventh NMOS transistor MN.sub.7 and a gate of the eighth NMOS transistor MN.sub.8 respectively, and the negative terminal of the resistor R.sub.0 outputs the bias voltage VB.sub.5 to a gate of the ninth NMOS transistor MN.sub.9 and a gate of the tenth NMOS transistor MN.sub.10 respectively.

(18) The second-stage amplifying circuit further includes an eighth PMOS transistor MP.sub.8, a ninth PMOS transistor MP.sub.9, an eleventh NMOS transistor MN.sub.11 and a twelfth NMOS transistor MN.sub.12. A source of the eighth PMOS transistor MP.sub.8 and a source of the ninth PMOS transistor MP.sub.9 are respectively connected with the external power supply VDD, a drain of the eighth PMOS transistor MP.sub.8 is connected with a drain of the eleventh NMOS transistor MN.sub.11, and a drain of the ninth PMOS transistor MP.sub.9 is connected with a drain of the twelfth NMOS transistor MN.sub.12, a source of the eleventh NMOS transistor MN.sub.11 and a source of the twelfth NMOS transistor MN 2 are both grounded, the drain of the sixth PMOS transistor MP.sub.6 is connected with a gate of the eleventh NMOS transistor MN.sub.11, and the drain of the seventh PMOS transistor MP.sub.7 is connected with a gate of the twelfth NMOS transistor MN.sub.12.

(19) The drain of the first PMOS transistor MP.sub.1 outputs the common-mode feedback signal VB.sub.2 to a gate of the eighth PMOS transistor MP.sub.8 and a gate of the ninth PMOS transistor MP.sub.9 respectively.

(20) The frequency compensation circuit 6 includes a first resistor R.sub.1P, a second resistor R.sub.1N, a first capacitor C.sub.1P and a second capacitor C.sub.1N. The first resistor R.sub.1P and the second resistor R.sub.1N are of a same type, and the first capacitor C.sub.1P and the second capacitor C.sub.1N are of a same type. The first resistor R.sub.1P and the first capacitor C.sub.1P are connected in series, a terminal of the first resistor R.sub.1P is connected with the drain of the eleventh NMOS transistor MN.sub.11 and a terminal of the first capacitor C.sub.1P is connected with the drain of the sixth PMOS transistor MP.sub.6; and the second resistor R.sub.1N and the second capacitor C.sub.1N are connected in series, a terminal of the second resistor R.sub.1N is connected with the drain of the twelfth NMOS transistor MN.sub.12 and a terminal of the second capacitor C.sub.1N is connected with the drain of the seventh PMOS transistor MP.sub.7.

(21) The common-mode signal acquisition circuit 5 further includes a third resistor R.sub.2P, a fourth resistor R.sub.2N, a third capacitor C.sub.2P and a fourth capacitor C.sub.2N. The third resistor R.sub.2P and the fourth resistor R.sub.2N are of a same type, and the third capacitor C.sub.2P and the fourth capacitor C.sub.2N are of a same type. The third resistor R.sub.2P and the fourth resistor R.sub.2N are connected in series between the differential output signals OUT.sub.P and OUT.sub.N; the third capacitor C.sub.2P and the forth capacitor C.sub.2N are connected in series between the differential output signals OUT.sub.P and OUT.sub.N; the third resistor R.sub.2P and the third capacitor C.sub.2P are connected in parallel, the fourth resistor R.sub.2N and the fourth capacitor C.sub.2N are connected in parallel; and the operational amplifier output common-mode signal V.sub.CMO is output at a common connecting point of the third resistor R.sub.2P, the fourth resistor R.sub.2N, the third capacitor C.sub.2P and the fourth capacitor C.sub.2N.

(22) This disclosure includes an operational amplifier control integrated circuit based on a telescopic two-stage operational amplifier. The first-stage amplifier circuit is of a telescopic cascode structure with a PMOS transistor differential input, which can provide a high gain. The second stage amplifier circuit is of a common-source structure, which can provide a largest output swing. The common-mode feedback circuit and the bias circuit only need 8 transistors and one resistor in total, in which the first NMOS transistor MN.sub.1 and the second NMOS transistor MN.sub.2 form a differential pair, respectively receiving the external input reference signal V.sub.CM and the operational amplifier output common-mode signal V.sub.CMO and amplifying a difference between them. The first PMOS transistor MP.sub.1 and the second PMOS transistor MP.sub.2 are diode-connected PMOS transistors, which form a load of the differential pair and generate the common-mode feedback signals VB.sub.1 and VB.sub.2 respectively. The common-mode feedback signals VB.sub.1 and VB.sub.2 both provide negative feedback to the output common-mode signal V.sub.CMO of the operational amplifier, and at the same time function to stabilize the output common-mode level. Because there are two negative feedback loops at the same time, a gain of a common-mode feedback loop can be increased. The source of the first NMOS transistor MN.sub.1 and the source of the second NMOS transistor MN.sub.2 are connected with the drain of the third NMOS transistor MN.sub.3 and provide a bias voltage VB.sub.3, the bias voltage VB.sub.3 is equal to the external input reference signal V.sub.CM minus a gate-source voltage of the first PMOS transistor MP.sub.1 or the second PMOS transistor MP.sub.2; and the gate of the third NMOS transistor MN.sub.3 and the gate of the fourth NMOS transistor MN.sub.4 are respectively connected to the gate of the seventh NMOS transistor MN.sub.7, the gate of the eighth NMOS transistor MN.sub.8, the gate of the ninth NMOS transistor MN.sub.9 and the gate of the tenth NMOS transistor MN.sub.10 to form a current source with a cascade structure, so as to provide a bias current for the differential pair composed of the first NMOS transistor MN.sub.1 and the second NMOS transistor MN.sub.2. The positive and negative terminals of the resistor R.sub.0 are respectively connected with the gate of the fifth NMOS transistor MN.sub.5 and the gate of the sixth NMOS transistor MN.sub.6. The bias circuit composed of the resistor R.sub.0, the fifth NMOS transistor MN.sub.5 and the sixth NMOS transistor MN.sub.6 provides bias voltages VB.sub.4 and VB.sub.5.

(23) A formula (1) for calculating a common mode feedback loop gain of the fully-differential two-stage operational amplifier circuit is as follows:
Gain_.sub.CMFB=(gm.sub.N1/gm.sub.P1)×{gm.sub.P8+gm.sub.N11×gm.sub.P3×[gm.sub.P4×ro.sub.P4×gm.sub.P6×ro.sub.P6×ro.sub.P3∥gm.sub.N7×ro.sub.N7×(ro.sub.N9/2)]}×(ro.sub.P8∥ro.sub.N11)  Equation (1).

(24) FIG. 4 and FIG. 5 are schematic diagrams of simulation of a common-mode response of the traditional fully-differential two-stage operational amplifier circuit with the telescopic structure in FIG. 2, and FIG. 6 and FIG. 7 are schematic diagrams of simulation of a common-mode response of the fully-differential two-stage operational amplifier circuit in FIG. 3 according to the embodiment of the present disclosure. By comparing FIGS. 4-7, the common-mode feedback loop of the circuit according to the present disclosure presents a higher loop gain and a better loop stability.

(25) In this disclosure, with a gain and stability of the common-mode feedback loop being ensured, the common-mode feedback circuit and the bias circuit only need one resistor and eight transistors, which simplifies a designed structure of the traditional fully-differential two-stage operational amplifier with the telescopic structure, reduces consumption of elements and hardware, reduces production cost and is beneficial to saving area of the integrated circuit.

(26) The present disclosure and embodiments thereof are described above in an illustrative manner, which is not restrictive; and what is shown in the drawings is only one of the embodiments of the present disclosure, and its actual structure is not limited thereto. Therefore, structures and embodiments similar to the technical scheme designed by those of ordinary skilled in the art inspired by this disclosure without creativity, without departing from the creative purpose of the present disclosure, are all within a protection scope of the present disclosure.