Pentacene organic field-effect transistor with n-type semiconductor interlayer and its application

Abstract

A method for enhancing the performance of pentacene organic field-effect transistor (OFET) using n-type semiconductor interlayer: an n-type semiconductor thin film was set between the insulating layer and the polymer electret in the OFET with the structure of gate-electrode/insulating layer/polymer/pentacene/source (drain) electrode. The thickness of n-type semiconductor layer is 1˜200 nm. The induced electrons at the interface of n-type semiconductor and polymer electret lead to the reduction of the height of the hole-barrier formed at the interface of polymer and pentacene, thus effectively reducing the programming/erasing (P/E) gate voltages of pentacene OFET, adjusting the height of hole barrier at the interface of polymer and pentacene to a reasonable scope by controlling the quantity of induced electrons in n-type semiconductor layer, thus improving the performance of pentacene OFET, such as the P/E speeds, P/E endurance and retention characteristics.

Claims

1. A method to prepare a pentacene organic field-effect transistor (OFET) memory, comprising providing a p-Si substrate covered with a 90-nm thermally-oxidized SiO.sub.2 layer and cleaning the substrate with acetone, ethanol and de-ionized water for 10 minutes successively, and then drying the substrate with a nitrogen gun; growing a polymer layer on the p-Si substrate by using a wet-coating method; depositing a layer of n-type semiconductor thin film on the PVN-covered SiO.sub.2/Si(100) substrate through either a wet-coating method or dry coating method; depositing a layer of pentacene through thermal vacuum evaporation; and depositing an electrode through thermal vacuum evaporation.

2. The method of claim 1, wherein the polymer is selected from polystyrene, poly(2-vinyl naphthalene) (PVN) and poly(α-methylstyrene) (PαMS).

3. The method of claim 1, wherein the polymer layer is a charge-trapping layer of PVN, having a thickness of 40 nm.

4. The method of claim 1, wherein the wet-coating method includes spin-coating method, sol-gel method, spray method, silk-screen printing method, ink-jet printing method, thermal evaporation method.

5. The method of claim 1, wherein a thickness of the polymer layer is 1-100 nm.

6. The method of claim 1, wherein the n-type semiconductor thin film includes n-type organic small-molecule semiconductor and n-type polymer semiconductor, including N,N′-Ditridecylperylene-3,4,9,10-tetracarboxylic diimide (PTCDI-C13), N,N′-Bis(3-pentyl) perylene-3,4,9,10-bis (dicarboximide) (EP-PDI); and 1,3,6,8(2H,7H)-Tetraone, 2,7-dicyclohexylbenzo[lmn][3,8]phenanthroline (NDI); having a thickness of 1-100 nm; in a crystalline thin film, or a semi-crystalline thin film, or an amorphous thin film.

7. The method of claim 1, wherein the n-type semiconductor thin film is an n-type inorganic semiconductor thin film including ZnSe, ZnS, ZnO, amorphous indium-gallium-zinc oxide (IGZO), an oxygen-deficient oxide film and an oxygen-deficient composite oxide film, including TiO.sub.2-x and ZrHfO.sub.2-x; with a thickness is 1-200 nm, in a crystalline thin film or a noncrystalline thin film.

8. The method of claim 1, wherein the n-type semiconductor thin film is a hybridized structure with two kinds of n-type semiconductor thin films having a total thickness of 1-100 nm, including an n-type inorganic semiconductor film prepared on a surface of a n-type organic small-molecule semiconductor film, or an n-type polymer semiconductor film prepared on the surface of a n-type organic small-molecule semiconductor film.

9. The method of claim 7, wherein the dry coat method includes film includes rf-magnetron sputtering, thermal evaporation and electron-beam evaporation.

10. The method of claim 8, wherein the thickness of n-type organic semiconductor film in the hybridized structure is 0.5-60 nm, the thickness of n-type organic semiconductor film is 0.5-60 nm, but the thickness of hybridized film is 1-100 nm.

11. The method of claim 1, wherein the electrode has a side-length of 300 μm and a thickness of 100 nm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows the schematic drawing of the structure of the organic field-effect transistor (OFET) based on the method for enhancing the performance of pentacene OFET. No. 1 layer is gate electrode, No. 2 layer is insulating layer, No. 3 layer is polymer dielectric thin film, No. 4 layer is n-type semiconductor thin film buffer layer, No. 5 layer is pentacene, and No. 6 layer is source (drain) electrode.

(2) FIG. 2 shows the transfer characteristics of pentacene OFETs with PTCDI-C13 buffer layer: the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(3) FIG. 3 shows the transfer characteristics of pentacene OFETs without PTCDI-C13 buffer layer: the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(4) FIG. 4 shows the endurance characteristics of pentacene OFETs with PTCDI-C13 buffer layer: the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(5) FIG. 5 shows the retention characteristics of pentacene OFETs with PTCDI-C13 buffer layer: the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(6) FIG. 6 shows the transfer characteristics of pentacene OFETs with PTCDI-C13 buffer layer: the charge-trapping dielectric is polystyrene (PS), the organic semiconductor is pentacene.

(7) FIG. 7 shows the transfer characteristics of pentacene OFETs without PTCDI-C13 buffer layer, the charge-trapping dielectric is polystyrene (PS), the organic semiconductor is pentacene.

(8) FIG. 8 shows the transfer characteristics of pentacene OFETs with ZnO buffer layer: the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(9) FIG. 9 shows the schematic drawing of the structure of the organic field-effect transistor (OFET) based on the method for enhancing the performance of pentacene OFET. No. 1 layer is gate electrode, No. 2 layer is insulating layer, No. 3 layer is n-type semiconductor interlayer, No. 4 layer is polymer dielectric thin film, No. 5 layer is pentacene, and No. 6 layer is source (drain) electrode.

(10) FIG. 10 shows the transfer characteristics of pentacene OFETs with ZnO interlayer: the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(11) FIG. 11 shows the transfer characteristics of pentacene OFETs without ZnO interlayer: the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(12) FIG. 12 shows the endurance characteristics of pentacene OFETs with ZnO interlayer: the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(13) FIG. 13 shows the retention characteristics of pentacene OFETs with ZnO interlayer: the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(14) FIG. 14 shows the transfer characteristics of pentacene OFETs with IGZO interlayer: The growth parameter of IGZO during the sputtering process was Ar:O.sub.2=15:1, and the growth time was 1 min, and the thickness was 10 nm, the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(15) FIG. 15 shows the retention characteristics of pentacene OFETs with IGZO interlayer: The growth parameter of IGZO during the sputtering process was Ar:O.sub.2=15:1, the growth time was 1 min, and the thickness was 10 nm, the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(16) FIG. 16 shows the transfer characteristics of pentacene OFETs with IGZO interlayer: The growth parameter of IGZO during the sputtering process was Ar:O.sub.2=15:1, the growth time was 2 min, and the thickness was 20 nm, the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(17) FIG. 17 shows the retention characteristics of pentacene OFETs with IGZO interlayer: The growth parameter of IGZO during the sputtering process was Ar:O.sub.2=15:1, the growth time was 2 min, and the thickness was 20 nm, the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(18) FIG. 18 shows the transfer characteristics of pentacene OFETs with IGZO interlayer: The growth parameter of IGZO during the sputtering process was Ar:O.sub.2=15:0.5, the growth time was 1 min, and the thickness was 10 nm, the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

(19) FIG. 19 shows the retention characteristics of pentacene OFETs with IGZO interlayer: The growth parameter of IGZO during the sputtering process was Ar:O.sub.2=15:0.5, the growth time was 1 min, and the thickness was 10 nm, the charge-trapping dielectric is poly (2-vinyl naphthalene) (PVN), the organic semiconductor is pentacene.

DETAILED EMBODIMENTS

Embodiment 1

(20) The structure of the traditional pentacene organic field-effect transistor (OFET) is gate-electrode/insulating layer/polymer/pentacene/source(drain)-electrode. In the present invention an n-type semiconductor thin film was set as a buffer layer between pentacene and polymer electret.

(21) The polymer thin film can be polystyrene (PS), or poly (2-vinyl naphthalene) (PVN), etc., but it's not limited to those. Which has a charge-trapping ability. The preparation methods of the polymer thin film include spin-coating method, sol-gel method, spray method, silk-screen printing method, ink-jet printing method, and other similar physical and chemical film preparation methods; the thickness of polymer film is 1-100 nm.

(22) The n-type semiconductor buffer layer can be an n-type inorganic semiconductor thin film, or an n-type organic semiconductor thin film.

(23) The preparation methods of n-type inorganic semiconductor thin film include thermal evaporation and electron beam evaporation; The thickness of n-type inorganic semiconductor thin film is 1-50 nm. The preparation methods of n-type organic semiconductor thin film include the solution method, spin-coating method, sol-gel method, spray method, silk-screen printing method, ink-jet printing method, thermal evaporation method, and other similar physical and chemical methods; Its thickness is 1-100 nm.

(24) N-type semiconductor thin film also can be a hybridized structure with two kinds of n-type semiconductor thin films. It can be an n-type inorganic semiconductor film prepared on the surface of n-type organic small molecule semiconductor film, or an n-type polymer semiconductor film prepared on the surface of n-type organic small molecule semiconductor film. The aim is to improve the morphology of n-type semiconductor buffer layer and make it flatter to improve the morphology of pentacene semiconductor thin film grown on it later. Specifically, the aim is to improve the density, flatness and grain size of pentacene thin films, and to improve the field-effect mobility of hole carriers in pentacene semiconductor thin films; The thickness of n-type small molecule semiconductor film in the hybridized structure thin film is 1-10 nm.

(25) The source (drain) electrode can be a metal, conductive nitride or conductive oxide material. The preparation methods of the source (drain) electrode include the physical deposition methods such as rf-magnetron sputtering and electron beam evaporation, and the chemical deposition methods such as atomic layer deposition method (ALD). The gate electrode of the bottom-gate type OFETs also can be a heavily doped n-type silicon with a high conductivity or a heavily doped p-type silicon with a high conductivity. The gate electrode of the bottom-gate type OFETs also can be a flexible substrate with a conductive coating.

(26) FIG. 1 shows the schematic drawing of the structure of the organic field-effect transistor (OFET) in embodiment 1. In FIG. 1, No. 1 layer is gate electrode using the heavy doped p-Si gate electrode with a crystal direction of <100>, which resistivity is less than 0.005 Ω.Math.cm; No. 2 layer is SiO.sub.2, which thickness is 90 nm; No. 3 layer is poly(2-vinyl naphthalene) (PVN), which thickness is 40 nm; No. 4 layer is N,N′-Ditridecylperylene-3,4,9,10-tetracarboxylic diimide (PTCDI-C13), which thickness is 20 nm; No. 5 layer is pentacene, which thickness is 40 nm; No. 6 layer is copper source (drain) electrode, which thickness is 100 nm.

(27) The specific preparation process steps are as followed:

(28) P—Si substrate covered with a 90-nm thermally-oxidized SiO.sub.2 layer was cleaned with acetone, ethanol and the de-ionized water for 10 minutes successively, and then dried with nitrogen gun for later use.

(29) A 40-nm PVN charge-trapping layer was grown on p-Si substrate by using spin-coating method.

(30) Then, PTCDI-C13 (20 nm) layer and pentacene (40 nm) layer were grown on the PVN-covered SiO.sub.2/Si(100) substrates by using the vacuum thermal evaporation method, respectively.

(31) The square copper (Cu) electrode with a side-length of 300 μm and a thickness of 100 nm was grown on the above-described sample by using the vacuum thermal evaporation method.

(32) The bottom heavily-doped p-Si was employed as the gate electrode.

(33) The electrical characteristics of the OFETs were measured with a semiconductor parameter analyzer (Keithley 4200). The output characteristic, transfer characteristic, programming/erasing (P/E) speeds, endurance characteristics and retention characteristics of the devices were analyzed by testing the relationship between the tested current and the applied voltage.

(34) The working principles of pentacene OFET memory device are as the following description. When a certain voltage is applied between two adjacent Cu electrodes of the memory device without applied gate voltage, namely the source electrode and the drain electrode, the current between the source electrode and the drain electrode is usually very small, and the current characteristic is similar to that of the insulator, and the device is in the OFF state. When a high enough negative voltage is applied to the gate electrode, a conducting channel will be generated in pentacene near the interface with the insulating layer, and then the current between the source electrode and the drain electrode will increase rapidly, making the device conducting. Thus, the device is in the ON state.

(35) FIG. 2 shows the transfer characteristics of pentacene OFETs with PTCDI-C13 buffer layer in embodiment 1, the voltage between the drain electrode and the source electrode is −5 V, the range of the sweeping voltage applied on the gate electrode is ±23 V˜±35 V. It can be seen that starting from the voltage of ±23 V, the memory window grows rapidly with the increase of the voltage. Here, the terminology ‘memory window’ (ΔV.sub.TH) is an important parameter for the OFET memory devices, which is defined as the difference between threshold voltages (V.sub.TH) in the programmed and the erased states. When the sweeping voltage is ±35 V, the memory window exceeds 25 V, and the difference between the OFF and the ON states is obvious.

(36) FIG. 3 shows the transfer characteristics of pentacene OFETs without PTCDI-C13 buffer layer in embodiment 1, the voltage between the drain electrode and the source electrode is −5 V, and the range of the sweeping voltage applied on the gate electrode is ±5 V˜±35 V. It can be seen that when the voltage is lower than 25 V, the curve shows almost no shift. Then, the memory window grows slowly with the increase of the gate voltage. When the sweeping voltage is ±35 V, the memory window is still less than 5V, and the difference between the OFF and the ON states is not obvious.

(37) According to the comparison as shown in FIG. 2 and FIG. 3, after introducing PTCDI-C13 buffer layer, the memory window of the device becomes significantly larger and the transfer characteristics are significantly improved.

(38) FIG. 4 shows the endurance characteristics of pentacene OFETs with PTCDI-C13 buffer layer in embodiment 1. The programming gate pulse is 35V/1 s, the erasing gate pulse: −23V/1 s, the applied voltage between the source electrode and the drain electrode is −5 V, and the reading voltage is 0 V. It can be seen that the initial switching current ratio of the device (I.sub.ON/I.sub.OFF) is 5.5×10.sup.4, and the switching current ratio of the device is still up to 2.6×10.sup.2 after 10,000 P/E switching cycles, indicating that the memory device has good endurance characteristics.

(39) FIG. 5 shows the retention characteristics of pentacene OFETs with PTCDI-C13 buffer layer in embodiment 1. The programming pulse is 35V/1 s, and the erasing pulse is −23V/1 s. The applied voltage between the source electrode and the drain electrode is −5V, and the reading voltage is 0 V. The switching current ratio of the device (I.sub.ON/I.sub.OFF) is still up to 3.2×10.sup.4 after 1×10.sup.4 s. By extending the curve to 10-year scale, the calculated current switch ratio would be 3.5×10.sup.2, indicating that the device has good retention characteristics.

Embodiment 2

(40) The difference between embodiment 1 and embodiment 2 is that the charge-trapping layer 3 is polystyrene (PS), which thickness is 40 nm, and the preparation method is still spin coating method.

(41) FIG. 6 shows the transfer characteristics of pentacene OFETs with PTCDI-C13 buffer layer in embodiment 2. The applied voltage between the drain electrode and the source electrode is −5 V, and the range of the sweeping voltage applied on the gate electrode is ±30 V˜±40 V. It can be seen that the memory window grows rapidly with the increase of the applied voltage. When the sweeping voltage is ±35 V, the memory window exceeds 17 V, and the difference between the ON and OFF states is obvious.

(42) FIG. 7 shows the transfer characteristics of pentacene OFETs without PTCDI-C13 buffer layer, the voltage between the drain electrode and the source electrode is −5V, and the range of the sweeping voltage applied on the gate electrode is ±5 V˜±35 V. It can be seen that when the voltage is lower than 25V, the curve barely moved. Then, the memory window grows slowly with the increase of the voltage. When the sweeping voltage is ±35V, the memory window still smaller than 5V, and the difference between the ON and the OFF states is not obvious.

(43) According to the comparison in FIG. 6 and FIG. 7, after introducing the PTCDI-C13 buffer layer, the memory window of the device becomes significantly larger and the transfer characteristics are significantly improved.

Embodiment 3

(44) The difference between embodiment 1 and embodiment 3 is that n-type semiconductor thin film 4 is zinc oxide (ZnO), which thickness is 10 nm, and the preparation method of it is rf-magnetron sputtering.

(45) FIG. 8 shows the transfer characteristics of pentacene OFETs with ZnO buffer layer. The applied voltage between the drain electrode and the source electrode is −5 V, and the range of the sweeping voltage applied on the gate electrode is ±5V˜±40 V. It can be seen that the memory window grows rapidly with the increase of the voltage. When the sweeping voltage is ±30V, the window is about 20V and the difference between the ON and the OFF states is obvious.

(46) According to the comparison in FIG. 8 and FIG. 3, after introducing ZnO buffer layer, the memory window of the device becomes significantly larger and the transfer characteristics are significantly improved.

Embodiment 4

(47) The structure of traditional pentacene organic field-effect transistor (OFET) is gate-electrode/insulating layer/polymer/pentacene/source(drain)-electrode. In the present invention an n-type semiconductor thin film was set between the insulating layer and the polymer electret.

(48) The n-type semiconductor layer can be an n-type inorganic semiconductor thin film, or an n-type organic semiconductor thin film.

(49) The preparation methods of n-type inorganic semiconductor thin film include rf-magnetron sputtering, thermal evaporation and electron beam evaporation; The thickness of n-type inorganic semiconductor thin film is 1-200 nm. The preparation methods of n-type organic semiconductor thin film include the solution method, spin-coating method, sol-gel method, spray method, silk-screen printing method, ink-jet printing method, thermal evaporation method, and other similar physical and chemical methods; Its thickness is 1-100 nm.

(50) N-type semiconductor thin film also can be a hybridized structure with two kinds of n-type semiconductor thin films. It can be an n-type inorganic semiconductor film prepared on the surface of n-type organic small molecule semiconductor film, or an n-type polymer semiconductor film prepared on the surface of n-type organic small molecule semiconductor film. The thickness of n-type organic semiconductor film in the hybridized structure is 0.5-60 nm, the thickness of n-type inorganic semiconductor film is 0.5-60 nm, but the thickness of hybridized film is 1-100 nm.

(51) The polymer thin film can be polystyrene (PS), or poly (2-vinyl naphthalene) (PVN), etc., which has a charge-trapping ability, but it's not limited to those. The preparation methods of the polymer thin film include spin-coating method, sol-gel method, spray method, silk-screen printing method, ink-jet printing method, and other similar physical and chemical film preparation methods; the thickness of polymer film is 1-100 nm.

(52) The gate electrode and the source (drain) electrode can be a metal, conductive nitride or conductive oxide material. The preparation methods of the source (drain) electrode include the physical deposition methods such as rf-magnetron sputtering and electron beam evaporation, and the chemical deposition methods such as atomic layer deposition method (ALD). The gate electrode of the bottom-gate OFETs also can be a heavily doped n-type silicon with a high conductivity or a heavily doped p-type silicon with a high conductivity. The gate electrode of the bottom-gate OFETs also can be a flexible substrate with a conductive coating.

(53) FIG. 9 shows the schematic drawing of the structure of the pentacene organic field-effect transistor (OFET) in embodiment 1. In FIG. 1, No. 1 layer is gate electrode using the heavy doped p-Si gate electrode with a crystal direction of <100>, which resistivity is less than 0.005 Ω.Math.cm; No. 2 layer is SiO.sub.2, which thickness is 90 nm; No. 3 layer is ZnO, which thickness is 20 nm; No. 4 layer is poly(2-vinyl naphthalene) (PVN), which thickness is 40 nm; No. 5 layer is pentacene, which thickness is 40 nm; No. 6 layer is copper source (drain) electrode, which thickness is 100 nm.

(54) The specific preparation process steps are as followed:

(55) P—Si substrate covered with a 90-nm thermally-oxidized SiO.sub.2 layer was cleaned with acetone, ethanol and the de-ionized water for 10 minutes successively, and then dried with nitrogen gun for later use.

(56) A 10-nm ZnO was grown on p-Si substrate by using magnetron sputtering method. Because O atoms are easy to be lost in the preparation process, ZnO thin film grown by magnetron sputtering method is actually an n-type semiconductor. The lack of O components leads to the n-type semiconductor characteristics of ZnO thin film.

(57) A 40-nm PVN charge-trapping layer was grown on the ZnO-covered SiO.sub.2/Si(100) substrates by using spin-coating method.

(58) Then, pentacene (40 nm) layer were grown on the PVN/ZnO/SiO.sub.2/Si(100) substrates by using the thermal evaporation method.

(59) The square copper (Cu) electrode with a scale of 300 μm and a thickness of 100 nm was grown on the above-described sample by using the thermal evaporation method.

(60) The bottom heavily-doped p-Si was employed as the gate electrode.

(61) The electrical characteristics of the OFETs were measured with a semiconductor parameter analyzer (Keithley 4200). The output characteristic, transfer characteristic, programming/erasing (P/E) speeds, endurance characteristics and retention characteristics of the devices were analyzed by testing the relationship between the drain-source current and the applied gate voltage.

(62) The working principles of pentacene OFET are as the following descriptions. When a certain voltage is applied between two adjacent Cu electrodes without applied gate voltage, namely the source electrode and the drain electrode, the current between the source electrode and the drain electrode is usually very low, and the current characteristic is similar to that of the insulator, and the OFET is in the ‘OFF’ state. When a high enough negative voltage is applied to the gate electrode, a conducting channel will be generated in pentacene layer near the interface with the insulating layer, and then the current between the source electrode and the drain electrode will increase rapidly, making the device conducting. Thus, the device is in the ‘ON’ state.

(63) FIG. 10 shows the transfer characteristics of pentacene OFETs with ZnO interlayer in embodiment 1, the voltage between the drain electrode and the source electrode is −5 V, the range of the sweeping voltage applied on the gate electrode is ±10 V˜±30 V. It can be seen that the memory window grows rapidly with the increase of the voltage. Here, the terminology ‘memory window’ (ΔV.sub.TH) is an important parameter for the OFET, which is defined as the shift between the threshold voltages (V.sub.TH) in the transfer characteristic curves in the programmed and the erased states. When the sweeping voltages are ±30 V, the memory window exceeds 30 V, and the difference between the ‘OFF’ and the ‘ON’ states is obvious.

(64) FIG. 3 shows the transfer characteristics of pentacene OFETs without ZnO interlayer in embodiment 1, the voltage between the drain electrode and the source electrode is −5 V, and the range of the sweeping voltage applied on the gate electrode is ±15 V˜±40 V. It can be seen that when the voltages are not over than ±25 V, the curve shows almost no shift. Then, the memory window grows slowly with the increase of the applied gate voltage. When the sweeping voltages are ±35 V, the memory window is still less than 10V, and the difference between the ‘OFF’ and the ‘ON’ states is not obvious.

(65) According to the comparison as shown in FIG. 10 and FIG. 11, after introducing ZnO interlayer, the memory window of the device becomes significantly larger and the transfer characteristics are significantly improved.

(66) FIG. 12 shows the endurance characteristics of pentacene OFETs with ZnO interlayer in embodiment 1. The programming gate pulse is 30V/1 s, the erasing gate pulse: −30V/1 s, the applied voltage between the source electrode and the drain electrode is −5 V, and the reading voltage is 0 V. It can be seen that the initial current ratio of the device (I.sub.ON/I.sub.OFF) is 1.0×10.sup.6, and the current ratio of I.sub.ON/I.sub.OFF for the device is still up to 1.0×10.sup.2 after 10,000 P/E switching cycles, indicating that the memory device has good endurance characteristics.

(67) FIG. 13 shows the retention characteristics of pentacene OFETs with ZnO interlayer in embodiment 1. The programming pulse is 30V/1 s, and the erasing pulse is −30V/1 s. The applied voltage between the source electrode and the drain electrode is −5V, and the reading voltage is 0 V. The current ratio of I.sub.ON/I.sub.OFF for the device is still up to 1.8×10.sup.4 after 1×10.sup.4 s, indicating that the device has good retention characteristics.

Embodiment 5

(68) The difference between embodiment 2 and embodiment 1 is that the n-type semiconductor layer 3 is IGZO, which thickness is 10 nm, and the preparation method is still magnetron sputtering method, and the growth parameter of IGZO during the sputtering process was Ar:O.sub.2=15:1, and the growth time was 1 min.

(69) FIG. 14 shows the transfer characteristics of pentacene OFETs with IGZO interlayer in embodiment 2. The applied voltage between the drain electrode and the source electrode is −5 V, and the range of the sweeping voltage applied on the gate electrode is ±15 V˜±35 V. It can be seen that the memory window grows rapidly with the increase of the voltage. When the sweeping voltages are ±35 V, the memory window exceeds 30 V, and the difference between the ‘OFF’ and the ‘ON’ states is obvious.

(70) According to the comparison as shown in FIG. 14 and FIG. 11, after introducing IGZO interlayer, the memory window of the device becomes significantly larger and the transfer characteristics are significantly improved.

(71) FIG. 15 shows the retention characteristics of pentacene OFETs with IGZO interlayer in embodiment 2. The programming pulse is 35V/1 s, and the erasing pulse is −25V/1 s. The applied voltage between the source electrode and the drain electrode is −5V, and the reading voltage is 0 V. The current ratio of I.sub.ON/I.sub.OFF for the device is still up to 3.8×10.sup.1 after 1×10.sup.4 s, indicating that the device has good retention characteristics.

Embodiment 6

(72) The difference between embodiment 3 and embodiment 1 is that the n-type semiconductor layer 3 is IGZO, which thickness is 20 nm, and the preparation method is still magnetron sputtering method, and the growth parameter of IGZO during the sputtering process was Ar:O.sub.2=15:1, the growth time was 2 min. The other growth parameters of IGZO are the same as those in embodiment 2, so the carrier concentration is the same as that in embodiment 2, and the increase of the thickness leads to an increase in the quantity of carriers in embodiment 3 as compared with that in embodiment 2.

(73) FIG. 16 shows the transfer characteristics of pentacene OFETs with IGZO interlayer in embodiment 3, the voltage between the drain electrode and the source electrode is −5 V, the range of the sweeping voltage applied on the gate electrode is ±15 V˜±35 V. It can be seen that the memory window grows rapidly with the increase of the voltage. When the sweeping voltages are ±35 V, the memory window exceeds 40 V, and the difference between the ‘OFF’ and the ‘ON’ states is obvious.

(74) According to the comparison as shown in FIG. 16 and FIG. 14, the memory window of the device in embodiment 3 is larger than that in embodiment 2, due to the more n-type carriers in the IGZO interlayer layer. The more negative charges gathering at IGZO/PVN interface, and the larger drops in the height of the barrier at the interface of pentacene/PVN. Thus, the performance of the OFET is more improved.

(75) FIG. 17 shows the retention characteristics of pentacene OFETs with IGZO interlayer in embodiment 3. The programming pulse is 35V/1 s, and the erasing pulse is −25V/1 s. The applied voltage between the source electrode and the drain electrode is −5V, and the reading voltage is 0 V. The current ratio of I.sub.ON/I.sub.OFF for the device is less than 10 after 2000 s, indicating that the device has bad retention characteristics.

(76) According to the comparison as shown in FIG. 17 and FIG. 15, the retention characteristics of the device in embodiment 3 is worse than that in embodiment 2 due to the more n-type carriers in the IGZO interlayer layer. The more negative charges gathering at the interface of IGZO/PVN, and the larger drops in the height of the barrier at the interface of pentacene/PVN. Thus, more holes trapped by PVN film may return spontaneously to pentacene.

(77) Based on above knowledge, by keeping the n-type carrier concentration in IGZO layer a constant, the thicker IGZO intercalating layer, the larger quantity of n-type carriers gathering at the interface of IGZO/polymer. Thus, the larger memory window for the OFET is obtained, while the retention characteristics of the device is worse. So, an appropriate thickness of n-semiconductor film should be carefully determined to get a larger memory window and better retention characteristics at the same time.

Embodiment 4

(78) The difference between embodiment 4 and embodiment 1 is that the n-type semiconductor layer 3 is IGZO, which thickness is 10 nm, and the preparation method is still magnetron sputtering method, and the growth parameter of IGZO was Ar:O.sub.2=15:0.5, the growth time was 1 min. The other growth parameters of IGZO are the same as those in embodiment 2, so the thickness is the same as that in embodiment 2. Due to the lower partial pressure of oxygen used in embodiment 4, more oxygen vacancies occur in the IGZO film, resulting in a higher carrier concentration, thus leading to an increase in the quantity of n-carriers in embodiment 4 as compared with that in embodiment 2.

(79) FIG. 18 shows the transfer characteristics of pentacene OFETs with IGZO interlayer in embodiment 4, the voltage between the drain electrode and the source electrode is −5 V, the range of the sweeping voltage applied on the gate electrode is ±15 V˜±35 V. It can be seen that the memory window grows rapidly with the increase of the voltage. When the sweeping voltages are ±35 V, the memory window exceeds 35 V, and the difference between the ‘OFF’ and the ‘ON’ states is obvious.

(80) According to the comparison as shown in FIG. 18 and FIG. 14, the memory window of the device in embodiment 4 is larger than that in embodiment 2 due to the more n-type carriers in the IGZO interlayer layer. The more negative charges gathering at the interface of IGZO/PVN, and the larger drops in the height of the barrier at the interface of pentacene/PVN. The performance of the OFET is more improved.

(81) FIG. 19 shows the retention characteristics of pentacene OFETs with IGZO interlayer in embodiment 4. The programming pulse is 35V/1 s, and the erasing pulse is −25V/1 s. The applied voltage between the source electrode and the drain electrode is −5V, and the reading voltage is 0 V. The current ratio of I.sub.ON/I.sub.OFF for the OFET is less than 10 after 2000 s, indicating that the device has bad retention characteristics.

(82) According to the comparison as shown in FIG. 19 and FIG. 15, the retention characteristics of the device in embodiment 4 is worse than that in embodiment 2 due to the more n-type carriers in IGZO interlayer layer. The more negative charges gathering at the interface of IGZO/PVN, and the larger drops in the height of the barrier at the interface of pentacene/PVN, thus more holes trapped by PVN likely spontaneously return to pentacene.

(83) Based on above knowledge, by keeping the thickness of IGZO layer a constant, the higher n-type carrier concentration of IGZO layer, the more n-type carriers gathering at the interface. Thus, the larger memory window for the device, while the retention characteristics of the device is worse. So, the appropriate carrier concentration should be carefully determined to get a larger memory window and better retention characteristics at the same time.

(84) It should be understood that the above specific implementation modes of the present invention are only used to exemplify or explain the principles of the invention, and do not constitute a limitation to the invention. Therefore, without deviating from the spirit and scope of the invention, any modification, equivalent replacement, improvement, etc. shall be included in the scope of protection of the invention. In addition, the claims attached to the invention are intended to cover all examples of changes and modifications that fall within the scope and boundaries of the attached claims, or in an equivalent form of such scope and boundaries.