Input Circuit for a Dynamic Comparator

Abstract

The present disclosure relates to an input circuit comprising positive and negative branches, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that the source terminal of the transistor in each of the positive branch and the negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch.

Claims

1. Input circuit for a dynamic comparator comprising a positive and a negative branch, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that a source terminal of the transistor in each of the positive and negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch, the first reset voltage and the second reset voltage being independent of each other.

2. The input circuit for a dynamic comparator as in claim 1, wherein the first reset voltage and the second reset voltage are provided by an external voltage.

3. The input circuit for a dynamic comparator as in claim 1, wherein the first reset voltage and the second reset voltage are provided via a resistive network.

4. The input circuit for a dynamic comparator as in claim 1, wherein the first reset voltage and the second reset voltage are provided via a capacitive network.

5. The input circuit for a dynamic comparator as in claim 1, wherein the first capacitor and the second capacitor are implemented as a switchable capacitive network arranged to be precharged to a fixed voltage and switched to generate the first reset voltage and the second reset voltage.

6. The input circuit for a dynamic comparator as in claim 1, wherein the first reset voltage and the second reset voltage are provided via amplifiers with fixed or tuneable gain values.

7. The input circuit for a dynamic comparator as in claim 1, comprising transistors arranged for acting as current sources to generate the first reset voltage and the second reset voltage.

8. The input circuit for a dynamic comparator as in claim 1, comprising a latch circuit arranged for receiving a first signal output from the positive branch and a second signal output from the negative branch.

9. The input circuit for a dynamic comparator as in claim 8, wherein the latch circuit is arranged for being triggered when a voltage difference between the first signal output and the second signal output reaches a given threshold level.

10. The input circuit for a dynamic comparator as in claim 1, wherein the transistors in the branches are PMOS transistors.

11. The input circuit for a dynamic comparator as in claim 1, wherein the transistors in the branches are NMOS transistors.

12. A comparator comprising an input circuit, the input circuit comprising a positive and a negative branch, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that a source terminal of the transistor in each of the positive and negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch, the first reset voltage and the second reset voltage being independent of each other.

13. The comparator as in claim 12, wherein the first reset voltage and the second reset voltage are provided by an external voltage.

14. The comparator as in claim 12, wherein the first reset voltage and the second reset voltage are provided via a resistive network.

15. The comparator as in claim 12, wherein the first reset voltage and the second reset voltage are provided via a capacitive network.

16. The comparator as in claim 12, wherein the first capacitor and the second capacitor are implemented as a switchable capacitive network arranged to be precharged to a fixed voltage and switched to generate the first reset voltage and the second reset voltage.

17. The comparator as in claim 12, wherein the first reset voltage and the second reset voltage are provided via amplifiers with fixed or tuneable gain values.

18. An analog-to-digital converter comprising: a comparator including an input circuit for a dynamic comparator comprising a positive and a negative branch, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that a source terminal of the transistor in each of the positive branch and the negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch, the first reset voltage and the second reset voltage being independent of each other.

19. The analog-to-digital converter as in claim 18, wherein the first reset voltage and the second reset voltage are provided by an external voltage.

20. The analog-to-digital converter as in claim 18, wherein the first reset voltage and the second reset voltage are provided via a resistive network.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0021] The present disclosure will now be described further, by way of example, with reference to the accompanying drawings, wherein like reference numerals refer to like elements in the various figures.

[0022] FIG. 1 illustrates a basic multi-bit quantizer architecture with external references for the comparators.

[0023] FIG. 2 illustrates a conventional input stage of a dynamic comparator.

[0024] FIG. 3 illustrates an implementation of a subtracting threshold voltage from the input voltage in front of the comparator.

[0025] FIG. 4 illustrates a conventional solution wherein an extra input pair is used to subtract the threshold voltage.

[0026] FIG. 5 illustrates an embodiment of an input stage for a dynamic comparator according to the present disclosure using external voltages V.sub.hp and V.sub.hn, according to an example embodiment.

[0027] FIG. 6 illustrates an example of wide range of threshold voltages of a dynamic comparator achieved using the proposed input stage circuit, according to an example embodiment.

[0028] FIG. 7 illustrates an implementation of a dynamic comparator comprising the proposed input stage using a charge-sharing DAC to internally generate the reset voltages V.sub.hp and V.sub.hn on the top plates of the capacitors C.sub.sp and C.sub.sn, according to an example embodiment.

[0029] FIG. 8 illustrates an implementation of a dynamic comparator comprising the proposed input stage using a charge-redistribution DAC to internally generate the reset voltages V.sub.hp and V.sub.hn on the top plates of the capacitors C.sub.sp and C.sub.sn, according to an example embodiment.

[0030] FIG. 9 illustrates an implementation of a dynamic comparator comprising the proposed input stage using a resistive DAC to internally generate the reset voltages V.sub.hp and V.sub.hn and provide them to the top plates of the capacitors C.sub.sp and C.sub.sn, according to an example embodiment.

[0031] FIG. 10 illustrates an implementation of a dynamic comparator comprising the proposed input stage using a current DAC to internally generate the reset voltages V.sub.hp and V.sub.hn on the top plates of the capacitors C.sub.sp and C.sub.sn, according to an example embodiment.

[0032] FIG. 11 illustrates an implementation of a dynamic comparator comprising the proposed input stage using a programmable amplifier to internally generate the reset voltages V.sub.hp and V.sub.hn and provide them to the top plates of the capacitors C.sub.sp and C.sub.sn, according to an example embodiment.

[0033] FIG. 12 illustrates an implementation containing a dynamic comparator and mapping circuitry used to tune the threshold of the comparator, according to an example embodiment.

[0034] FIG. 13 illustrates an implementation of a SAR ADC containing a dynamic comparator where the threshold voltages are changed during the conversion, according to an example embodiment.

[0035] FIG. 14 illustrates an ADC implementation containing multiple dynamic comparators implementing an asynchronous search algorithm, according to an example embodiment.

DETAILED DESCRIPTION

[0036] The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto but only by the claims.

[0037] Furthermore, the terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the present disclosure described herein are capable of operation in other sequences than described or illustrated herein.

[0038] It is to be noticed that the term comprising, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression a device comprising means A and B should not be limited to devices consisting only of components A and B. It means that with respect to the present disclosure, the only relevant components of the device are A and B.

[0039] Reference throughout this specification to one embodiment or an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases in one embodiment or in an embodiment in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

[0040] Similarly it should be appreciated that in the description of exemplary embodiments of the present disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of present disclosure, however, is not to be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.

[0041] Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the present disclosure, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0042] Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the present disclosure, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0043] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0044] The present disclosure proposes an input stage for a dynamic comparator with a simple architecture allowing the use of a single comparator for a wide range of threshold voltages. Further properties of the disclosed circuit comprise: [0045] small comparison time between sampling moment and a valid comparator result for high-speed applications; [0046] low power consumption; [0047] low input capacitance; and [0048] operation over a wide range of common-mode input values.

[0049] The proposed circuit is explained assuming a PMOS input pair, but it can also be applied to comparators with NMOS input pair. A scheme illustrating the general idea behind the proposed comparator is given in FIG. 5. Compared to the conventional solution of FIG. 2, the source node of the differential input pair is split in two nodes S.sub.ip and S.sub.in and two capacitors C.sub.Sp and C.sub.Sn are added to these nodes. The top plates are connected to the S.sub.ip and S.sub.in nodes, while the bottom plates are connected to fixed voltages V.sub.2p and V.sub.2n, respectively. Note that the proposed circuit can also be realized with the top and bottom plates swapped. C.sub.Sp and C.sub.Sn represent the total capacitances on the nodes S.sub.ip and S.sub.in, respectively, including all parasitic capacitance on these nodes. In the reset mode the top plate voltages of C.sub.sp and C.sub.sn are reset to independent voltages V.sub.hp and V.sub.hn depending on the comparator threshold voltage to realize as well as on the common-mode input level of the comparator. Also in the reset mode, the nodes D.sub.ip and D.sub.in are reset to a fixed voltage V.sub.1. During the comparison phase, the switches SW.sub.2p, SW.sub.2n are closed and the voltage on the nodes D.sub.ip and D.sub.in increases and builds up a difference until the threshold of the latch is achieved and a decision is made.

[0050] FIG. 5 shows an embodiment where the reset voltages V.sub.hp and V.sub.hn are provided via switches SW.sub.3p, SW.sub.3n. While the source nodes S.sub.ip and S.sub.in are reset to a high voltage (V.sub.hp, V.sub.hn), the drain nodes D.sub.ip and D.sub.in (with some capacitance C.sub.D comprising the parasitic capacitance and, optionally, an extra capacitor, for example, to lower the noise) are reset to a fixed low voltage V.sub.1, usually the electrical ground and in general different from reset voltages V.sub.hp and V.sub.hn. Although the capacitors C.sub.Dp and C.sub.Dn are usually the same in FIG. 5 and the nodes D.sub.ip and D.sub.in are reset to the same voltage V.sub.1, different capacitors and/or voltages (e.g. V.sub.1p, V.sub.1n) might be used, for example to compensate for mismatch errors. During the comparison phase the switches SW.sub.2p and SW.sub.2n are closed and the voltages on the nodes D.sub.ip and D.sub.in increase at different rates depending on the input voltage and the high voltages V.sub.hp, V.sub.hn. Different implementations may choose to open or close the reset switches SW.sub.3p, SW.sub.3n during this comparison phase. Similar to a conventional dynamic comparator, the latch circuit is triggered when the voltage difference on the nodes D.sub.ip and D.sub.in is large enough to generate the result of the comparison. In one implementation as in FIG. 5 extra switches SW.sub.7p and SW.sub.7n are added to the source nodes of the input transistors Tl_p, Tl_n to connect them to a fixed voltage (for example, the electrical ground) to put these nodes to a fixed voltage, when the switches SW.sub.2p and SW.sub.2n are open to realize a fixed input capacitance of the comparator while in reset phase.

[0051] The main difference with the conventional input pair of FIG. 2 is the source-gate voltage of the input pair when the input voltage is around the threshold voltage. If V.sub.th denotes the comparator threshold voltage and V.sub.cm the common-mode input voltage, the input voltages on the positive (P) and negative (N) side are V.sub.in.sub._.sub.p=V.sub.cmV.sub.th/2 and V.sub.in.sub._.sub.n=V.sub.cm+V.sub.th/2. In a conventional input structure as in FIG. 2, the source of both PMOS transistors is the same, resulting in one transistor having a large source-gate voltage while the other has a small source-gate voltage. In this input structure the N side would have a source-gate voltage of (V.sub.DDV.sub.sd)(V.sub.cm+V.sub.th/2) with V.sub.sd the required voltage over the top switch (or current source). To avoid turning off one side of the differential pair to obtain accurate comparison around the threshold voltage, this source-gate voltage should be larger than the absolute value of the threshold voltage V.sub.T of the transistor. With a common-mode voltage halfway the supply voltage, this poses an upper limit to the threshold voltage of V.sub.DD2V.sub.sd2V.sub.T. For example, for a V.sub.DD=800 mV and aggressive values for V.sub.ds=50 mV and V.sub.T=200 mV, this result in a maximum comparator threshold voltage of 300 mV.

[0052] In the proposed architecture, however, the source voltage of each input transistor moves along with the target threshold voltage ensuring both transistors have the same overdrive voltage around the threshold point. As a result, a much wider range of threshold voltages can be realized.

[0053] FIG. 6 shows simulation results of an implementation of the proposed technique in a 16 nm technology with 800 mV supply voltage. The threshold voltage ranges from almost 600 mV to +600 mV. Due to the charge-sharing between the respective capacitors C.sub.Sp, C.sub.Sn and C.sub.Dp, C.sub.Dn the voltages at the source nodes drop during the comparison phase and as a result the threshold voltage of the comparator is somewhat larger than the voltage difference V.sub.hpV.sub.hn to which C.sub.Sp and C.sub.Sn are reset.

[0054] Another disadvantage of the conventional implementation is that the input common-mode level is limited in the input pair to avoid turning off the transistors of the input pair which would make the comparator very slow. For example, a PMOS input pair with the same values for V.sub.sd and V.sub.T as listed above operates for a maximum input common-value of V.sub.DDV.sub.sdV.sub.TV.sub.th/2 which becomes 550 mV when no threshold voltage V.sub.th is programmed into the comparator. For higher input common-mode values, an NMOS input pair should be used. The input circuit according to this disclosure, however, overcomes this disadvantage as it allows continued use of a PMOS input pair for higher input values by putting the source of the input transistors also higher, which prevents turning them off.

[0055] In the embodiment of FIG. 5, the voltages V.sub.hp and V.sub.hn are available as external voltages. Fixed capacitors C.sub.sp and C.sub.sn are used with a bottom plate connected to yet other external voltages V.sub.2p, V.sub.2n, for example the electrical ground. A practical implementation uses some buffer to provide the voltages V.sub.hp and V.sub.hn to one or more comparators. The time available to precharge the capacitors C.sub.Sp and C.sub.Sn is usually relaxed since it corresponds to the reset time of the comparator, which is at least equal to the tracking time of the sampler in a typical flash ADC or pipelined ADC. Consequently, the bandwidth of the external circuit (e.g. a buffer) used to provide the voltages V.sub.hp and V.sub.hn can be small, and small switches SW.sub.3p, SW.sub.3p can be used. As a result, only a small amount of power is required in the external circuits and to toggle the switches.

[0056] In other embodiments the voltages V.sub.hp and V.sub.hn are internally generated. FIG. 7 shows an example of a capacitor network that dynamically generates these voltages by charge-sharing between a fixed capacitor C.sub.Sp, C.sub.Sn with the bottom plate connected to the electrical ground and with the top plate connected to a tuneable capacitor C.sub.Bp, C.sub.Bn. This tuneable capacitor is usually built as an array of switchable capacitors. A digital code is used to select the number of capacitors and, hence, the size of C.sub.Bp, C.sub.Bn. The reset phase .sub.1 is split in two parts wherein during the first reset phase (.sub.1a) the capacitors C.sub.Sp and C.sub.Sn are reset to the supply voltage V.sub.DD via switches SW.sub.4p, SW.sub.4n and the capacitors C.sub.B are reset to the electrical ground via switches SW.sub.5p, SW.sub.5h. Then, during the second reset phase (.sub.1b), the top plates of C.sub.Sp and C.sub.Sn are connected to the capacitors C.sub.Bp, C.sub.Bn via switches SW.sub.6p, SW.sub.6n to generate the voltages V.sub.hp, V.sub.hn on the top plates of the capacitors C.sub.Sp and C.sub.Sn. As a result, the reset voltages V.sub.hp and V.sub.hn are now different from the initial reset voltages V.sub.DD and electrical ground. Instead of the supply voltage V.sub.DD, any fixed voltage can be used, be it lower or higher than V.sub.DD. For example, any conventional charge pump can be used to generate a voltage higher than V.sub.DD.

[0057] In another implementation, the capacitors C.sub.Bp and C.sub.Bn are first precharged to fixed voltages and then connected either via the top or the bottom plate to the capacitors C.sub.Sp, C.sub.Sn, respectively, with the other plate to a fixed voltage (e.g. the electrical ground) to generate voltages V.sub.hp and V.sub.hn, similar to a charge-sharing DAC. In a fully differential implementation, only one tuneable capacitor C.sub.B is used which is also first precharged to a fixed voltage and then via the top and bottom plates connected to S.sub.ip, S.sub.in or S.sub.in, S.sub.ip to generate V.sub.hp and V.sub.hn.

[0058] Another embodiment is shown in FIG. 8. Here, the fixed capacitors C.sub.sp (41.sub.p) and C.sub.Sn (41.sub.n) are both split into a plurality of capacitor units C.sub.s1, C.sub.s2 . . . . The bottom plates of these C.sub.sp and C.sub.Sn can be switched between external voltages V.sub.2a, V.sub.2b. During the first reset phase (.sub.1a), the top plates of the respective capacitors C.sub.sp, C.sub.Sn are reset to a fixed external voltage V.sub.3 (e.g., the supply voltage or the common-mode level) while the bottom plates of the units are connected to either V.sub.2a or V.sub.2b. In the second reset phase (.sub.1b) the bottom plates are switched to generate the reset voltages V.sub.hp, V.sub.hn at the top plates (similarly to FIG. 5, but for simplicity not shown here). The voltages V.sub.hp, V.sub.hn are in general different from the fixed external voltage V.sub.3. In one implementation the bottom plates are switched to a higher voltage to generate the V.sub.hp, V.sub.hn voltages higher than V.sub.DD. Another implementation adds a fixed series capacitor between the common top plate of the capacitors and the source nodes S.sub.ip, S.sub.in to realize effective low values of C.sub.sp and C.sub.Sn without the need for physically small capacitors, which are very impractical. Smaller capacitors require less energy to be recharged, which may be desirable in low-power applications. Also, when C.sub.sp and C.sub.sn are made of units (as in FIG. 8), small capacitors may be desirable to realize a high tuning range resolution without getting a large sum, which would increase the power.

[0059] In yet another embodiment shown in FIG. 9, the capacitors C.sub.sp, C.sub.Sn are reset via switches SW.sub.3p, SW.sub.3n to nodes of which the voltages (V.sub.hp, V.sub.hn) are determined by the ratios of tuneable resistors 43, 44. These resistors can be made tuneable by putting resistor units in parallel or in series. In another implementation a fixed resistor ladder may be used, which generates different reference voltages. Via a network of switches the appropriate reference voltage can then be chosen to be connected to the respective nodes S.sub.ip, S.sub.in. By adding tuneable resistors on top and/or bottom of the fixed resistor ladder, an attenuation factor can be applied to all reference voltages, for example, to match an attenuation of the input signal provided to the comparator. In yet another implementation, an R-2R DAC comprising a network of parallel and series resistors, is used to generate the reference voltages which are connected to respective nodes S.sub.ip, S.sub.in via a switch matrix. Since the reset time is usually relaxed, large resistors can be used to limit the static power consumption. In one implementation, switches can be added in the resistive network to turn it completely off during the comparison phase and only activate the resistive network during the reset phase when the voltages V.sub.hp and V.sub.hn are to be generated.

[0060] The embodiment of FIG. 10 shows the voltages V.sub.hp and V.sub.hn being generated using current sources which are connected during a fixed time .sub.1b to the top plates of capacitors C.sub.sp and C.sub.Sn. During .sub.1a these capacitors are first reset to a fixed voltage V.sub.0 (like the supply voltage, the electrical ground or the common-mode level, which in general is different from V.sub.hp and V.sub.hn). During the phase .sub.1b the current sources are putting a charge proportional to the current value and the time .sub.1b onto the capacitors C.sub.sp, C.sub.Sn, which increases or decreases the voltages V.sub.hp, V.sub.hn accordingly. Hence, different values are readily generated by using programmable current sources, or by varying the reset time used to generate the voltages V.sub.hp and V.sub.hn.

[0061] Amplifiers or buffers can also be used to provide the voltages V.sub.hp and V.sub.hn. The embodiment of FIG. 11 shows two amplifiers with a tuneable gain A.sub.p, A.sub.n, which amplify a fixed reference signal V.sub.ref to the different voltages for the positive and negative branches. In one implementation a closed-loop amplifier containing an opamp, operational transconductance amplifier (OTA), switched opamp, ring amplifier or comparator with a resistive or capacitive feedback network, is used to generate different voltages by varying one or more resistors or capacitors. In another implementation an open-loop dynamic amplifier is used with tuneable amplification time to generate the different voltages.

[0062] In an embodiment, the circuit according to the present disclosure (as implemented in any of the embodiments shown in FIG. 5 and FIGS. 7 to 11) is used for a coarse tuning of the threshold voltage while a fine tuning is realized conventionally, for example, with tuneable capacitors C.sub.Dp and C.sub.Dn, tuneable current sources at the nodes D.sub.ip and D.sub.in or tuneable bulk or substrate voltages for the input transistors.

[0063] In one implementation, the input stage contains a mapping circuit, such as a combinatorial logic or a memory block like a look-up table which maps an input M-bit code B<M1:0> onto two digital N-bit codes B.sub.p<N1:0> and B.sub.n<N1:0> which sets the threshold voltage according to any one of the embodiments mentioned above. FIG. 12 illustrates the use of such mapping circuit 50 in the embodiment of FIG. 5. This configuration with a mapping circuit allows changing the threshold voltage or the common-mode input level during a data conversion algorithm. For example, as shown in FIG. 13, a SAR logic 60 performing a SAR algorithm can be employed where the comparator threshold voltages are adapted in each step rather than the input voltage of the comparator. Another implementation, illustrated in FIG. 14, uses multiple comparators with common input pins, which are subsequently activated, and whereby the threshold voltage of each comparator is set according to the results of the previous comparators. For example, the search logic in FIG. 14 implements an asynchronous binary search algorithm.

[0064] In yet another implementation, the outputs of two input stages are combined, for example via resistors, to create interpolated output values which are used to trigger more than two latches. This architecture allows realizing comparisons with interpolated threshold voltages without the need for extra input stages which would increase the power and total input capacitance.

[0065] The proposed solution ensures both input transistors see the same source-gate voltage around the threshold of the comparator without turning off one side when a large threshold voltage is required. Also, it allows operation with a wide range of input common-mode levels. For example, PMOS input transistors can be used for a high input level by putting both V.sub.hp and V.sub.hn at a higher level ensuring the gate-source voltage is large enough for correct operation.

[0066] There is no need for a network in front of the comparator to subtract the threshold voltage from the input before comparing which otherwise increase the comparison time, the power and the total input capacitance and introduces non-linear attenuation of the input signal.

[0067] The source capacitors C.sub.Sp, C.sub.Sn are precharged to V.sub.hp, V.sub.hn during the reset phase of the comparator, which is not in the critical timing path of typical flash and pipelined ADCs. As a result, there is no speed penalty.

[0068] The basic efficiency regarding energy, input capacitance, timing and noise is the same as for the conventional dynamic comparator with the extra functionality of a high threshold available.

[0069] To program the threshold voltage into the comparator, a simple calibration routine based can be employed. At the input of the comparator the threshold voltage at the desired common-mode input level is provided and the voltages V.sub.hp, V.sub.hn are varied until the comparator provides an equal numbers of ones and zeros.

[0070] While the present disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The foregoing description details certain embodiments of the present disclosure. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the present disclosure may be practiced in many ways. The present disclosure is not limited to the disclosed embodiments.

[0071] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed disclosure, from a study of the drawings, the disclosure and the appended claims. In the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality. A single processor or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems. Any reference signs in the claims should not be construed as limiting the scope.