Energy storage system comprising a modular multi-level converter

Abstract

An energy storage system (ESS) for an electrical system includes an energy storage, and a converter interface arranged for connecting the energy storage to the electrical system. The converter interface includes a modular multilevel converter in which each phase leg includes a plurality of series connected cells of which at least one is a half-bridge cell and at least one is a full-bridge cell.

Claims

1. A method performed in an energy storage system (ESS) being connected to a high voltage AC electrical system, the ESS comprising an energy storage and a converter interface having a DC link and connecting the energy storage to the high voltage AC electrical system, wherein the converter interface comprises a modular multilevel converter in which each phase leg comprises an upper arm connected to a positive pole of the DC link of the modular multilevel converter and a lower arm connected to a negative pole of the DC link of the modular multilevel converter, each arm comprising a plurality of series connected cells of which at least one is a half-bridge cell and at least one is a full-bridge cell, the method comprising: when a DC link voltage (VDC, batt) provided by the energy storage is more than or equal to a peak-to-peak voltage (VAC, peak-peak) of the high voltage AC electrical system, operating the at least one full-bridge cell to produce positive voltage; and subsequently when the DC link voltage (VDC, batt) provided by the energy storage is less than the peak-to-peak voltage (VAC, peak-peak) of the high voltage AC electrical system, operating the at least one full-bridge cell to produce negative voltage.

2. The method of claim 1, wherein the ESS has a nominal voltage of at least 30 kV or at least 50 kV, and/or up to 70 kV or up to 100 kV.

3. The method of claim 1, wherein the modular multilevel converter has three, and only three, phase legs.

4. The method of claim 3, wherein the ESS has a nominal voltage of at least 30 kV or at least 50 kV, and/or up to 70 kV or up to 100 kV.

5. The method of claim 1, wherein the energy storage comprises an electrochemical battery or a supercapacitor.

6. The method of claim 5, wherein the modular multilevel converter has three, and only three, phase legs.

7. The method of claim 5, wherein the ESS has a nominal voltage of at least 30 kV or at least 50 kV, and/or up to 70 kV or up to 100 kV.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments will be described, by way of example, with reference to the accompanying drawings, in which:

(2) FIG. 1 is a graph illustrating how voltage varies with the cell capacity in a converter for different currents, in accordance with prior art.

(3) FIG. 2 is a circuit diagram of a phase leg of a prior art ESS converter interface.

(4) FIG. 3 is a schematic circuit diagram of a phase leg of an embodiment of an ESS converter interface, in accordance with the present invention.

(5) FIG. 4a is an exemplary graph of a standard M2LC-BESS voltage waveform.

(6) FIG. 4b is an exemplary graph of an M2LC-ESS voltage waveform of an embodiment of the present invention.

(7) FIG. 5a is a graph illustrating active (P) and reactive (Q) power characteristics of an embodiment of an ESS in accordance with the present invention operating at maximum DC link voltage.

(8) FIG. 5b is a graph illustrating active (P) and reactive (Q) power characteristics of an embodiment of an ESS in accordance with the present invention with a reduced DC link voltage.

(9) FIG. 6 is a schematic circuit diagram of an embodiment of an ESS with a three-phase converter interface in accordance with the present invention.

DETAILED DESCRIPTION

(10) Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown. However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description.

(11) The present invention provides a solution that reduces the cost for the derating, and provides an extra degree of freedom in choosing the DC link and storage (e.g. battery) voltage. Battery voltage, negative-sequence capability and voltage-ampere (VA) rating can be optimized, in order to provide a high power ESS of more optimal cost. The invention proposes that some of the half-bridge cells in the standard M2LC are replaced by full-bridge cell(s).

(12) FIG. 3 is a schematic circuit diagram of a phase leg of an embodiment of an ESS 1 converter interface, in accordance with the present invention. The ESS 1, e.g. a battery energy storage system (BESS) or a supercapacitor ESS, comprises an energy storage 2 and a converter interface comprising a modular multilevel converter (M2LC) 3. The term M2LC is not intended to limit the converter to a specific type of M2LC converter, since any type of modular multilevel converter may be used with the present invention. The converter interface connects the DC energy storage 2 with the electrical system 4, e.g. an AC system such as an AC power grid or an AC motor drive, or alternatively a HVDC line connected in parallel with the energy storage 2. The M2LC 3 leg comprises an upper arm connected to the positive pole of the DC link of the converter and a lower arm connected to the negative pole of the DC link of the converter. The M2LC 3 of the embodiment in FIG. 3 is a five-level converter, implying that each arm of the phase leg has four modular cells 5 connected in series, but in other embodiments within the present invention may have any number of levels as required. Each cell 5 comprises a capacitor and a plurality of switches, each typically with an associated diode. The switches are in FIG. 3 as an example depicted as insulated-gate bipolar transistors (IGBT). However, it should be noted that these are only examples of the components of the cells. Other corresponding components known in the art may alternatively be used. As is well-known in the field, the cells of an M2LC may be half-bridge cells, with two switches, or full-bridge cells (H-bridge), with four switches. As is shown in FIG. 2, half-bridge cells are used in the converter interface of an ESS since the cells need only conduct current in one direction, and full-bridge cells are also substantially more expensive since they require more components. However, in accordance with the present invention, the converter 3 of the ESS 1 has a mix of both half-bridge cells 5a and full-bridge cells 5b. In the embodiment of FIG. 3, each arm of the phase leg has three half-bridge cells 5a and 1 full-bridge cell 5b, but other embodiments with two or even three of the four cells 5 being full-bridge cells 5b are also contemplated. In FIG. 3, the full-bridge cell(s) are closest to the AC system 4. This may be preferred in some embodiments, but any order of half-bridge cells 5a and full-bridge cells 5b within each arm may be used as convenient.

(13) Replacing some half-bridge cells 5a with full-bridge cells 5b enables the converter arms to synthesize (at least some) negative voltage that makes it possible to operate the converter 3 with a DC link voltage V.sub.DC, batt lower than the line peak-to-peak voltage V.sub.AC, peak-peak. At the same time, the arm voltage rating will not need to be increased to handle the variable battery voltage, since when the battery voltage is low, the full-bridge(s) 5b may synthesize a sinusoidal voltage without or with reduced DC offset. When battery voltage is high, the full-bridge cells may be operating as half-bridges 5a, producing only positive (or negative) voltage.

(14) FIG. 4a shows upper and lower arm voltage waveforms for a standard M2LC-BESS. The full lines represent the waveforms at maximum battery voltage, the dashed lines represent the waveforms at minimum battery voltage, and the dotted lines represent the nominal battery voltage. Thus, the minimum battery voltage V.sub.batt, min is the distance between the dashed line waveforms. Since only half-bridge cells 5a are used, the arm voltages are prohibited from crossing the zero line in the graph. The maximum voltage V.sub.arm, req over each of the arms of the converter, i.e. the voltage the arm is required to be rated for, is the distance between the peak voltage at maximum battery voltage and the zero voltage line.

(15) FIG. 4b shows upper and lower arm voltage waveforms for the same arrangement as in 4a but where the converter has been changed for a converter 3 in accordance with the present invention, thus having some full-bridge cells 5b able to provide negative arm voltage capability. The full lines represent the waveforms at maximum battery voltage, the dashed lines represent the waveforms at minimum battery voltage, and the dotted lines represent the nominal battery voltage. Thus, the minimum battery voltage V.sub.batt, min is the distance between the dashed line waveforms. Due to the use of full-bridges for boosting the battery voltage by producing negative voltage, the arm voltages are allowed to pass the zero line in the graph, whereby the V.sub.batt, min is substantially smaller than for the standard converter of FIG. 4a. Consequently, the maximum voltage V.sub.arm, req over each of the arms of the converter are is also markedly reduced and is less than the AC peak-to-peak voltage.

(16) In FIGS. 4a and 4b, it has been assumed a battery voltage that varies about 33%, e.g. from between approximately 2.7 to 4.0 V per battery cell. This is realistic and may even be a bit conservative. For instance, the battery cells of the energy storage 2 used in some BESS can be safely operated between 2.3 and 4.1 V. Supercapacitors may have an even larger voltage variation. In the FIGS. 4a and 4b it has also been assumed that one out of four half bridge cells 5a has been replaced with a full-bridge cell 5b. To optimize cost and losses, the ratio between half- and full-bridge cells 5 may be selected differently for different applications. The energy storage 2 of the present invention may have a relatively high nominal voltage, e.g. at least 30 kV or at least 50 kV, and/or up to 70 kV or up to 100 kV.

Example 1

(17) When the DC link voltage is reduced, a larger current is needed to handle negative-sequence load currents at the AC side of a converter 3.

(18) A first step to control the second order harmonic is to find the voltage ripple on the capacitors and correct the insertion index at all times using this voltage ripple. Then the modulation indices of upper and lower arms of a phase leg, e.g. of phase A, are as follows:

(19) $\begin{array}{cc}{\mathrm{nau}}_{\mathrm{arm}}=\frac{U_{\mathrm{battery}}-\mathrm{mU}\sin \left(t\right)}{2U+U_{\mathrm{ruarm}}}& \left(I\right)\\ {\mathrm{nal}}_{\mathrm{arm}}=\frac{U_{\mathrm{battery}}-\mathrm{mU}\sin \left(t\right)}{2U+U_{\mathrm{rlarm}}}& \left(\mathrm{II}\right)\end{array}$

(20) Where:

(21) nau.sub.arm=insertion index for the upper arm Aa.

(22) nal.sub.arm=insertion index for the lower arm Ab.

(23) U.sub.battery=battery 2 pole-to-ground voltage.

(24) $\begin{array}{cc}U=\frac{{\hat{U}}_{\mathrm{AC},\mathrm{pole}\text{-}\mathrm{to}\text{-}\mathrm{ground}}}{m}& \left(\mathrm{III}\right)\end{array}$

(25) m=modulation index of the cells 5.

(26) U.sub.ruarm=voltage reference value to compensate for capacitor voltage ripples in both half-bridge 5a and full-bridge 5b cells in the upper arm.

(27) U.sub.rlarm=voltage reference value to compensate for capacitor voltage ripples in both half-bridge 5a and full-bridge 5b cells in the lower arm.

(28) A preliminary solution for finding these voltage ripples is to filter out the sum of the capacitor voltages via the filter. First, the DC component of the capacitor voltages is cancelled out by using a first-order band stop filter at:

(29) $\begin{array}{cc}=0\frac{\mathrm{rad}}{\sec }& \left(\mathrm{IV}\right)\end{array}$

(30) After the DC component is cancelled out, 10 second-order bandpass filters are used to extract the voltage ripples. A circulating current control and voltage balancing of the converter 3 arm can be achieved while 40% voltage drop has been applied at the DC side, when full-bridge cells 5b are generating the negative arm voltage while half-bridges are bypassed.

Example 2

(31) To select the best and most cost-effective ratio between the number of half-bridge cells 5a and full-bridge cells 5b, an optimization may be performed and it is proportional to the voltage drop. Normally, half of the voltage drop rating is required for the full-bridge cell(s) 5b in each arm to be able to have maximum AC voltage. However, factors that must be considered include but are not limited to Cost for converter 3 voltage over-rating related to energy storage 2 voltage variations. Cost for converter 3 current over-rating related to negative-sequence requirements. Energy storage 2 system rating and additional cost for high-voltage protection such as static DC breakers.

(32) It can be mathematically shown that the DC link voltage dropping while maintaining a stable operation for the converter has some limitation. This is shown in FIGS. 5a and 5b in which the real (P) and reactive (Q) power characteristics for the ESS of the present invention are considered. FIG. 5a relates to a situation with maximum energy storage 2 voltage, while FIG. 5b relates to a situation when the converter 3 operates with a reduced energy storage 2 voltage and thus a reduced DC link voltage. S is apparent power, P is active (real) power, Q is reactive power and j is the imaginary operator. It is noted that this is a generic illustration, and that actual P-Q diagrams may be somewhat different.

(33) One conservative limit was found based on the energy fluctuation in the full-bridge cells 5b. To have zero energy in each half and full bridge cells over one cycle allows to find out whether the full-bridges 5b can regain this lost energy during the negative voltage generation or not. At this limit, all non-DC circulating currents were assumed to be cancelled out by a perfect current controller.

(34) Another limit was found based on the sign of the current in the arm.

(35) Simulation results show that voltage drop of up to 50% is possible without having to make any major considerations.

Example 3

(36) FIG. 6 illustrates an example of an ESS 1 of the present invention, in which a 3-phase M2LC 3 is used. The converter 3 has three phase legs A, B and C, to each of which as an upper arm Aa, Ba and Ca as well as a lower arm Ab, Bb and Cb. Again, the converter 3 is a five-level converter in which each arm has four modular cells 5. In accordance with the present invention, each arm has at least one half-bridge cell 5a and at least one full-bridge cell 5b. In the exemplary embodiment of FIG. 6, each arm has two half-bridge cells 5a and two full-bridge cells 5b. As discussed herein, the present invention may be used with any number of phases and levels of the converter 3.

(37) The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.