Static switch

Abstract

A thyristor switch is constituted of a pair of arms connected in anti-parallel, each of the arms including a plurality of thyristors connected in series. A controller includes a phase detecting unit configured to detect a phase of a power supply voltage supplied from an alternating-current power supply, and a gate signal generating unit configured to interrupt a gate signal when an open command is provided to the static switch and the phase of the power supply voltage detected by the phase detecting unit matches a target phase. The target phase is set outside of a phase range where interruption of the gate signal is prohibited, the phase range being set so as to include a zero crossing point at which a load current is switched in polarity.

Claims

1. A static switch for switching between electrical connection and disconnection between an alternating-current power supply and a load, the static switch comprising: a thyristor switch connected between the alternating-current power supply and the load and including a pair of arms connected in anti-parallel, each of the arms including a plurality of thyristors connected in series; and a controller configured to perform on-off control of the thyristor switch, the thyristor switch being configured to be turned on in response to a gate signal supplied from the controller, and turned off in response to a current coming to zero in a state in which the gate signal is interrupted, the controller including: a phase detecting unit configured to detect a phase of a power supply voltage supplied from the alternating-current power supply, and a gate signal generating unit configured to interrupt the gate signal when an open command is provided to the static switch and when the phase of the power supply voltage detected by the phase detecting unit matches a target phase, the target phase being set outside of a phase range where interruption of the gate signal is prohibited, the phase range being set so as to include a zero crossing point at which a load current is switched in polarity.

2. The static switch according to claim 1, wherein the controller further includes a target phase setting unit configured to set the target phase, and the target phase setting unit is configured to set the phase range where interruption of the gate signal is prohibited based on a power factor angle of the load, and set the target phase outside of the phase range.

3. The static switch according to claim 1, wherein an upper limit and a lower limit of the phase range where interruption of the gate signal is prohibited are set so as to satisfy a condition that all of the plurality of thyristors constituting each of the pair of arms have a conduction current larger than or equal to a holding current.

4. The static switch according to claim 2, wherein an upper limit and a lower limit of the phase range where interruption of the gate signal is prohibited are set so as to satisfy a condition that all of the plurality of thyristors constituting each of the pair of arms have a conduction current larger than or equal to a holding current.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a circuit configuration diagram of a static switch according to an embodiment of the present invention.

(2) FIG. 2 is a waveform diagram for explaining an operation of a thyristor switch when a gate signal is in an on-state.

(3) FIG. 3 is a waveform diagram for explaining one mode of an operation of a thyristor switch when a gate signal is switched off.

(4) FIG. 4 is a waveform diagram for explaining another mode of an operation of a thyristor switch when a gate signal is switched off.

(5) FIG. 5 is a diagram for explaining the concept of an open phase control of a thyristor switch according to an embodiment of the present invention.

(6) FIG. 6 is a diagram for explaining the concept of an open phase control of a thyristor switch according to an embodiment of the present invention.

(7) FIG. 7 is a functional block diagram showing a control structure of a controller in a static switch according to an embodiment of the present invention.

(8) FIG. 8 is a timing chart explaining an open phase control of a thyristor switch according to an embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

(9) An embodiment of the present invention is described below in detail with reference to the drawings. In the following, identical or equivalent portions are denoted with identical reference signs in the drawings, and explanations for the portions are not repeated in principle.

(10) FIG. 1 is a circuit configuration diagram of a static switch according to an embodiment of the present invention. With reference to FIG. 1, the static switch is a switch for switching between electrical connection and disconnection between an alternating-current power supply 2 and a load 3. The static switch includes a thyristor switch 1 and a controller 4.

(11) Thyristor switch 1 is connected between alternating-current power supply 2 and load 3. In FIG. 1, a power supply voltage of alternating-current power supply 2 is denoted by V, an inter-terminal voltage of thyristor switch 1 is denoted by Vs, and a current (load current) supplied through thyristor switch 1 to load 3 is denoted by I. In the following description, in order to facilitate understanding of an operation of thyristor switch 1, load 3 is assumed to be an inductive load.

(12) Thyristor switch 1 includes a pair of thyristor arms TA1, TA2 connected in anti-parallel. Each of thyristor arms TA1, TA2 is constituted of a plurality of thyristors T1-Tn (where n is an integer of two or more) connected in series. Thyristors T1-Tn are turned on in response to a gate signal G input (switched on) from controller 4. On-state thyristors T1-Tn are turned off in response to the current coming to zero in a state in which gate signal G is interrupted (switched off). In the following, thyristor arms TA1, TA2 are also simply referred to as thyristor arm TA when they are expressed comprehensively, and thyristors T1-Tn are also simply referred to as thyristor T when they are expressed comprehensively.

(13) Controller 4 performs on-off control of thyristor switch 1. Controller 4 is implemented mainly by, for example, a central processing unit (CPU), a memory, and an interface circuit. In response to open and close commands supplied from a high-order control unit (not shown), controller 4 generates gate signal G to be supplied to thyristor switch 1. A control structure of controller 4 will be described later.

(14) FIG. 2 is a waveform diagram for explaining an operation of thyristor switch 1 when gate signal G is in an on-state.

(15) With reference to FIG. 2, load current I is delayed in phase by a power factor angle of load with respect to power supply voltage V. During negative half cycles in the sinusoidal waveform of load current I, thyristor arm TA2 of thyristor switch 1 is ON. On the other hand, during positive half cycles in the sinusoidal waveform, thyristor arm TA1 is ON. Thus, while gate signal G is being supplied, thyristor arm TA1 and thyristor arm TA2 are alternately comes into an on-state every half cycle in accordance with the polarity of load current I. Accordingly, inter-terminal voltage Vs of thyristor switch 1 presents substantially zero.

(16) FIG. 3 is a waveform diagram for explaining one mode of an operation of thyristor switch 1 when gate signal G is switched off in order to open thyristor switch 1. FIG. 3 shows an operation of thyristor switch 1 in the case where gate signal G is switched off at a point in time at which a phase of power supply voltage V is delayed from a point of zero by phase during a positive half cycle of power supply voltage V.

(17) With reference to FIG. 3, in the case where phase is smaller than power factor angle (0<<), load current I is negative in polarity and thyristor arm TA2 remains ON at a point in time at which gate signal G is switched off. Then, when load current I reaches a zero point, thyristor arm TA2 is turned off. At this time, thyristor arm TA1, to which gate signal G is not supplied, is not turned on. As a result, thyristor switch 1 comes into an open state. At the timing when thyristor switch 1 comes into the open state, power supply voltage V is applied in a positive direction between the terminals of thyristor switch 1.

(18) As described below, however, thyristor T of thyristor switch 1 may be subject to unwanted stress depending on phase at which gate signal G is switched off.

(19) FIG. 4 is a waveform diagram for explaining another mode of an operation of thyristor switch 1 when gate signal G is switched off. FIG. 4 shows an operation of thyristor switch 1 in the case where gate signal G is switched off at a zero crossing point at which load current I is switched in polarity (in the case where phase is equal to power factor angle ).

(20) With reference to FIG. 4, thyristor arm TA2 is turned off at a zero crossing point of load current I. Since gate signal G is switched off at a zero crossing point, thyristor arm TA1 is not turned on. As a result, thyristor switch 1 comes into an open state and power supply voltage V is applied in the positive direction between the terminals of thyristor switch 1.

(21) Now consideration is given to an operation of thyristor switch 1 in the case where gate signal G is switched off immediately after a zero crossing point of load current I.

(22) As shown in FIG. 2, in the case where gate signal G is ON, thyristor arm TA2 is turned off and thyristor arm TA1 is turned on at a zero crossing point of load current I. On the other hand, in the case where gate signal G is switched off prior to a zero crossing point of load current I (see FIG. 3) or where gate signal G is switched off at a zero crossing point of load current I (see FIG. 4), that is, in the case where phase is smaller than or equal to power factor angle , thyristor arm TA1 is not turned on at a zero crossing point of load current I.

(23) However, in the case where gate signal G is switched off slightly after a zero crossing point of load current I, that is, in the case where phase is slightly larger than power factor angle (=+), thyristor arm TA1 is turned on at a zero crossing point of load current I. Accordingly, gate signal G is switched off immediately after load current I starts to flow through thyristor arm TA1. In such a case, two problems described below may arise.

(24) Firstly, a non-uniform state may occur among a plurality of thyristors T1-Tn constituting thyristor arm TA1 due to differences in element characteristics. The non-uniform state is a state where some thyristors are turned on and the other thyristors remain in an off-state without being turned on during a short period of time (<<) from a zero crossing point of load current I to a point at which gate signal G is supplied. If such a non-uniform state occurs in thyristors T1-Tn connected in series due to variations in timing of turn-on, inter-terminal voltage Vs of thyristor switch 1 is intensively applied to some off-state thyristors. Since inter-terminal voltage Vs is equal to power supply voltage V, an overvoltage may be applied to the off-state thyristors depending on power supply voltage V in the case where alternating-current power supply 2 is a high-voltage system.

(25) Secondly, once thyristors are supplied with gate signal G and turned on, a load current flows through the thyristors. After gate signal G is switched off, thyristors that have a load current larger than or equal to a latching current still remain ON until the next zero crossing point. On the other hand, thyristors that have a load current smaller than a latching current are turned off at a point in time at which gate signal G is switched off. Since the latching current is caused by element variations, it takes time for some on-state thyristors to be turned off after gate signal G is switched off. As a result, switching losses generated in these thyristors are increased, causing stress on these thyristors.

(26) In this way, in the case where gate signal G is switched off immediately after a zero crossing point of load current I, thyristors T constituting thyristor arm TA may be subject to unwanted stress. As measures to prevent such problems, a static switch according to this embodiment performs an open phase control of thyristor switch 1, where phase at which thyristor arm TA is turned off is controlled in opening thyristor switch 1.

(27) The open phase control of the thyristor switch according to this embodiment is described below.

(28) FIGS. 5 and 6 are diagrams for explaining the concept of the open phase control of thyristor switch 1 according to this embodiment.

(29) FIG. 5 shows waveforms of power supply voltage V and load current I in the case where load 3 is a purely resistive load. As shown in FIG. 5, since =0 (where is a power factor angle of load), the zero crossing points of load current I are at =0, 180, and 360.

(30) In this embodiment, a range of phase where switch-off of gate signal G is prohibited is set within a phase range that includes a zero crossing point and phases near the zero crossing point of load current I. In the following description, a phase range is also referred to as a gate-off prohibition zone. In FIG. 5, the phase ranges of 0, 180180+, and 360360 (corresponding to ranges RGN1 in FIG. 5) are set as gate-off prohibition zones.

(31) An upper limit and a lower limit of each gate-off prohibition zone (corresponding to phase in FIG. 5) are preferably set so as to satisfy the condition that all of a plurality of thyristors T1-Tn constituting thyristor arm TA have a conduction current larger than or equal to a holding current. In this case, all of thyristors T1-Tn are in an on-state at phases outside of gate-off prohibition zones. Therefore, whichever phase outside gate-off prohibition zones the gate signal G is switched off at, an overvoltage can be prevented from being applied to some of thyristors T1-Tn.

(32) FIG. 6 shows waveforms of power supply voltage V and load current I in the case where load 3 is an inductive load. As shown in FIG. 6, the zero crossing points of load current I are at = (power factor angle) and 180+.

(33) When power factor angle of load is in the range of 0-90, a zero crossing point of load current I appears within the range. Accordingly, in FIG. 6, phase ranges of 090 and 180270 (corresponding to ranges RGN2 in FIG. 6) are set as gate-off prohibition zones, as an example. As in the case of FIG. 5 (where power factor angle is zero), an upper limit and a lower limit of each gate-off prohibition zone are preferably set so as to satisfy the condition that all of a plurality of thyristors T1-Tn constituting thyristor arm TA have a conduction current larger than or equal to a holding current.

(34) When a gate-off prohibition zone is set in accordance with power factor angle of load in this way, a target phase (hereinafter also referred to as a gate-off phase) .sub.OFF at which gate signal G is to be switched off is set outside of the set gate-off prohibition zone. In this embodiment, a phase that is not included in either of a gate-off prohibition zone in the case where load 3 is a purely resistive load (see FIG. 5) or a gate-off prohibition zone in the case where load 3 is an inductive load (see FIG. 6) is set as gate-off phase .sub.OFF. FIGS. 5 and 6 show a case where gate-off phase .sub.OFF is set to 120 and 300 (=180+120).

(35) FIG. 7 is a functional block diagram showing a control structure of controller 4 in the static switch according to this embodiment.

(36) With reference to FIG. 7, controller 4 includes a phase detecting unit 10, a gate signal generating unit 20, and a target phase setting unit 40.

(37) A voltage detector 6 detects a voltage (power supply voltage) V of alternating-current power supply 2. Power supply voltage V detected by voltage detector 6 is supplied to phase detecting unit 10 in controller 4. Phase detecting unit 10 detects phase of power supply voltage V detected by voltage detector 6.

(38) Target phase setting unit 40 sets gate-off phase .sub.OFF based on power factor angle of load that is externally input. Specifically, target phase setting unit 40 sets a gate-off prohibition zone based on power factor angle of load and then sets gate-off phase .sub.OFF outside of the set gate-off prohibition zone (see FIGS. 5 and 6). Target phase setting unit 40 outputs the set gate-off phase .sub.OFF to gate signal generating unit 20.

(39) In the example configuration of FIG. 7, phase detecting unit 10 resets phase of power supply voltage V for each zero crossing point of the sinusoidal wave to treat the phase as the range of 0-180, based on the symmetry of positive and negative of power supply voltage V. Also, with an assumption that power factor angle of load 3 is in the range of 0-90, target phase setting unit 40 sets gate-off phase .sub.OFF to 120.

(40) Gate signal generating unit 20 compares phase of power supply voltage V detected by phase detecting unit 10 and gate-off phase .sub.OFF set by target phase setting unit 40 with each other. Gate signal generating unit 20 then generates gate signal G based on the comparison results.

(41) Specifically, gate signal generating unit 20 includes a comparing unit 22, a one-shot pulse generating unit 24, a NOT circuit 26, an AND circuit 28, and RS flip-flop circuits 30, 32, 34.

(42) Comparing unit 22 compares phase of power supply voltage V and gate-off phase .sub.OFF (=120 with each other. If phase is larger than or equal to gate-off phase .sub.OFF, comparing unit 22 sets an output signal to activation level 1. On the other hand, if phase is smaller than gate-off phase .sub.OFF, comparing unit 22 sets an output signal to inactivation level 0.

(43) An output signal of comparing unit 22 is input to one-shot pulse generating unit 24. One-shot pulse generating unit 24 generates a one-shot pulse signal having a predetermined pulse width in response to a rise of an output signal of comparing unit 22. The generated pulse signal is input to one input of AND circuit 28.

(44) RS flip-flop circuit 32 is a reset dominant RS flip-flop circuit. RS flip-flop circuit 32 receives an open command of thyristor switch 1 from a high-order control unit (not shown). Specifically, RS flip-flop circuit 32 receives a close command of thyristor switch 1 with a set terminal S, and receives an open command of thyristor switch 1 with a reset terminal R. When the close command is at the H (logical high) level in activation level, RS flip-flop circuit 32 outputs an H level signal from an output terminal Q. When the open command is at the H level in activation level, RS flip-flop circuit 32 outputs an L (logical low) level signal from output terminal Q. Since RS flip-flop circuit 32 is of a reset dominant type, it outputs an L level signal from output terminal Q when the close command and the open command are both at the H level. Output of RS flip-flop circuit 32 is input to NOT circuit 26 and to a set terminal S of RS flip-flop circuit 34.

(45) NOT circuit 26 inverts an output signal of RS flip-flop circuit 32. Output of NOT circuit 26 is input to the other input of AND circuit 28.

(46) AND circuit 28 calculates a logical AND of a pulse signal and an output signal of NOT circuit 26 (inversion signal of output of RS flip-flop circuit 32). When the close command is at the H level, AND circuit 28 outputs an L level signal. On the other hand, when the open command is at the H level, AND circuit 28 outputs an H level signal during a period in which the pulse signal is at the H level, and outputs an L level signal during a period in which the pulse signal is at the L level. A period in which output of AND circuit 28 is at the H level corresponds to the pulse width of a pulse signal output from one-shot pulse generating unit 24.

(47) RS flip-flop circuit 30 is a set dominant RS flip-flop circuit. RS flip-flop circuit 30 receives output of AND circuit 28 with a set terminal S. and receives output of RS flip-flop circuit 32 with a reset terminal R. RS flip-flop circuit 30 outputs an H level signal from an output terminal Q when output of AND circuit 28 is at the H level. That is, when the open command is at the H level and the pulse signal is at the H level, RS flip-flop circuit 30 outputs an H level signal from output terminal Q. Also, RS flip-flop circuit 30 outputs an L level signal from output terminal Q when output of RS flip-flop circuit 32 is at the H level. That is, when the close command is at the H level, RS flip-flop circuit 30 outputs an L level signal from output terminal Q. Since RS flip-flop circuit 30 is of a set dominant type, it outputs an H level signal from output terminal Q when output of AND circuit 28 and output of RS flip-flop circuit 32 are both at the H level. In other words, when the open command is at the H level, RS flip-flop circuit 30 outputs an H level signal within a range of time corresponding to the pulse width of a pulse signal starting from a point in time at which phase of power supply voltage V reaches gate-off phase .sub.OFF.

(48) RS flip-flop circuit 34 is a reset dominant RS flip-flop circuit. RS flip-flop circuit 34 receives output of RS flip-flop circuit 32 with a set terminal S, and receives output of RS flip-flop circuit 30 with a reset terminal R. RS flip-flop circuit 34 outputs an H level signal from an output terminal Q when output of RS flip-flop circuit 32 is at the H level. That is, RS flip-flop circuit 34 outputs an H level signal from output terminal Q when the close command is at the H level. Also, RS flip-flop circuit 34 outputs an L level signal from output terminal Q when output of RS flip-flop circuit 30 is at the H level. That is, when the open command is at the H level and the pulse signal is at the H level, RS flip-flop circuit 34 outputs an L level signal from output terminal Q. Since RS flip-flop circuit 34 is of a reset dominant type, it outputs an L level signal from output terminal Q when output of RS flip-flop circuit 32 and output of RS flip-flop circuit 30 are both at the H level. Output of RS flip-flop circuit 34 is supplied to thyristor arms TA1, TA2 of thyristor switch 1 as gate signal G.

(49) In summary, when the close command is at the H level, gate signal generating unit 20 outputs H level gate signal G. On the other hand, when the open command is at the H level and the pulse signal is at the H level, gate signal generating unit 20 outputs L level gate signal G. In other words, when the open command is at the H level, gate signal generating unit 20 outputs L level gate signal G within a range of time corresponding to the pulse width of a pulse signal starting from a point in time at which phase of power supply voltage V reaches gate-off phase .sub.OFF.

(50) In thyristor switch 1, gate signal G is input to thyristor arms TA1, TA2 in response to H level gate signal G, and gate signal G is switched off in response to L level gate signal G.

(51) FIG. 8 is a timing chart explaining an open phase control of thyristor switch 1 according to this embodiment.

(52) With reference to FIG. 8, gate signal G presents the H level on and after time t0. Accordingly, gate signal G is supplied to each of thyristor arms TA1, TA2 of thyristor switch 1.

(53) In controller 4, phase of power supply voltage V detected by phase detecting unit 10 and gate-off phase .sub.OFF (e.g. 120) are always compared with each other by comparing unit 22. When phase of power supply voltage V reaches gate-off phase .sub.OFF during each positive half cycle and each negative half cycle of power supply voltage V according to the comparison results at comparing unit 22, one-shot pulse generating unit 24 generates a one-shot pulse signal having a predetermined pulse width t.

(54) Here, lets assume that an open command activated at the H level is supplied to controller 4 from a high-order control unit at time t1. In controller 4, in response to the H level open command, gate signal generating unit 20 executes the control process shown in FIG. 7 using the H level open command and a pulse signal, thereby generating gate signal G. Gate signal G transitions from the H level to the L level in response to a rise of a pulse signal at time t2 after time t1, as shown in FIG. 8. The transition of gate signal G to the L level causes gate signal G that has been supplied to thyristor arms TA1, TA2 of thyristor switch 1 to be switched off.

(55) The switch-off of gate signal G at time t2 causes one of the thyristor arms TA1, TA2 that is in an on-state to be turned off at a zero crossing point of load current I after time t2. On the other hand, the other of the thyristor arms TA1, TA2 that is in an off-state is not turned on at the zero crossing point of load current I. As a result, thyristor switch 1 comes into an open state.

(56) Thus, the static switch according to this embodiment sets gate-off phase .sub.OFF outside of a gate-off prohibition zone that includes a zero crossing point and phases near the zero crossing point of load current I. This can prevent unwanted stress from being applied to thyristor T constituting thyristor arm TA when gate signal G is switched off in response to an open command of thyristor switch 1. As a result, a failure of thyristor switch 1 can be avoided and the life of the static switch can be prolonged.

(57) In the above embodiment, a case is described as an example where target phase setting unit 40 is provided in controller 4 to set gate-off phase .sub.OFF (target phase) of thyristor switch 1. Instead of target phase setting unit 40, however, an input unit may be provided to receive input of gate-off phase .sub.OFF from a component external to the static switch. Power factor angle of load is uniquely determined based on the operation conditions of a system in which the static switch according to the present invention is used. Therefore, a user of the system can set gate-off phase .sub.OFF based on power factor angle and input it to controller 4.

(58) It should be considered that the embodiment described herein is not limitative but illustrative in all respects. It is intended that the scope of the present invention is defined not by the above description but by the claims and includes all the modifications within the meaning and scope of equivalents of the claims.

REFERENCE SIGNS LIST

(59) 1: thyristor switch; 2: alternating-current power supply; 3: load; 4: controller; 10: phase detecting unit; 20: gate signal generating unit; 22: comparing unit; 24: one-shot pulse generating unit; 26: NOT circuit; 28: AND circuit; 30, 32, 34: RS flip-flop circuit; 40: target phase setting unit