Phase locked loop circuit with charge pump up-down current mismatch adjustment and static phase error reduction

Abstract

A magnitude difference between intrinsic positive and negative current components forming a PLL's charge pump output current is determined by simultaneously outputting the intrinsic positive and negative pump current components, and incrementally increasing a bias current added to one of the intrinsic current components (e.g., such that the total positive current component is gradually increased). Calibration control voltages generated by the calibration pump output current are measured to determine when magnitudes of the adjusted (e.g., positive) current component and the non-adjusted/intrinsic (e.g., negative) current component are equal, and the bias current amount required to achieve equalization is stored as a digital converter code. During subsequent normal PLL operations, the digital converter code is utilized to control the charge pump such that the magnitude of the positive current component is adjusted by the bias current amount such that the positive and negative current components are matched.

Claims

1. A phase locked loop (PLL) circuit configured to generate a PLL output signal such that an output phase of the PLL output signal matches the input phase of an applied input signal, the PLL circuit comprising: a phase frequency detector configured to generate at least one pump control voltage in response to a phase difference between said output phase and said input phase; a charge pump circuit configured to generate a pump output current on a pump output terminal in response to said at least one pump control voltage such that said pump output current includes an intrinsic positive current component having a first intrinsic magnitude when said at least one pump control voltage has a first pump control value, and such that said pump output current includes an intrinsic negative current component having a second intrinsic magnitude when said at least one pump control voltage has a second pump control value; and a charge pump control circuit configured to determine a magnitude difference between said first intrinsic magnitude and said second intrinsic magnitude and configured to generate a bias control signal having a voltage level corresponding to said determined magnitude difference, wherein said charge pump circuit is further configured to generate a bias current in response to said bias control signal such that said bias current is combined with one of the intrinsic positive current component and said intrinsic negative current component to generate a combined current component, and such that a combined magnitude of said combined current component is equal to said intrinsic magnitude of the other of said intrinsic positive current component and said intrinsic negative current component.

2. The PLL circuit of claim 1, further comprising: a capacitive circuit coupled to said pump output terminal and configured to generate a controlled voltage in response to the pump output current; a voltage controlled oscillator (VCO) coupled to said capacitive circuit and configured to generate said PLL output signal such that said output phase is adjusted in accordance with said controlled voltage; and a feedback circuit configured to transmit a feedback signal, which corresponds with the output phase, to the phase frequency detector.

3. The PLL circuit of claim 1, wherein the phase frequency detector is configured to assert a first pump control voltage when said output phase leads the input phase and to assert a second pump control voltage when said output phase lags the input phase, and wherein the charge pump circuit comprises: a first pull-up switch configured to apply said intrinsic positive current component on said pump output terminal when said first pump control voltage is asserted; a first pull-down switch configured to apply said intrinsic negative current component on said pump output terminal when said second pump control voltage is asserted; and one or more bias current transistors operably configured to generate said bias current in response to the bias control signal generated by the bias generator.

4. The PLL circuit of claim 3, wherein said one or more bias current transistors comprises a pull-up transistor coupled between a high voltage source and said pump output terminal.

5. The PLL circuit of claim 1, wherein the charge pump control circuit comprises: a difference measurement circuit configured to calculate and store a digital converter code value corresponding to the determined magnitude difference between said first intrinsic magnitude of said intrinsic positive current component and said second intrinsic magnitude of said intrinsic negative current component; and a bias generator configured to generate said bias control signal in accordance with said digital converter code value.

6. The PLL circuit of claim 5, further comprising a capacitive circuit coupled to said pump output terminal and configured to generate a controlled voltage in response to the pump output current, wherein the charge pump control circuit is further configured to control at least one of said phase frequency detector and said charge pump during a calibration period such that said charge pump simultaneously applies said intrinsic positive current component, said intrinsic negative current component, and a time-varying bias current to said pump output terminal, wherein the difference measurement circuit is configured to measure said controlled voltage generated by said capacitive circuit during said calibration period.

7. The PLL circuit of claim 5, wherein said bias generator comprises a digital-to-analog converter configured to generate said bias control signal by way of converting said digital converter code value to an associated voltage level.

8. The PLL circuit of claim 6, wherein said difference measurement circuit further comprises: an envelope detector coupled to the capacitive circuit and configured to generate an envelope signal based on said controlled voltage; and a comparator configured to compare the envelope signal with said controlled voltage.

9. The PLL circuit of claim 8, wherein said difference measurement circuit further comprises an amplifier coupled to the capacitive circuit and configured to amplify the controlled voltage, and wherein the comparator is configured to indicate when the envelope signal deviates from said amplified controlled voltage.

10. The PLL circuit of claim 8, further comprising a lock circuit configured to generate a frequency lock signal having a first value when said output phase of the PLL output signal matches the input phase of the applied input signal, wherein the difference measurement circuit further comprises a counter configured to increment in accordance with changes in the current level of said bias current, and wherein the difference measurement circuit is configured to determine said digital adjustment code value based on one-half of a count value accrued on the counter between a first time when the frequency lock signal switches to said first value and the controlled voltage has a first value, and a second time when the comparator indicates the controlled voltage has returned to the first value.

11. The PLL circuit of claim 5, wherein the charge pump control circuit comprises a calibration charge pump configured to generate to generate a calibration pump output current on a calibration pump output terminal such that said calibration pump output current includes a duplicate intrinsic positive current component having said first intrinsic magnitude and a duplicate intrinsic negative current component having said second intrinsic magnitude; wherein said charge pump control circuit is further configured such that said calibration pump output current includes a combination of said duplicate intrinsic positive current component, said intrinsic negative current component, and a time-varying bias current during a calibration period, wherein the difference measurement circuit is configured to measure a controlled voltage generated in response to the calibration pump output current during said calibration period.

12. A phase locked loop (PLL) circuit configured to generate an output signal such that an output phase of the output signal matches the input phase of an input signal, the PLL circuit comprising: a charge pump circuit configured to generate an output current including one of a positive current component and a negative current component when said at least one pump control voltage has the second value, wherein said charge pump circuit is further configured such that one of a first magnitude of said positive current component and a second magnitude of said negative current component is adjusted to include a bias current; and a charge pump control circuit configured to generate a pump bias voltage having a voltage level that varies in accordance with a digital value of a stored digital adjustment code, wherein said charge pump control circuit is further configured to transmit said pump bias voltage to said charge pump circuit such that said bias current has a current level that varies in accordance with the voltage level of said pump bias voltage.

13. A method for adjusting a charge pump output current in a phase locked loop circuit such that a magnitude difference between a positive current component and a negative current component forming said charge pump output current during normal PLL operating periods is minimized, the method comprising: controlling a charge pump during a calibration period to generate a time-varying calibration current by simultaneously applying said intrinsic positive current component, said intrinsic negative current component and an incrementally changing bias current to a pump output terminal of said charge pump; measuring a time-varying calibration controlled voltage generated in response to said time-varying calibration current during said calibration period; determining a current adjustment amount by detecting an inflection point of the time-varying calibration controlled voltage, and identifying an amount of said bias current applied to pump output terminal at the time of said inflection point; and adjusting the charge pump output current such that said positive current component is increased by the determined current adjustment amount during said normal operating period.

14. The method of claim 13, wherein controlling the charge pump during the calibration period comprises: coupling the pump output terminal to a high voltage source by way of a pull-up switch such that said intrinsic positive current component passes through the pull-up switch; coupling the pump output terminal to a low voltage source by way of a pull-down switch such that said intrinsic negative current component passes through the pull-down switch; and utilizing an incrementally changing bias voltage to control a transistor coupled between said pump output terminal and one of said high voltage source and said low voltage source such that said transistor passes said incrementally changing bias current to the pump output terminal in response to said incrementally changing bias voltage.

15. The method of claim 14, wherein adjusting the charge pump such that said positive current component is increased by the determined current adjustment amount during said normal operating period comprises utilizing a bias voltage to control said transistor such that a bias current equal to the determined current adjustment amount is passed through said transistor during said normal operating period.

16. The method of claim 15, further comprising storing a digital adjustment code having a digital value corresponding to said determined current adjustment amount, wherein utilizing said bias voltage to control said transistor during said normal operating period comprises generating said bias voltage in accordance with said stored digital adjustment code.

17. The method of claim 16, generating said bias voltage comprises utilizing a digital-to-analog converter configured to receive said stored digital adjustment code and to generate said bias voltage at a voltage level corresponding to said digital value of said digital adjustment code.

18. The method of claim 16, wherein determining the current adjustment amount comprises incrementing a counter value in accordance with incremental changes to the incrementally changing bias current, and utilizing said counter value to determine said digital value of said digital adjustment code.

19. The method of claim 18, wherein determining the current adjustment amount comprises applying said time-varying calibration controlled voltage to an envelope detector, and comparing an output from said envelope detector with said time-varying calibration controlled voltage.

20. The method of claim 13, wherein adjusting the charge pump output current during said normal operating period comprises adjusting a primary charge pump such that said positive current component generated by said primary charge pump is increased by the determined current adjustment amount, and wherein said controlling a charge pump during the calibration period comprises controlling a secondary charge pump.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings, where:

(2) FIG. 1 illustrates an enhanced PLL circuit according to a generalized embodiment of the invention;

(3) FIG. 2 illustrates a time-voltage curve generated in accordance with an exemplary embodiment;

(4) FIGS. 2A, 2B and 2C illustrate a charge pump circuit during various operating periods according to an exemplary embodiment;

(5) FIG. 3 illustrates a PLL loop circuit according to an exemplary embodiment;

(6) FIG. 4 illustrates a charge mismatch cancellation method according to another exemplary embodiment;

(7) FIG. 5 illustrates a charge mismatch cancellation method according to another exemplary embodiment;

(8) FIG. 6 illustrates an embodiment of a runtime calibration circuit according to another embodiment; and

(9) FIGS. 7A and 7B illustrate a conventional phase locked loop circuit and an exemplary timing diagram showing its operation.

DETAILED DESCRIPTION OF THE DRAWINGS

(10) The present invention relates to an improvement in phase locked loop circuits. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. As used herein, the terms coupled and connected are defined as follows. The term connected is used to describe a direct connection between two circuit elements, for example, by way of a metal line formed in accordance with normal integrated circuit fabrication techniques. In contrast, the term coupled is used to describe either a direct connection or an indirect connection between two circuit elements. For example, two coupled elements may be directly connected by way of a metal line, or indirectly connected by way of an intervening circuit element (e.g., a capacitor, resistor, inductor, or by way of the source/drain terminals of a transistor). Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

(11) FIG. 1 shows a phase locked loop (PLL) circuit 100 according to an exemplary generalized embodiment of the invention. Similar to conventional PLL 50 (see FIG. 7A), PLL 100 is fabricated as part of a larger integrated circuit (IC) device (not shown), and utilizes a PFD 104, a charge pump 108, a capacitive circuit (e.g., a loop filter) 114, a VCO 102, a loop divider 110 and optional level shifters 106 such that PLL circuit 100 generates an output signal frequency OUTF at a PLL output terminal 101O having an output phase F.sub.VCO that matches the input phase F.sub.INF of an input signal frequency INF applied to a PLL input terminal 101I.

(12) PFD 104 is configured using known techniques to generate at least one pump control voltage in response to a phase difference between said output phase F.sub.VCO and said input phase F.sub.INF. In the exemplary embodiment, PFD 104 generates pump control voltages V.sub.UP and V.sub.DOWN such that pump control voltages V.sub.UP and V.sub.DOWN have first voltage levels (values) when the output phase F.sub.VCO (as indicated by a corresponding feedback phase F.sub.FB) leads the input phase F.sub.INF, such that pump control voltages V.sub.UP and V.sub.DOWN have second values when the output phase lags the input phase, and such that pump control voltages V.sub.UP and V.sub.DOWN have third values when the output phase matches the input phase.

(13) Charge pump circuit 108 is configured to generate a pump output current I.sub.CP-OUT on a pump output terminal 108O in response to pump control voltages V.sub.UP and V.sub.DOWN such that, during normal operation, pump output current I.sub.CP-OUT consists either of a positive (UP) current component I.sub.UP, a negative (DOWN) current component I.sub.DOWN, or has no current level. The positive (UP) current component I.sub.UP is at least partially controlled by a (first) pull-up switch 109A that is either fully turned on or fully turned off by pump control voltage V.sub.UP, thereby selectively coupling pump output node 108O to a high voltage supply V.sub.DD. That is, when pump control voltage V.sub.UP has a first state (e.g., high), charge pump output current I.sub.CP-OUT includes an intrinsic positive (UP) current component I.sub.UP-INT having a first intrinsic magnitude determined by the characteristics (e.g., size) of pull-up switch 109A. Similarly, the negative (DOWN) current component I.sub.DOWN is at least partially controlled by a (first) pull-down switch 109B that is either fully turned on or fully turned off by pump control voltage V.sub.DOWN, thereby selectively coupling pump output node 108O to a low voltage supply (ground) such that, when pump control voltage V.sub.DOWN has a first state (e.g., high), charge pump output current I.sub.CP-OUT includes an intrinsic negative (DOWN) current component I.sub.DOWN-INT having a (second) intrinsic magnitude determined by the characteristics of pull-down switch 109A. During normal operation, when pump control voltages V.sub.UP and V.sub.DOWN have the first (leading) values, pull-up switch 109A is turned on and pull-down switch 109B is turned off, whereby charge pump 108 is controlled to generate output current I.sub.CP-OUT at a positive (charge increasing) current value corresponding at least to intrinsic positive (UP) current component I.sub.UP-INT passed through pull-up switch 109A. Conversely, when pump control voltages V.sub.UP and V.sub.DOWN have the second (lagging) values, pull-down switch 109B is turned on and pull-up switch 109A is turned off, whereby charge pump 108 is controlled to generate output current I.sub.CP-OUT at a negative (charge decreasing) current value corresponding at least to intrinsic negative (DOWN) current component I.sub.DOWN-INT passed through pull-down switch 109B. Finally, when both pump control voltages V.sub.UP and V.sub.DOWN have the third (e.g., low) values, both pull-up switch 109A and pull-down switch 109B are turned off, whereby charge pump 108 is controlled to generate pump output current I.sub.CP-OUT at a neutral (zero) current level.

(14) Charge pump 108 is further configured such that at least one of positive (UP) current component I.sub.UP and negative (DOWN) current component I.sub.DOWN includes both the associated intrinsic current component mentioned above, and also a bias current component that serves to adjust the associated intrinsic current component in order to equalize current components I.sub.UP and I.sub.DOWN. As depicted in FIG. 1, positive current component I.sub.UP is generated by combining both associated intrinsic positive current component I.sub.UP-INT and an optional positive bias current component I.sub.UP-BIAS that is passed through a (second) pull-up transistor 109C, which is controlled in the manner described below. Similarly, negative current component I.sub.DOWN is generated by combining both associated intrinsic negative current component I.sub.DOWN-INT and an optional negative bias current component I.sub.DOWN-BIAS that is passed through a (second) pull-down transistor 109D, which is controlled in the manner described below. In a presently preferred embodiment only one of current components I.sub.UP and I.sub.DOWN are modified by way of a corresponding bias current I.sub.UP-BIAS or I.sub.DOWN-BIAS and the other current component I.sub.UP and I.sub.DOWN includes only its corresponding intrinsic current component I.sub.UP-INT or I.sub.DOWN-INT. For example, in the specific embodiments described below, positive current component I.sub.UP includes both intrinsic positive current component I.sub.UP-INT and positive bias current I.sub.UP-BIAS, and negative current component I.sub.DOWN is made up entirely of negative intrinsic current component I.sub.DOWN-INT (i.e., negative bias current I.sub.DOWN-BIAS is zero). Those skilled in the art will recognize that this arrangement may be reversed (i.e., such that negative current component I.sub.DOWN comprises both intrinsic and bias current components, and positive current component I.sub.UP includes only intrinsic positive current component I.sub.UP-INT that the bias current may be utilized to reduce, instead of increase, the combined current components I.sub.UP and I.sub.DOWN (e.g., by way of connecting one or more of transistors 109C and 109D in series with switches 109A and 109B, respectively, and controlling transistors 109C and 109D to reduce the current passed through switches 109A and 109B). Accordingly, providing charge pump 108 with at least one of pull-up transistor 109C and pull-down transistor 109D facilitates adjusting the associated intrinsic current component in order to equalize current components I.sub.UP and I.sub.DOWN using the methods described below.

(15) Capacitive circuit (loop filter) 114 is connected to pump output terminal 108O, and is configured using known techniques to generate a charge (controlled voltage) V.sub.CONT at a level that is controlled by the time-varying composition of pump output current I.sub.CP-OUT. That is, controlled voltage V.sub.CONT is caused to increase to a higher voltage level when charge pump 108 is controlled by PFD 104 to generate pump output current I.sub.CP-OUT at positive current component I.sub.UP, and controlled voltage V.sub.CONT is caused to decrease to a lower voltage level when charge pump 108 is controlled by PFD 104 to generate pump output current I.sub.CP-OUT at negative current component I.sub.DOWN. Controlled voltage V.sub.CONT is therefore generated at a desired voltage level by way of controlling the amount of time pump output current I.sub.CP-OUT is at positive current component I.sub.UP versus the amount of time pump output current I.sub.CP-OUT is at negative current component I.sub.DOWN.

(16) VCO 102 has an input terminal connected to loop filter 114, and is configured according to known techniques to generate output signal frequency OUTF on PLL output circuit 101O such that its instantaneous output phase F.sub.VCO is adjusted in accordance with instantaneous corresponding value of controlled voltage V.sub.CONT.

(17) Loop divider 110 and optional level shifters 106 are connected in series between PLL output terminal 101O and PFD 104, and are configured using known techniques to function as a feedback circuit that generates feedback signal frequency F.sub.FB supplied to PFD 104 substantially as described above with reference to corresponding circuit elements utilized by conventional PLL 50.

(18) PLL circuit 100 also includes a charge pump control circuit 120 that is configured to determine a magnitude difference between intrinsic current components I.sub.UP-INT and I.sub.DOWN-INT, and to generate at least one bias control Signal V.sub.UP-BIAS and/or V.sub.DOWN-BIAS that controls charge pump 108 during subsequent normal PLL operations to generate positive current component I.sub.UP and negative current component I.sub.DOWN at equal magnitude levels. In the exemplary generalized embodiment, charge pump control circuit 120 includes an UP/DOWN (pump output current) measurement circuit 122 that determines the magnitude difference between intrinsic current components I.sub.UP-INT and I.sub.DOWN-INT by way of measuring a calibration controlled voltage V.sub.CONT-CAL generated on capacitive circuit 114 in response to pump output current I.sub.CP-OUT from the PLL's primary charge pump (i.e., charge pump 108) during a calibration period performed during power-up or reset of the IC (not shown) implementing PLL circuit 100. In an alternative embodiment described below with reference to FIG. 6, the calibration controlled voltage V.sub.CONT-CAL utilized by measurement circuit 122 is generated by a duplicate (secondary) calibration charge pump and calibration capacitive circuits. In either case, measurement circuit 122 implements one of the measurement methods described below (e.g., with reference to FIG. 2) to determine the magnitude difference between intrinsic current components I.sub.UP-INT and I.sub.DOWN-INT then generates a digital adjustment code DC having a digital/binary value (e.g., 101011) that corresponds to the measured difference, and then stores digital adjustment code DC in a memory circuit 125. In addition, charge pump control circuit 120 includes a bias voltage generator 127 (e.g., a digital-to-analog converter) that is configured to generate corresponding bias control signals V.sub.UP-BIAS and/or V.sub.DOWN-BIAS having corresponding voltage levels that vary directly with the digital value of digital adjustment signal DC), where bias voltage generator 127 is operably coupled to transmit bias control signals V.sub.UP-BIAS and/or V.sub.DOWN-BIAS to transistors 109C and 109D, respectively, of charge pump circuit 108 during subsequent normal PLL operation periods. In one embodiment charge pump control circuit generates an optional phase frequency detector control signal PFDC that is utilized to control PFD 104 such that both intrinsic current components I.sub.UP-INT and I.sub.DOWN-INT are applied to pump output terminal 108O during the calibration operating period. With this configuration, charge pump control circuit 120 causes charge pump circuit 108 to generate at least one of bias currents I.sub.UP-BIAS and/or I.sub.DOWN-BIAS in response to bias control signals V.sub.UP-BIAS and/or V.sub.DOWN-BIAS such that a corresponding bias current I.sub.UP-BIAS or I.sub.DOWN-BIAS is combined with one of intrinsic positive current components I.sub.UP-INT or I.sub.DOWN-INT to generate a combined current component I.sub.UP or I.sub.DOWN such that a combined magnitude of the combined current component (e.g., I.sub.UP) is equal to the magnitude of the other intrinsic current component (i.e., intrinsic negative current component I.sub.DOWN-INT), whereby current components I.sub.UP and I.sub.DOWN are generated at substantially equal magnitude levels during normal PLL operations.

(19) According to an aspect of the present invention, the measured difference between intrinsic UP (positive) current component I.sub.UP-INT and intrinsic DOWN (negative) current component I.sub.DOWN-INT is determined during a calibration operation period, for example, by way of controlling charge pump 108 to generate a time-varying calibration current I.sub.CP-OUT-CAL by simultaneously supplying intrinsic UP (positive) current component I.sub.UP-INT, intrinsic DOWN (negative) current component I.sub.DOWN-INT and an incrementally changing (e.g., gradually increasing) bias current (e.g., I.sub.UP-BIAS or I.sub.DOWN-BIAS) to pump output terminal 108O of charge pump 108, and monitoring changes in a calibration controlled voltage V.sub.CONT-CAL that is generated on loop filter 114 in response to time-varying calibration current I.sub.CP-OUT-CAL in order to detect when, e.g., a combined UP current component I.sub.UP formed by combining intrinsic UP (positive) current component I.sub.UP-INT and bias current I.sub.UP-BIAS matches intrinsic DOWN current component I.sub.DOWN-INT. As described below with reference to FIG. 2, an inflection point detection approach provides a simple and reliable method for determining the precise point at which the magnitudes of the adjusted UP current component matches the DOWN current component, e.g., by way of identifying when the measured controlled voltage V.sub.CONT stops decreasing and then begins to increase (i.e., at a corresponding inflection point). By correlating the detected inflection point with the amount of additional current applied to the UP current component at that point in time, the amount of additional current added to the UP current component (i.e., the amount by which the UP current component was adjusted to achieve an equal magnitude with the DOWN current component) can be accurately identified. Operation of charge pump 108 can then be adjusted, e.g., by generating digital adjustment code DC with a value corresponding to the measured additional current amount, and storing digital adjustment code DC in a memory circuit 125 such that the stored value is operably transferred to bias generator 127 such that a corresponding updated control signal V.sub.UP-BIAS is provided to the charge pump 108, whereby the on-state of pull-up PMOS transistor 109C is adjusted (increased) to provide the additional bias current amount I.sub.UP-BIAS. As indicated in FIG. 1, bias current amount I.sub.UP-BIAS which is added to (combined with) intrinsic UP current component I.sub.UP-INT, thereby providing a combined (adjusted) positive current component I.sub.UP to the pump's output terminal that has the same magnitude as negative current component I.sub.DOWN during subsequent normal PLL operations (i.e., in this case bias current component I.sub.DOWN-BIAS is zero). In an alternative embodiment, a negative bias current component I.sub.DOWN-BIAS may be calculated using the method described above such that combined (adjusted) negative current component I.sub.DOWN has the same magnitude as intrinsic positive current component I.sub.UP-INT during subsequent normal PLL operations (i.e., in this case bias current component I.sub.UP-BIAS is zero). As set forth in the alternative specific embodiments set forth below, various circuits and methods may be used to detect the inflection point, calculate the required current adjustment amount, and generate the digital adjustment code.

(20) FIG. 2 includes exemplary charge and current graphs illustrating a calibration process utilizing the inflection point approach (mentioned above), and FIG. 2A illustrates a modified charge pump 108A during the calibration process. For brevity, modified charge pump 108A includes only one bias current transistor (i.e., pull-up transistor 109C) utilized to generate an increasing time-varying bias current amount I.sub.UP-BIAS-TX that is combined with intrinsic positive current component I.sub.UP-INT. For explanatory purposes pull-up transistor 109C is shown as being connected in parallel with pull-up switch 109A, but it is understood that other configurations (e.g., series connection) may also be utilized. Referring to the lower portion of FIG. 2, the present example assumes that the magnitude of intrinsic UP current component I.sub.UP-INT (i.e., [I.sub.UP-INT]) is lower than the magnitude of intrinsic DOWN current component I.sub.DOWN-INT (i.e., [I.sub.DOWN-INT]). Specifically, in the illustrated example, intrinsic UP current component I.sub.UP-INT has a magnitude of 3.0 A, which is generated through pull-up switch 109A in response to assertion of pump control voltage V.sub.UP, and intrinsic DOWN current component I.sub.DOWN-INT has a magnitude of 3.5 A, which is generated through pull-down switch 109B in response to assertion of pump control voltage V.sub.DOWN.

(21) Referring to FIG. 2A, at the beginning of the calibration process charge pump 108A is controlled to simultaneously supply both intrinsic UP current component I.sub.UP-INTand intrinsic DOWN current component I.sub.DOWN-INT to a capacitive circuit (not shown) by way of asserting both pump control voltage V.sub.UP and V.sub.DOWN, thereby generating a calibration controlled voltage V.sub.CONT-CAL(TX) on pump output terminal 1080, where the suffix TX indicates that calibration controlled voltage V.sub.CONT-CAL varies with time T. As set forth above and illustrated in FIG. 2, the calibration controlled voltage V.sub.CONT-CAL(T0) generated by combining intrinsic current components I.sub.UP-INT and I.sub.DOWN-INT at the beginning of the calibration process (i.e., when bias current I.sub.UP-BIAS(TX) is zero) has a relatively high initial voltage level (e.g., approximately 200 millivolts) due to the larger magnitude of negative current component I.sub.DOWN-INT. In one embodiment, the calibration process is initiated after a phase lock signal is generated indicating that phases of the PLL input and output signals are matched, whereby the initial value of V.sub.CONT-CAL(T0) is at a balance point.

(22) Referring to the lower portion of FIG. 2, bias current I.sub.UP-BIAS-TX is gradually increased by a small amount each half nanosecond (i.e., by gradually changing bias voltage V.sub.UP-BIAS-TX such that bias current I.sub.UP-BIAS-TX passed through pull-up transistor 109C increases incrementally as indicated). As indicated in FIG. 2A, combined calibration UP current I.sub.UP-CAL is formed by time-varying bias current I.sub.UP-BIAS-TX combined with (added to) positive intrinsic current component I.sub.UP-INT, and therefore gradually increases during the calibration process. In contrast, the only DOWN current generated by charge pump circuit 108A is intrinsic negative current component I.sub.DOWN-INT which remains fixed (unchanged) during the calibration process. Referring to the upper portion of FIG. 2, because the magnitude of intrinsic current component I.sub.UP-INT is initially significantly lower than the magnitude of intrinsic DOWN current magnitude (i.e., at time T0), and because the magnitude difference between the intrinsic current components is maximum at time T0, calibration controlled voltage V.sub.CONT-INT is initially pulled lower by a relatively large amount, as indicated by the downward sloping portion of voltage curve 200 shown in the upper-left portion of FIG. 2. As calibration UP current I.sub.UP-CAL is incrementally increased over time (i.e., as indicated in the lower portion of FIG. 2), the difference between the magnitudes of calibration UP current I.sub.UP-CAL and intrinsic DOWN current component I.sub.DOWN-INT decreases, but while the magnitude of intrinsic DOWN current component remains larger than calibration UP current I.sub.UP-CAL, the value of calibration controlled voltage V.sub.CONT-CAL, continues to decrease. Eventually, as indicated at time 7.5 in FIG. 2, when bias current I.sub.UP-BIAS-T7.5 has increased to 0.5 A, calibration UP current I.sub.UP-CAL becomes equal to intrinsic DOWN current component I.sub.DOWN-INT, whereby V.sub.CONT-CAL stops decreasing (i.e., at inflection point 202). Subsequently, as the UP current component continues to incrementally increase above the magnitude of the DOWN current component due to the continued incremental increase of bias current I.sub.UP-BIAS-TX, calibration controlled voltage V.sub.CONT-CAL begins to increase, as indicated by the upward sloping portion of the curve shown in the upper-right portion of FIG. 2. Calibration controlled voltage V.sub.CONT-CAL thus evolves according to the example time-voltage curve 200.

(23) In exemplary embodiments provided herein, the improved phase locked loop circuits of the present invention adjust one of the UP or DOWN current components by way of performing the calibration process described above and detecting inflection point 202 in the resulting time-voltage curve 200, utilizing the inflection point data to determine the total current adjustment amount (e.g., amount 215 shown in the lower portion of FIG. 2) by which the magnitude of the UP current component was increased in order to match the magnitude of the negative DOWN current component, and then adjusting one or both of the UP or DOWN current components generated by charge pump 108A during subsequent normal operation. That is, FIG. 2B depicts the operating state of charge pump circuit 108A during subsequent normal operation time period NO1 when pump control voltages V.sub.UP and V.sub.DOWN have the first (leading) values, whereby pull-up switch 109A is turned on and pull-down switch 109B is turned off. In this case, charge pump output current I.sub.CP-OUT is equal to the UP current I.sub.UP, which is a combination of that intrinsic UP current component I.sub.UP-INT and by bias current I.sub.UP-BIAS-DC, where bias current I.sub.UP-BIAS-DC is equal to determined current adjustment amount 215 (see FIG. 2), and is generated by way of turning on pull-up transistor 109C using pump bias voltage V.sub.UP-BIAS-DC whose voltage level is determined by a stored digital adjustment code corresponding to the determined current adjustment amount 215. In contrast, FIG. 2C depicts the operating state of charge pump circuit 108A during normal operation time period NO2 when pump control voltages V.sub.UP and V.sub.DOWN have the second (lagging) values, whereby pull-up switch 109A is turned off and pull-down switch 109B is turned on. In this case, charge pump output current I.sub.CP-OUT is equal to the intrinsic DOWN current component I.sub.DOWN-INT. There are generally two techniques by which the inflection point 202 may be determined, as described in conjunction with FIG. 4 and FIG. 5.

(24) FIG. 3 illustrates an enhanced PLL circuit 100B according to an exemplary practical embodiment of the invention that performs the above-mentioned calibration process during a power-up/reset period (i.e., before normal PLL operations). Portions of PLL circuit 100B that perform similar functions to those performed by portions of PLL circuit 100 (described above) are identified with similar reference numbers, and are understood to function substantially as described above unless stated otherwise below.

(25) Phase frequency detector (PDF) 104B is configured to generate at least one pump control voltage V.sub.UP/DOWN in response to a phase difference between a feedback (output) clock signal ck_fb and an input clock signal ck_in during normal PLL operations.

(26) Charge pump circuit 108B is configured using the techniques described above to generate an output current according to the PLL operating mode. During normal PLL operations, charge pump circuit 108B generates pump output current I.sub.CP-OUT including either an UP (positive) current component or a DOWN (negative) current component in response to pump control voltage V.sub.UP/DOWN, where the UP (positive) current component is adjusted by way of an applied fixed bias signal V.sub.BIAS in the manner described above. During calibration operations charge pump circuit 108B generates pump output current I.sub.CP-OUT-CAL including both intrinsic UP (positive) and DOWN (negative) current components along with a time-varying bias current component generated in accordance with a time-varying bias signal V.sub.BIAS-CAL in the manner described above with reference to FIG. 2.

(27) Capacitive circuit 114A is coupled to the output terminal of charge pump 108B and includes a loop resistor Rloop, a loop capacitor Cloop and a small capacitor Csmall that are configured to generate controlled voltages V.sub.CONT or V.sub.CONT-CAL in response to pump output currents I.sub.CP-OUT or I.sub.CP-OUT-CAL, respectively.

(28) Charge pump control circuit 120B includes an UP/DOWN difference measurement circuit (UP/DOWN DMC) 122B configured to determine a magnitude difference between intrinsic UP (positive) and DOWN (negative) current components of pump output current I.sub.CP-OUT-CAL generated by charge pump 108B during calibration operations, and to store a digital adjustment code value DC (e.g., binary 100111) in a memory circuit 125B. In one embodiment, measurement circuit 122B includes an envelope detector 314 coupled to capacitive circuit 114B and configured to generate an envelope signal V.sub.CONT-ENV based on calibration controlled voltage V.sub.CONT-CAL, and a comparator 310 configured to compare envelope signal V.sub.CONT-ENV with calibration controlled voltage V.sub.CONT-CAL. In cases where the Csmall capacitor is relatively large, every step increase in the bias current may produce such a small step increase in calibration controlled voltage V.sub.CONT-CAL that these step increases can be overlooked by comparator 310 due to it's own input offset voltage. In such cases, an optional amplifier 308 is connected between capacitive circuit 114B and comparator 310 to supply amplified controlled voltage V.sub.CONT-AMP to comparator 310 so that comparator 310 reliably triggers, thereby facilitating reliable detection of an inflection point using amplified controlled voltage V.sub.CONT.sub._.sub.AMP from amplifier 308. In one embodiment, PLL circuit 100B includes a lock circuit 312 provides a frequency lock signal having a first value (FLOCK=1) when output phase F.sub.VCO of PLL output signal OUTF matches input phase F.sub.INF of applied input signal ck_in, and difference measurement circuit 122B further comprises a counter circuit 316 that is configured to generate a count value that increments in accordance with changes in the current level of the time-varying bias current, where digital adjustment code value DC based the count value accrued on counter circuit 316 during a calibration operation period in the manner described below.

(29) Charge pump control circuit 120B also includes a digital-to-analog converter (DAC) circuit (bias generator) 122B that is configured either to generate bias control signal V.sub.BIAS during normal PLL operations, where bias control signal V.sub.BIAS is generated in accordance with the stored digital adjustment code value DC, or to generate time varying bias control signal V.sub.BIAS(TX) during calibration operations such that bias current I.sub.UP-BIAS is generated by charge pump 108B in the manner described above with reference to FIG. 2.

(30) In one embodiment, enhanced PLL circuit 100B detects an inflection point of a time-voltage curve generated in the manner described above with reference to FIG. 2 by continuously scanning (e.g., from a lowest to a highest value) the UP (positive) current component generated by charge pump 108B. When circuit effects causing mismatch in the charge pump 108B have cancelled one other at a particular value of the UP current component, the enhanced phase locked loop circuit 100B reaches an inflection point (e.g., inflection point 202 in FIG. 2). The value of the UP current component corresponding to the inflection point is stored in the form of digital code DC that is then utilized to adjust the operation of charge pump 108B in order to minimize mismatches between the positive/negative current components generated in the charge pump 108B. The extent to which the positive/negative current component mismatch may be reduced is dependent upon the resolution of the digital to analog converter 127B. For example, to achieve an approximately 1% mismatch level (e.g., 0.8-1.2%) in the charge pump 108B, a 6-bit resolution digital to analog converter 127B may be utilized. A greater reduction in the mismatch results in a lower noise floor for the enhanced phase locked loop circuit 100B, which consequently reduces the integrated jitter. Reducing the mismatch also reduces the static phase error and reference spur level of the enhanced phase locked loop circuit 100B.

(31) In one embodiment charge pump 108B is designed with an intrinsic skew, whereby the magnitude of one of the intrinsic DOWN current component or UP current component is naturally higher than the magnitude of the other current component (e.g., referring to FIG. 1, pull-up transistor 109A and pull-down transistor 109B are intentionally fabricated such that the magnitude of intrinsic current component I.sub.UP-INT is greater than the magnitude of intrinsic current component I.sub.DOWN-INT). During operation enhanced PLL circuit 100B is first allowed to establish a frequency lock. Frequency lock (state FLOCK=1) is established when the input clock and the feedback clock, which are respectively transmitted on PFD input terminals 104B1 and 104B2, are aligned to a preconfigured tolerance. Subsequent to state FLOCK=1, logic circuit 107B transmits input clock ck_in onto level shifter input terminal 106B1 such that both input terminals 104B1 and 104B2 to phase frequency detector 104B receive input clock ck_in. Counter circuit 316 begins counting up from zero, and DAC 127B incrementally increases the UP bias current by way of increasing calibration control voltage V.sub.BIAS-CAL. Due to the intrinsic skew of charge pump 108B, the (second) magnitude of the DOWN current component is initially higher than the (first) magnitude of the UP current component, whereby the output current generated by charge pump 108B is negative during the initial operation period, and remains negative while the UP current component is increased uniformly with every cycle of the input clock so long as the magnitude of the DOWN current component is larger than the magnitude of the UP current (e.g., in the manner depicted by the decreasing slope of time-voltage curve 200 in the upper left portion of FIG. 2). However, the increasing UP current component causes the time-voltage curve 200 to flatten out, and then to begin increasing (e.g., in the manner depicted by the increasing slope of time-voltage curve 200 in the upper right portion of FIG. 2). The inflection point 202 where the time-voltage curve 200 flattens out is the balanced state at which the mismatch between the UP and DOWN current components is fully eliminated. Due to the symmetric nature of the time-voltage curve 200, the count value (code value) will be twice the code corresponding to the maximum available reduction in mismatch between the UP and DOWN current components. The technique of connecting both inputs 104B1 and 104B2 of PFD 104B to the same clock signal (i.e., input clock ck_in) for a period of time during the calibration process has the advantage of cancelling the PFD delay mismatches in the UP and DOWN current path indirectly, and also serves to remove mismatches in the inherent UP and DOWN current components generated by charge pump 108B in the manner described above. Also it is this technique that makes the perfect alignment of ck_in and ck_fb possible that can be used in some de-skew PLLs.

(32) As mentioned above, FIGS. 4 and 5 are flow diagrams that respectively illustrate two techniques by which the inflection point 202 (FIG. 2) may be determined.

(33) FIG. 4 illustrates a first method 400 that utilizes envelope detector 314 and comparator 310 (both shown in FIG. 3) to detect the inflection point during the calibration process. The envelope detector 314, (optionally) the amplifier 308, and the comparator 310 are coupled to controlled voltage V.sub.CONT (block 402, block 404, and block 406 respectively). In one embodiment the comparator 310 has an offset of 10 mV. Counter circuit 316 starts counting at the beginning of the calibration process, and increments its count value each time bias signal V.sub.BIAS incrementally increases the bias current applied to charge pump 108B. When V.sub.CONT (or V.sub.CONT.sub._.sub.AMP) is detected to deviate from V.sub.CONT.sub._.sub.ENV (e.g., using comparator 310), counter 316 is stopped, and the final digital count value is stored as the digital converter code value DC, which is then passed to digital-to-analog converter (DAC) 127B (block 408). Digital converter code value DC, which is proportional to the required current offset amount needed to eliminate mismatches between the UP and DOWN current components, is then utilized to control charge pump circuit 108B in the manner described above.

(34) Another embodiment of a charge mismatch cancellation method 500 to operate the enhanced phase locked loop circuit 100B is illustrated in FIG. 5. In this case, lock circuit 312 (see FIG. 3) is utilized to generate a frequency lock signal having a first value (FLOCK=1) when the phase F.sub.VCO of PLL output signal OUTF matches the input phase F.sub.INF of the applied input signal. During the calibration process, V.sub.CONT (or V.sub.CONT.sub._.sub.AMP) is sampled until locked state FLOCK=1 is reached (block 502). When FLOCK=1 is reached, incrementing of the digital code value by counter 316 begins (block 504). V.sub.CONT or V.sub.CONT.sub._.sub.AMP will decrease and then increase again as described above with reference to FIG. 2. Comparator 310 (e.g., with 10 mV offset) is utilized to compare V.sub.CONT or V.sub.CONT.sub._.sub.AMP with V.sub.CONT.sub._.sub.SAM (sample value) (block 506). When the output of the comparator 310 goes high, counter 316 is stopped, and one-half of the final digital code count is stored as the digital converter code value, which is then applied to set the value of the UP current component to cancel the mismatch between UP and DOWN current components generated by the charge pump (block 508).

(35) FIG. 6 shows a partial enhanced PLL circuit 100C that includes a primary charge pump and associated circuitry such as that shown in FIG. 1, and a charge pump control circuit 120C configured to achieve runtime calibration of a primary charge pump (e.g., charge pump 108 in FIG. 1) to account for variations between current components I.sub.UP and I.sub.DOWN during normal PLL operations (e.g., due to ambient temperature changes or circuit aging). To perform runtime calibration, charge pump control circuit 120C includes a (second) calibration phase frequency detector 604, a secondary calibration charge pump 608, a calibration capacitive circuit 614 and a calibration bias control circuit 627 that are configured to operate substantially identically to their corresponding primary components. That is, calibration charge pump 608 is configured to generate to generate a calibration pump output current I.sub.CP-OUT-CAL on a calibration pump output terminal 6080 such that calibration pump output current I.sub.CP-OUT-CAL includes duplicate intrinsic positive (UP) and negative (DOWN) current components that are substantially identical to those generated by the primary charge pump circuit, calibration charge pump 608 is controlled (e.g., by way of pump control signal V.sub.UP/DOWN) to output a combination of the duplicate intrinsic positive and negative current components and a time-varying bias current (which is generated in accordance with bias control signal V.sub.BIAS(TX)) during each calibration process. In one embodiment, the charge pump control circuit performs one of the charge pump mismatch cancellation techniques previously described (e.g., in FIG. 4 or FIG. 5). Once calibration is completed, a digital adjustment code DC corresponding to the measured magnitude difference that is generated by UP/DOWN measurement circuit 122 is then stored in memory circuit 125, and the digital adjustment code DC is then passed to bias generator 127 (described above) for control of the primary charge pump circuit (not shown) to cancel mismatches in the manner described above. The runtime calibration may be timed to repeat on a cycle at a set frequency, for example every 100 cycles of the PLL input clock. After each calibration cycle, V.sub.CONT.sub._.sub.CAL is reinitialized to V.sub.CONT and the digital code DC changed to cancel charge pump mismatches.

(36) Although the present invention has been described with respect to certain specific embodiments, it will be clear to those skilled in the art that the inventive features of the present invention are applicable to other embodiments as well, all of which are intended to fall within the scope of the present invention.