METHOD AND DEVICE FOR SELF-BIASED AND SELF-REGULATED COMMON-MODE AMPLIFICATION

Abstract

An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.

Claims

1. A method of common-mode biasing of an output terminal of an amplification stage that comprises a transconductance amplification transistor, the method comprising: biasing the output terminal to a bias potential that is based on a gate-source voltage present between a gate and a source of the amplification transistor and on a compensation of parasitic variations of the gate-source voltage.

2. The method according to claim 1, wherein the compensation is based on a compensation current flowing in a resistor connected between the gate of the amplification transistor and the output terminal, the compensation current generating a compensation voltage across terminals of the resistor.

3. The method according to claim 1, wherein the amplification stage comprises a first cascoded amplification arrangement that comprises the amplification transistor and a second cascoded amplification arrangement in series and sharing the output terminal with a controlled common mode, the second cascoded amplification arrangement having transistors of a conductivity type opposite to a conductivity type of transistors of the first cascoded amplification arrangement, the method further comprising regulating a static current flowing in the first and second cascoded amplification arrangements.

4. An amplification device comprising: an amplification stage having a transconductance amplification transistor and an output terminal; and a biasing circuit configured to bias, in common mode, the output terminal to a bias potential based on a gate-source voltage present between a gate and a source of the amplification transistor, the gate-source voltage being compensated for parasitic variations.

5. The device according to claim 4, wherein the biasing circuit is configured to pass a compensation current through a first resistor connected between the gate of the amplification transistor and the output terminal, the voltage generated across terminals of the first resistor being intended to compensate the parasitic variations.

6. The device according to claim 5, wherein the biasing circuit comprises a compensation transistor paired with the amplification transistor of the compensation transistor being connected to a terminal intended to receive a fixed control voltage, and being configured to generate the compensation current at a drain thereof.

7. The device according to claim 6, wherein the biasing circuit comprises a second resistor connected between a source of the compensation transistor and the source of the amplification transistor.

8. The device according to claim 7, wherein the amplification stage comprises a third resistor connected between a supply terminal intended to receive a supply voltage and the source of the amplification transistor.

9. The device according to claim 6, wherein the biasing circuit comprises a current generator connected between the drain of the compensation transistor and a terminal intended to receive a reference voltage, the current generator configured to subtract an adjustment current from the compensation current.

10. The device according to claim 4, wherein the amplification stage comprises a resistor connected between a supply terminal intended to receive a supply voltage and the source of the amplification transistor.

11. The device according to claim 4, wherein the amplification stage comprises a first input on the gate of the amplification transistor and coupled to an input terminal by a filtering capacitor that is configured to behave as a short-circuit at an operating frequency of the amplification stage and as a circuit breaker at an operating frequency of the biasing circuit.

12. The device according to claim 11, further comprising a current-feedback-control loop configured to regulate a current flowing in the amplification stage.

13. A radio frequency communication system comprising a reception stage that includes an antenna input, the reception stage comprising an amplification device according to claim 4 configured to amplify a reception signal, and a signal processor configured to process the amplified reception signal.

14. The system according to claim 13, further comprising an antenna coupled to the antenna input of the reception stage.

15. The system according to claim 14, wherein the radio frequency communication system is part of a personal computer.

16. The system according to claim 14, wherein the radio frequency communication system is part of a mobile telephone.

17. An amplification device comprising: a reference voltage terminal; an output terminal; a transconductance amplification transistor having a current path between the reference voltage terminal and the output terminal; a resistor coupled between a gate of the amplification transistor and the output terminal; and a compensation transistor having a current path coupled between the reference voltage terminal and a node that is connected to both the gate of the amplification transistor and a terminal of the resistor.

18. The device according to claim 17, wherein a gate of the compensation transistor is coupled to a fixed control voltage terminal.

19. The device according to claim 17, further comprising a second resistor coupled between a source of the compensation transistor and the source of the amplification transistor.

20. The device according to claim 19, further comprising a third resistor connected between the reference voltage terminal and the source of the amplification transistor.

21. The device according to claim 17, further comprising a current generator having a current path coupled between a drain of the compensation transistor and ground terminal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0052] other advantages and characteristics of the invention will become apparent on examining the detailed description of wholly non-limiting embodiments and appended drawings in which:

[0053] FIGS. 1 and 2, previously described, represent examples of radio frequency amplifiers of the prior art;

[0054] FIGS. 3 to 7 represent various embodiments and modes of implementation of the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0055] FIG. 3 represents an exemplary amplification device AMP comprising a first cascoded amplification arrangement 101 and a common-mode biasing open loop MC, otherwise called a biasing circuit.

[0056] In this example, the first cascoded amplification arrangement 101 is included in a radio frequency signal transconductance amplification stage TRSC.

[0057] The amplification stage TRSC furthermore comprises a second cascoded amplification arrangement 111 connected by the output 120 to the first cascoded amplification arrangement 101.

[0058] The second cascoded amplification arrangement 111 comprises a transconductance amplification transistor of N-MOS type 113 and a cascode transistor of N-MOS type 115 connected in series between the output terminal 120 and a terminal intended to receive a reference voltage GND, for example, the ground.

[0059] The amplification device AMP also comprises a static-current feedback control closed loop BCLI, which can be of similar structure to that described in conjunction with FIG. 1 and is not represented nor described again here and hereinafter.

[0060] The first cascoded amplification arrangement 101 comprises a transconductance amplification transistor 103 of P-MOS type and a cascode transistor 105 of P-MOS type.

[0061] The amplification transistor 103 is connected on its source to a supply terminal intended to receive a supply voltage VDD by way of a resistor 109, and on its drain to the source of the cascode transistor 105 whose drain is connected to the output terminal 120.

[0062] The amplification transistor 103 is controlled on its gate by an input signal carried by the voltage present on an input terminal 122 and its function is to amplify this input signal in terms of dynamic current on the output terminal 120.

[0063] The gate of the amplification transistor 103 is coupled to the input terminal 122 by way of a capacitor 124 configured to behave as a short-circuit at the operating frequencies of the cascoded amplification arrangements 101 and 111, i.e., the frequencies of the signals received on the input terminal 122, and as a circuit breaker at the operating frequency of the common-mode biasing open loop MC.

[0064] Likewise, the gate of the amplification transistor 113 is coupled to the input terminal 122 by way of a capacitor 126 configured to behave as a short-circuit at the operating frequencies of the cascoded amplification arrangements 101 and 111, i.e. the frequencies of the signals received on the input terminal 122, and as a circuit breaker at the operating frequency of the static-current feedback control closed loop BCLI.

[0065] Cascode reference voltages Vref are applied to the gates of the cascode transistors 105 and 115 in a conventional manner known per se.

[0066] The transconductance amplification stage TRSC comprises a resistor 109 (of value R2), connected between a supply voltage terminal VDD and the amplification transistor 103, making it possible to perform the measurement of the static current which passes through the cascoded amplification arrangements 101, 111, and to control it by feedback with respect to a desired current, proportional to Iref (131) by means, for example, of a current-feedback-control loop BLCI.

[0067] The common-mode biasing circuit MC comprises a biasing circuit comprising a first resistor 151 (of value R). A first terminal of the first resistor 151 is connected to the gate of the amplification transistor 103 and the other terminal of the first resistor 151 is connected to the output terminal 120.

[0068] The common-mode biasing circuit MC furthermore comprises a compensation transistor 153, of P-MOS type, whose drain is connected to the first terminal of the resistor 151 (and therefore also to the gate of the amplification transistor 103). The compensation transistor 153 is connected on its gate to a control terminal 155 intended to receive a constant control voltage (Vcom).

[0069] The biasing circuit MC also comprises a resistor 157 (of value R1), connected on the one hand to the source of the compensation transistor 153 and on the other hand to a node A situated between the resistor 109 and the source of the amplification transistor 103.

[0070] The resistor 157 and the compensation transistor 153 together form a compensation current source I.

[0071] The compensation transistor 153 and amplification transistor 103 are paired, that is to say that they are produced in the course of the same fabrication method, so as to have the same characteristics, to within a size factor.

[0072] More precisely, the compensation transistor 153 and amplification transistor 103 have notably the same characteristic constant kp, the same threshold voltage Vth, an active region of one and the same length L, but of a different width W. This difference of width W influences the resistivity of the transistor and consequently the quantity of current passing between its conduction terminals.

[0073] The above-mentioned size factor is equal to the ratio of the widths of the active regions of the two transistors.

[0074] The variation of the width W is customarily obtained by producing a plurality of unitary transistors having strictly the same characteristics, linked in parallel. The size factor is thus equal to the number of unitary transistors connected in parallel.

[0075] In particular, the paired compensation transistor 153 and amplification transistor 103 manifest the same parasitic variations notably due to temperature.

[0076] FIG. 4 represents the amplification device AMP described in conjunction with FIG. 3 in the operating state, and illustrates voltages and currents involved during implementation of the device AMP.

[0077] During operation, the resistor 109 controls the static current I.sub.103 through the amplification stage TRSC, which adds thereto the input-signal variations amplified in terms of current.

[0078] The voltage V.sub.A of the node A can be expressed, by way of the compensation transistor 153, V.sub.A=VcomVGS.sub.153+R1*I [eq1], with I the compensation current in the resistor 157, in the conduction terminals of the compensation transistor 153 and in the resistor 151, and with VGS.sub.153 the voltage present between the gate and the source of the compensation transistor 153.

[0079] The reference eq1 designates the path traversed to define equation [eq1], represented in bold in FIG. 4.

[0080] The bias voltage V.sub.MC of the output terminal can be expressed, with VGS.sub.103 the voltage present between the gate and the source of the amplification transistor 103, by the following equation ([eq2]):

V.sub.MC=V.sub.A+VGS.sub.103R*I,i.e., by inserting [eq1],

V.sub.MC=VcomVGS.sub.153+R1*I+VGS.sub.103R*I, i.e.

V.sub.MC=VcomVGS.sub.153+VGS.sub.103+I*(R1R)[eq2]

[0081] Likewise, the reference eq2 designates the path traversed to define equation [eq2], represented in bold in FIG. 4.

[0082] Moreover, with the acceptable approximation that I.sub.103>>I, I.sub.103 representing the current passing through the amplification transistor 103,

V.sub.MC=VDDR2*I.sub.103+VGS.sub.103R*I[eq3]

[0083] Likewise, the references eq3 designate the path traversed to define equation [eq3], represented in bold in FIG. 4.

[0084] Through V.sub.MC=[eq2]*R/R1+[eq3]*(R1R)/R1, we obtain:

V.sub.Mc=VDD*(R1R)/R1+Vcom*R/R1I.sub.103*R2*(R1R)/R1+VGS.sub.103VGS.sub.153*R/R1[eq4]

[0085] If the areas of the transistors 153 and 103 are in the same ratio as the ratio of the currents passing through them, then VGS.sub.153=VGS.sub.103 and if we take R=R1, the equation simplifies thus: V.sub.MC=Vcom.

[0086] Equation [eq4] shows that with an appropriate adjustment of the form factor of the compensation transistor 153, the variations of the value VGS.sub.153 can compensate the variations of VGS.sub.103 on the biasing of the output terminal 120.

[0087] For example, the width of the compensation transistor 153 can be 8 times smaller than the width of the amplification transistor 103.

[0088] Thus, the biasing of the common mode is applied directly on the output terminal, without calling upon a modification of the static current flowing in the cascoded amplification arrangements that might disturb the feedback control of this current by the feedback control closed loop BCLI.

[0089] Furthermore, the compensation transistor 153 and amplification transistor 103 being paired, random variations such as variations due to temperature are self-regulated.

[0090] In other words, a biasing of the output terminal 120 to a bias potential V.sub.MC obtained on the basis of the gate-source voltage VGS.sub.103 present between the gate and the source of the amplification transistor 103 has been implemented. This biasing is furthermore self-regulated, that is to say that parasitic variations present between the gate and the source of the amplification transistor 103 are compensated by the same parasitic variations present on the compensation transistor 153.

[0091] More precisely, the compensation is implemented notably by virtue of the flow of the compensation current I in the first resistor 151, and generating a voltage R*I across its terminals comprising variations which compensate the parasitic variations of the voltage VGS.sub.103.

[0092] This implementation of a biasing of the output terminal does not disturb the static current in the transconductance amplification stage TRSC, thus it is thus advantageously possible to effectively combine a closed-loop feedback control of the static current in a customary manner, for example, such as described in conjunction with FIG. 1, with this method for biasing the output terminal.

[0093] FIG. 5 represents another advantageous embodiment of the amplification device AMP. The elements common to this embodiment and to that described in conjunction with FIG. 3 bear the same references and are not detailed again here.

[0094] In this embodiment, the common-mode biasing open loop MC furthermore comprises a current generator 159 drawing a current I.sub.159 on a node situated between the drain of the compensation transistor 153 and the first resistor 151 (that is to say on the node to which the gate of the amplification transistor 103 is also connected).

[0095] This makes it possible to pass a larger current I through the compensation transistor 153, without increasing the compensation current (I-I.sub.159) passing through the first resistor 151, and therefore without increasing the compensation voltage across its terminals.

[0096] Thus, in this embodiment it is possible to employ a bigger compensation transistor (therefore exhibiting less dispersed characteristics), passing a larger and more precise current than when the size factor has to be fixed in order to balance equation eq3.

[0097] Moreover, this generator 159 can make it possible to reverse the direction of the current flowing in the first resistor 151 and thus to introduce a compensation voltage of opposite sign across the terminals of the first resistor 151.

[0098] Indeed, by adding the current source 159, the size of the transistor 153 can be increased so as to improve the precision of the common-mode voltage on the output 120. On the other hand, increasing the size of the transistor 153 increases its parasitic output capacitance, and as a consequence the capacitance on the input 122 of the amplifier TRSC.

[0099] Thus, an isolation resistor 152 is connected between the source of the compensation transistor 153 and the gate of the amplification transistor 103. The isolation resistor 152 exhibits a large resistive value so as to mask the parasitic capacitance which exists on the drain of the transistor 153.

[0100] Adding the isolation resistor 152 makes it possible to isolate the input 122 in relation to the output capacitance of the transistor 153. This resistor being not traversed by any static current (since it is connected to the gate of the transistor 103), no voltage drop occurs across its terminals: it does not therefore play any role in equation [eq4]. Its value can be chosen arbitrarily, and preferably so as to be much greater (for example, by an order of magnitude) than the output impedance of the transistor 153, at the working frequency.

[0101] FIG. 6 represents an exemplary radio frequency communication system SYS, comprising an antenna ANT and a reception stage RX connected to the antenna by way of a transformer TR.

[0102] The reception stage RX conventionally comprises a low noise amplifier LNA, transmitting the signal received by the antenna ANT to a symmetric-asymmetric transformer BLN (balun according to the usual term).

[0103] On output from the balun transformer BLN, the signal is in differential mode, and each differential circuit comprises an amplification device AMP1, AMP2, AMP3, AMP4 of the type of the devices described in conjunction with FIGS. 3 to 5.

[0104] The reception stage RX is thus configured to amplify a reception signal by means of the amplification devices AMP1, AMP2, AMP3, AMP4, having a controlled common output mode.

[0105] Mixers MIX carry out a frequency transposition with a signal generated by a local oscillator LO, before processing by radio frequency signal processor MTS, for example, implemented digitally.

[0106] FIG. 7 represents an exemplary electronic apparatus APP equipped with an embodiment of a radio frequency communication system SYS such as detailed previously, here a mobile telephone. It will be apparent to the person skilled in the art that the embodiments of a radio frequency communication system SYS or of an amplification device AMP such as detailed previously can be included with any other type of apparatus or other known system not described here.

[0107] Moreover, the invention is not limited to the embodiments which have been described hereinabove but embraces all variants thereof, for example, the static-current feedback control loop described previously has been given by way of example, as has the cascode amplification arrangement or the radio frequency system.