METHOD OF SWITCHING ON AND OFF A POWER AMPLIFIER, RELATED POWER AMPLIFIER CIRCUIT, SYSTEM AND COMPUTER PROGRAM PRODUCT

Abstract

Systems and methods for switching on and off a power amplifier including a signal input receiving an input signal and a signal output providing an output signal. The power amplifier includes a control input receiving a gain control signal indicating a requested gain and a control input receiving a mute control signal indicating whether the signal output should be switched on or switched off. A control unit determines whether the signal output of the power amplifier should be switched on and/or off, and if switched on receives data identifying a switch-on ramp and if switched off receives data identifying a switch-off ramp. The control unit generates the mute control signal to switch on the signal output of the power amplifier on or off, and generates the gain control signal as a function of the data identifying the switch-on or switch-off ramp to thereby increase or decrease the gain control signal.

Claims

1. A method of switching on and off a power amplifier, the power amplifier, comprising: generating a mute control signal indicating whether an output signal of the power amplifier should be switched on or switched off; generating a gain control signal having a value that determines a gain of the power amplifier; generating the output signal by amplifying said input signal as a function of said gain control signal to generate the output signal based on switch-on ramp data responsive to the mute control signal indicating the power amplifier should be switched on, the switch-on ramp data increasing the gain control signal from a first gain value to a second gain value greater than the first gain value; and generating the output signal by amplifying said input signal as a function of said gain control signal to generate the output signal based on switch-off ramp data responsive to the mute control signal indicating the power amplifier should be switched off, the switch-off ramp data decreasing the gain control signal from the second gain value to the first gain value that is less than the second gain value.

2. The method according to claim 1, wherein said at least one of said switch-on ramp or said switch-off ramp data comprise data identifying one or more ramp-steps and/or one or more ramp-widths, and wherein said gain control signal is generated by increasing or decreasing said gain control signal as a function of said one or more ramp-steps and/or one or more ramp-widths.

3. The method of claim 2, further comprising: controlling an up-counter to generate a series of up-count values to thereby generate the switch-on ramp data; and controlling a down-counter to generate a series of down-count values to thereby generate the switch-off ramp data.

4. The method of claim 3, wherein each of the switch-on ramp data and switch-off ramp data include at least one of variable ramp-steps or variable ramp-widths.

5. The method according to claim 1, generating the gain control signal comprises storing data in a memory for the switch-on and switch-off ramp data or generating the gain control signal based on a mathematical function.

6. The method according to claim 1, further comprising: receiving data identifying a switch-on duration; and determining whether said output signal of said power amplifier should be switched off by determining whether said switch-on duration has lapsed since said gain control signal has reached said second gain value.

7. The method of claim 1, further comprising providing a delay between the gain control signal and the mute control signal.

8. The method of claim 7, wherein providing the delay between the gain control signal and the mute control signal comprises controlling a counter to generate a count value that determines the delay.

9. The method of claim 7, wherein providing the delay between the gain control signal and the mute control signal comprises: generating a variable bias current having a value that determines the gain of the power amplifier; and generating a feedback control signal based on the variable bias current, the feedback signal setting a value of the delay.

10. The method according to claim 7, further comprising: delaying said switching on of said output signal of said power amplifier and/or said generation of said gain control signal with respect to said control signal indicating that said signal output of said power amplifier should be switched on, and/or delaying said switching off of said signal output of said power amplifier with respect to said decreasing of said gain control signal

11. A power amplifier circuit, comprising: a power amplifier including: a signal input for receiving an input signal, a signal output for providing an output signal, a control input for receiving a gain control signal being indicative of a requested gain, and a control input for receiving a mute control signal indicating whether said signal output should be switched on or switched off; a control unit coupled to said power amplifier to provide the input signal, the gain control signal and the mute control signal, the control unit being configured to generate the gain control signal having a switch-on ramp and a switch-off ramp based on switch-on and switch-off ramp data, the power amplifier being configured to: in response to said mute control signal indicates that the said signal output should be switched on, to generate at said signal output the output signal by amplifying said input signal as a function of said gain control signal, and in response to said mute control signal indicates that the said signal output should be switched off, deactivating said signal output.

12. The power amplifier circuit according to claim 11, wherein the control unit comprises a first circuit configured to: receive a control signal indicating whether said signal output of said power amplifier should be switched on; generate a switch-on signal indicating that said signal output of said power amplifier should be switched on as a function of said control signal.

13. The power amplifier circuit according to claim 12, wherein said control signal indicates whether said signal output of said power amplifier should be switched off, and wherein said first circuit is configured to generate a switch-off signal indicating that said signal output of said power amplifier should be switched off as a function of said control signal, and wherein said control unit is configured to generate said gain control signal as a function of said switch-off ramp data identifying said switch-off ramp when said switch-off signal indicates that said signal output of said power amplifier should be switched off.

14. The power amplifier circuit according to claim 13, wherein said control unit is configured to generate a further switch-off signal responsive to said gain control signal having reached a first gain value at the end of said switch-off ramp, said control unit including a second circuit configured to, generate said mute control signal of said power amplifier in order to indicate that said signal output of said power amplifier should be switched on when said switch-on signal indicates that said signal output of said power amplifier should be switched on; and generate said mute control signal of said power amplifier in order to indicate that said signal output of said power amplifier should be switched off when said further switch-off signal is generated.

15. The power amplifier circuit according to claim 9, wherein: said generating said mute control signal of said power amplifier in order to indicate that said signal output of said power amplifier should be switched on when said switch-on signal indicates that said signal output of said power amplifier should be switched on comprises delaying said switch-on signal, and/or said generating said mute control signal of said power amplifier in order to indicate that said signal output of said power amplifier should be switched off when said further switch-off signal is generated comprises delaying said further switch-off signal.

16. The power amplifier circuit according to claim 6, wherein said data identifying said switch-on ramp and/or said switch-off ramp comprise data identifying one or more ramp-steps and/or one or more ramp-widths, and wherein control unit comprises a counter block comprising one or more counters for generating said gain control signal by increasing or decreasing said gain control signal as a function of said one or more ramp-steps and/or one or more ramp-widths.

17. A system, comprising: a radio frequency signal generator; and a power amplifier circuit coupled to the radio frequency signal generator, the power amplifier circuit including a power amplifier including: a signal input for receiving an input signal, a signal output for providing an output signal, a control input for receiving a gain control signal being indicative of a requested gain, and a control input for receiving a mute control signal indicating whether said signal output should be switched on or switched off; and a control unit coupled to said power amplifier to provide the input signal, the gain control signal and the mute control signal, the control unit being configured to generate the gain control signal having a switch-on ramp and a switch-off ramp based on switch-on and switch-off ramp data, the power amplifier being configured to: in response to said mute control signal indicates that the said signal output should be switched on, to generate at said signal output the output signal by amplifying said input signal as a function of said gain control signal, and in response to said mute control signal indicates that the said signal output should be switched off, deactivating said signal output.

18. The system of claim 17, wherein radio frequency signal generator comprises an RF oscillator.

19. The system of claim 17, wherein the control unit includes a first circuit that is further configured to: receive a control signal indicating whether said signal output of said power amplifier should be switched on; and generate a switch-on signal indicating that said signal output of said power amplifier should be switched on as a function of said control signal.

20. The system of claim 19, wherein said control signal indicates whether said signal output of said power amplifier should be switched off, and wherein said first circuit is configured to generate a switch-off signal indicating that said signal output of said power amplifier should be switched off as a function of said control signal, and wherein said control unit is configured to generate said gain control signal as a function of said switch-off ramp data identifying said switch-off ramp when said switch-off signal indicates that said signal output of said power amplifier should be switched off.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0044] Embodiments of the present disclosure will now be described with reference to the annexed drawings, which are provided purely by way of non-limiting example and in which:

[0045] FIG. 1 is a block diagram of a conventional power amplifier;

[0046] FIG. 2 is a signal diagram showing signals generated in the power amplifier of FIG. 1 during operation of the power amplifier;

[0047] FIG. 3 is a block diagram of a conventional differential power amplifier;

[0048] FIG. 4 shows a power amplifier circuit in accordance with an embodiment of the present disclosure;

[0049] FIG. 5 shows an embodiment of a method of controlling the power amplifier circuit of FIG. 4;

[0050] FIGS. 6a and 6b show details according to an embodiment of the method of FIG. 5;

[0051] FIGS. 7, 8a, 8b and 9 show further embodiments of power amplifier circuits in accordance with the present disclosure and signals generated during operation of these power amplifier circuits;

[0052] FIGS. 10a to 10d show further details according to an embodiment of the method of FIG. 5;

[0053] FIGS. 11, 12, 13a and 13b show further embodiments of power amplifier circuit in accordance with the present disclosure and signals generated during operation of these power amplifier circuits;

[0054] FIGS. 14a to 14m show further details according to an embodiment of the method of FIG. 5;

[0055] FIGS. 15 and 15a to 15f show an embodiment of a power amplifier which may be used in the power amplifier circuits of the present disclosure;

[0056] FIG. 16 shows an embodiment of a variable current source which may be used in the power amplifier of FIGS. 15 and 15a to 15f; and

[0057] FIGS. 17, 18, 19a and 19b show still further embodiments of a power amplifier circuit in accordance with the present disclosure and signals generated during operation of these power amplifier circuits.

DETAILED DESCRIPTION

[0058] In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0059] Reference throughout this specification to one embodiment or an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases in one embodiment or in an embodiment in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0060] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0061] In the following FIGS. 4 to 19 parts, elements or components which have already been described with reference to FIGS. 1 to 3 are denoted by the same references previously used in such figures. The description of such previously described elements will not be repeated in the following in order not to overburden the present detailed description.

[0062] As mentioned in the foregoing, various embodiments of the present disclosure relate to solutions for reducing the spurious emissions of a power amplifier.

[0063] FIG. 4 shows a power amplifier circuit 40 in accordance with a first embodiment of the present disclosure.

[0064] In the embodiment of FIG. 4 being considered, the power amplifier circuit 40 includes a power amplifier 20, such as the power amplifier shown in FIG. 3, and a control unit 42.

[0065] Specifically, in the embodiment considered, the power amplifier 20 includes: [0066] an input for receiving a signal IN, [0067] an output for providing a signal OUT, [0068] an input for receiving a mute control signal MUTE.sub.INT, [0069] an input for receiving at least one control signal A.sub.INT for setting the gain of the power amplifier 20.

[0070] Specifically, in the embodiment being considered, the power amplifier 20 is configured to operate as follows: [0071] when the mute control signal MUTE.sub.INT has a first logic level (e.g., low) indicating that the output of the power amplifier 20 should be switched on, generate at the output OUTa signal by amplifying the signal IN, as a function of the gain specified by the control signal A.sub.INT; and [0072] when the mute control signal MUTE.sub.INT has a second logic level (e.g., high) indicating that the output of the power amplifier 20 is switched off, deactivate the output OUT of the power amplifier 20.

[0073] In the embodiment considered, the power amplifier circuit 40 includes: [0074] an input for receiving the signal IN, [0075] an output for providing the signal OUT, [0076] an input for receiving a mute control signal MUTE.

[0077] Accordingly, in the embodiment being considered, the signal IN provided to the input of the power amplifier circuit 40 is fed directly to the input IN of the power amplifier 20 and the output OUT of the power amplifier 20 corresponds to the output OUT of the power amplifier circuit 40.

[0078] Conversely, the signal MUTE provided to the power amplifier circuit 40 is fed to the control unit 42, which is configured to generate the mute control signal MUTE.sub.INT and the gain control signal A.sub.INT of the power amplifier 20 as a function of the signal MUTE. Generally, the control unit 42 may be any analog and/or digital circuit. For example, in various embodiments, the control unit 42 may be a micro-processor being programmed via software instructions or a custom digital circuit implementing a state machine.

[0079] For example, similar to FIG. 1, the signals IN and MUTE may be generated by a signal generator circuit 10. For example, the signal IN may be generated by an oscillator 12, such as an (RF) oscillator with fixed or controllable frequency, such as a voltage controlled oscillator (VCO). Conversely, the signal MUTE may be generated by an electronic control circuit 14. Accordingly, at least part of the control circuit 14 may also be implemented directly within the control unit 42 or vice versa at least part of the control unit 42 may be implemented within the control circuit 14.

[0080] FIG. 5 is a flow chart showing an embodiment of the operation the control unit 42 and FIGS. 6a and 6b show exemplary waveforms for the signals MUTE, MUTE.sub.INT and A.sub.INT.

[0081] Specifically, after a start step 1000, the control unit 42 verifies at a step 1002 whether the signal MUTE has the first logic level indicating that the output of the power amplifier circuit 20 should be switched on or the second logic level indicating that the output of the power amplifier circuit 40 should be switched off.

[0082] In case the signal MUTE has the first logic level (output ON of the verification step 1002), the process executed by the control unit 42 proceeds to a step 1004, in which the control unit 42 obtains data identifying a switch-on ramp. For example, these data may be stored in a memory or may be identified with a mathematical function. For example, in various embodiments, the switch-on ramp corresponds to a linear increase from a minimum gain A.sub.MIN to a maximum gain A.sub.MAX. Accordingly, the values for A.sub.MIN and/or A.sub.MAX may be stored in an internal memory or provided to the control unit 42.

[0083] For example, in various embodiments (see, e.g., FIG. 6a) the gain A.sub.MIN indicates a zero amplification. However, generally (see, e.g., FIG. 6b), the gain A.sub.MIN may also indicate a non-zero value. In various embodiments, the gain A.sub.MIN corresponds, however, to the smallest settable gain of the power amplifier 20.

[0084] Next, the control unit 42 sets at a step 1006 the signal MUTE.sub.INT to a first logic level indicating that the output of the power amplifier 20 should be switched on, i.e., the power amplifier 20 is switched on and amplifies the signal IN with A.sub.INT=A.sub.MIN.

[0085] The control unit 42 proceeds then to a step 1008, in which the control unit 42 increases the gain signal A.sub.INT according to the switch-on ramp from the value A.sub.MIN to a given value A.sub.MAX, i.e., the power amplifier 20 increases the amplification of the signal IN until A.sub.INT=A.sub.MAX. Generally, the gain A.sub.MAX may be any gain being greater than the gain A.sub.MIN. In various embodiments, the gain A.sub.MAX corresponds, however, to the highest settable gain of the power amplifier 20.

[0086] Accordingly, as shown in FIGS. 6a and 6b when the power amplifier circuit 40 is switched on at a time to by changing the signal MUTE from the second to the first logic level (e.g., from high to low), the control unit 42 switches on the power amplifier 20 by changing the signal MUTE.sub.INT from the second to the first logic level (e.g., from high to low) and increases the amplification until the gain A.sub.INT reaches A.sub.MAX at a time t.sub.3.

[0087] At a step 1010, the control unit 42 verifies then whether the signal MUTE changes.

[0088] In case the signal MUTE does not change (output NO of the verification step 1010), the control unit 42 returns to the step 1010, possibly via a wait step 1012.

[0089] Conversely, in case the signal MUTE changes (output YES of the verification step 1010), the control unit 42 returns to the step 1002.

[0090] Accordingly, in case the signal MUTE has now the second logic level (output OFF of the verification step 1002), the control unit 42 proceeds to a step 1014, in which the control unit 42 obtains data identifying a switch-off ramp. Again, these data may be stored in a memory or may be identified with a mathematical function. For example, in various embodiments, the switch-off ramp corresponds to a linear decrease from a maximum gain A.sub.MAX to a minimum gain A.sub.MIN.

[0091] The control unit 42 proceeds then to a step 1016, in which the control unit 44 decreases the gain signal A.sub.INT according to the switch-off ramp from the value A.sub.MAX to the value A.sub.MIN, i.e., the power amplifier 20 decreases the amplification of the signal IN until A.sub.INT=A.sub.MIN.

[0092] Next, the control unit 42 sets at a step 1018 the signal MUTE.sub.INT to the second logic level indicating that the output of the power amplifier 42 should be switched off, i.e., the power amplifier 20 is switched off with A.sub.INT=A.sub.MIN.

[0093] Accordingly, as shown in FIGS. 6a and 6b, once the power amplifier circuit 40 is switched off at a time t.sub.1 by changing the signal MUTE from the first to the second logic level (e.g., from low to high), the control unit 42 will decrease the amplification from A.sub.MAX to A.sub.MIN and only then the power amplifier 20 is switched off at a time t.sub.4 by changing the signal MUTE.sub.INT from the first to the second logic level (e.g., from low to high).

[0094] Finally, the control unit 42 proceeds again to the step 1010 for verifying whether the signal MUTE changes again.

[0095] Accordingly, in the embodiment being considered, the power amplifier circuit 40 is smoothly switched on and off by varying the gain of the power amplifier 20, thereby reducing spurious emissions.

[0096] Generally, as shown in FIG. 6b, which especially applies when the gain A.sub.MIN does not correspond to a zero gain, the output power P.sub.OUT may have a small step-like decrease at the instant t.sub.4, when the output of the power amplifier 20 is switched off via the signal MUTE.sub.INT.

[0097] In various embodiments, the gain values A.sub.MAX and A.sub.MIN are fixed or configured within the control unit 42. For example, in case of analog signals, the values A.sub.MAX and/or A.sub.MIN may be set via a voltage reference or a simple voltage divider. Conversely, in case of digital signals, the values A.sub.MAX and/or A.sub.MIN may be stored in a memory. Instead, in other embodiments, the control unit 42 may include an input for receiving the (digital or analog) gain values A.sub.MAX and/or A.sub.MIN.

[0098] For example, FIG. 7 shows an embodiment, in which the gain value A.sub.MIN may be fixed, e.g., to the minimum gain of the power amplifier 20, and the gain value A.sub.MAX may be provided to the power amplifier circuit 40, e.g., by the signal generator 10.

[0099] Moreover, instead of using an on/off mute control signal MUTE, also other types of signals may be used to switch on and off the output of the power amplifier circuit.

[0100] For example, FIG. 8a shows an embodiment, in which a trigger signal TRIG is used. For example, as shown in FIG. 8b, this trigger signal TRIG may be set to high for a brief time interval, each time the output of the power amplifier circuit 20 should be switched.

[0101] For example, in this case, the control unit 42 may perform alternatively the steps 1004-1008 or 1014-1018 each time a trigger in the signal TRIG is detected. For example, this can be achieved by monitoring the signal TRIG at the step 1010 in FIG. 5, and the signal MUTE.sub.INT at the step 1002.

[0102] For example, in this case the control unit 42 may be configured to: [0103] in case no trigger is detected in the signal TRIG at the step 1010, return to the step 1010 (possibly via the optional wait step 1012), and [0104] in case a trigger is detected in the signal TRIG at the step 1010, return to the step 1002.

[0105] Conversely, at the step 1002, the control unit 42 may: [0106] proceed to the step 1004, in case the mute control signal MUTE.sub.INT is currently set to the second logic level indicating that the output of the power amplifier 20 is currently switched off, and [0107] proceed to the step 1014, in case the mute control signal MUTE.sub.INT is currently set to the first logic level indicating that the output of the power amplifier 20 is currently switched on.

[0108] As mentioned before, the control unit 42 may also implement at least part of the control circuit 14. For example, FIG. 9 shows an embodiment, wherein the signal TRIG indicates only the start of a new cycle and the control unit 42 receives (e.g., from a memory or the control circuit 14) data being indicative of the switch-on duration T.sub.ON.

[0109] In the previous embodiments, the operation of the control unit 42 is thus synchronized with the operation of the signal generator 10, e.g., with the frequency sweeping operation performed by the circuit 12. However, in case no modulation of the signal IN is performed, the control unit 42 may also operate independently from the control circuit 14. For example, in this case, the control unit 42 may directly receive signals being indicative for the switch-on duration T.sub.ON and the switch-off duration T.sub.OFF, such as a signal being indicative of the duty cycle to be used.

[0110] Moreover, in the previous embodiments, the amplitude of the internal gain signal A.sub.INT is varied linearly at the steps 1008 and 1016. However, generally also any other profiles may be used.

[0111] For example, FIG. 10a shows the wave-form of the signal A.sub.INT, as shown in FIG. 6b. FIG. 10b shows that the waveform may also use a greater/smaller gradient (i.e., increase/decrease rate) and FIGS. 10c and 10b show two arbitrary rising and falling profiles for the signal A.sub.INT.

[0112] As described in the foregoing, the control unit 42 may thus receive data identifying the rising profile/ramp between the instants t.sub.0 and t.sub.3 (FIG. 6b) and/or the falling profile/ramp between the instants t.sub.1 and t.sub.4 (FIG. 6b). For example, in the embodiments shown in FIGS. 7, 8 and 9, these profiles of the signal A.sub.INT were specified via the maximum value A.sub.MAX (and possibly the minimum value A.sub.MIN) and the increase/decrease rates used at the steps 1008/1016 were fixed.

[0113] As mentioned in the foregoing, the control unit 42 may be any analog and/or digital circuit.

[0114] FIG. 11 shows a first embodiment of a digital control unit 42, which may be used, e.g., in the embodiment shown in FIG. 8, in which the trigger signal TRIG contains a trigger each time the output of the power amplifier circuit 40 should be turned on or turned off.

[0115] For example, in the embodiment considered, the control unit 42 includes a trigger detector 420 configured to determine a trigger in the signal TRIG. Specifically, the trigger detector 420 may generate two signals ON and OFF indicating whether the output OUT should be switched on or switched off, respectively. Accordingly, the trigger detector 420 implements steps 1002 and 1010 of FIG. 5. A similar behavior may thus also be reached by implementing the steps 1002 and 1010 in the trigger detector 420 also for a mute signal MUTE.

[0116] As shown in FIG. 5, in case the output OUT should be switched on, the signal MUTE.sub.INT should switch on the output of the power amplifier 20 (step 1006) and increase the gain A.sub.INT from A.sub.MIN to A.sub.MAX (step 1008). For example, the step 1006 is implemented by a switching block 422 configured to set the signal MUTE.sub.INT to the first logic level for switching on the output OUT of the power amplifier 20 when the signal ON is set, e.g., to high. Conversely, the step 1008 is implemented by a counter block 424 configured to generate a digital count value corresponding to a digital gain signal A.sub.INT,D in accordance with a clock signal CLK. Specifically, this counter block 424 is configured to increase the digital gain signal A.sub.INT,D until A.sub.INT,D=A.sub.MAX when the signal ON is set, thereby implementing step 1008. Conversely, this counter block 424 is configured to decrease the digital gain signal A.sub.INT,D until A.sub.INT,D=A.sub.MIN when the signal OFF is set, thereby implementing also the step 1016.

[0117] In the embodiment being considered, the counter block 424 generates also an end-signal OFF indicating that the digital gain signal A.sub.INT,D has reached A.sub.MIN, thereby indicating the end of the step 1016. This signal OFF may thus be used by the switching block 422 in order to set the signal MUTE.sub.INT to the second logic level for switching off the output OUT of the power amplifier 20 when the signal OFF is set.

[0118] Accordingly, the switch block 422 implements both the step 1006 and the step 1018 of FIG. 5. For example, the block 422 may be implemented with a set-reset (SR) flip-flop.

[0119] Generally, the counter 424 block may be implemented with a single up-and-down counter. Conversely, FIG. 11 shows an embodiment in which an up-counter 4240, a down-counter 4242 and a multiplexer 4248 are used. For example, the up-counter 4240 may be reset and enabled as a function of the signal ON. Conversely, the down-counter 4240 may be reset and enabled as a function of the signal OFF. Finally, the multiplexer 4248 receives at input the count values from the counters 4240 and 4242 and the selection may be driven either by the signal ON or the signal OFF.

[0120] In the embodiment being considered, the digital gain signal A.sub.INT,D is provided to a digital-to-analog converter 28 configured to generate a corresponding analog gain signal A.sub.INT,A. As mentioned in the foregoing, the D/A converter (DAC) 28 may also be part of the power amplifier 20.

[0121] In various embodiments, the analog gain signal A.sub.INT,A may be filtered by a filter 202, such as a low-pass filter. Accordingly, the filter 202 will generate a filtered version of the analog gain signal A.sub.INT,F of the analog gain signal A.sub.INT,A, which may then be used by the power amplifier 20. For example, the filter 202 may be useful in order to generate a smoother gain signal, which does not include the digital steps of the digital-to-analog conversion. Accordingly, from a spectral point of view, the filter 202 filters the spurs generated by the control circuit 42, in particular the clock signal CLK, around the carrier at offsets equal to clock frequency and its harmonics.

[0122] Generally, also in this case, the minimum gain A.sub.MIN and/or the maximum gain A.sub.MAX may be fixed or provided to the control unit 42.

[0123] FIG. 12 shows a second embodiment of the control unit 42, which may be used, e.g., in the embodiment shown in FIG. 9, in which the trigger signal TRIG contains a trigger each time a new cycle should be performed.

[0124] Specifically, in this case, the block 420 generates a signal ON, when the signal TRIG contains a trigger. This signal is then used by the switching block 422, as in FIG. 11, in order to switch-on the output OUT of the power amplifier 20.

[0125] Moreover, also in this case, the signal ON is used by the counter block 424 in order create the rising ramp of the digital gain signal A.sub.INT,D. However, due to the fact that the signal OFF is not provided by the block 420, the counter block 424, determines internally, whether the switch-on duration T.sub.ON has lapsed. For example, as shown in FIG. 12, when the digital gain signal A.sub.INT,D reaches the maximum gain A.sub.MAX, the counter block 424 may perform a second count operation (schematically shown by a further counter 4244), which counts until a count value being proportional to the switch-on duration T.sub.ON is reached. Once the count value has been reached, the counter 4244 may generate the signal OFF, which signals to the down-counter 4242 that the switch-off profile has to be generated.

[0126] Accordingly, in the embodiment considered, the switch-off phase is started automatically, when the counter block 424 determined internally that the switch-on duration T.sub.ON has finished.

[0127] Generally, the A/D converter 28, the filter 202 and/or the power amplifier 20 may introduce a delay in the transfer of the gain A.sub.INT to the output OUT, or is at least slower than the actuation of the mute control signal MUTE.sub.INT. Accordingly, as shown in FIG. 13a, it is likely, that the output will be switched off at the instant t.sub.4, while the output power P.sub.OUT is still decreasing.

[0128] Accordingly, the control unit 42 may introduce a delay in the mute control signal MUTE.sub.INT in order to compensate this behavior.

[0129] For example, FIG. 13b shows an embodiment, in which the counter block 424 determines internally (once the falling ramp has been generated) that a switch-off delay duration has finished. For example, in the embodiment considered a further switch-off delay counter 4246 is used for this purpose, which is started when the counter 4242 has reached the minimum gain value A.sub.MIN. For example, the signal OFF may be generated by this switch-off delay counter 4246, which thus signals to the block 422 that the power amplifier 20 may be switched off when the switch-off delay counter 4246 reaches a count value being proportional to the desired switch-off delay.

[0130] Generally, a similar delay may also be used in order delay the rising ramp. For example, this may be achieved by a further switch-on delay counter 4250 before the counter block 4240, i.e., the counter 4240 is not driven directly by the signal ON but a delayed version ON thereof which is generated by the counter 4250. For example, this may be useful in case the gain may not be increased immediately at the instant to, e.g., in case the power amplifier 20 requires a given time until the output power is stable. As will be disclosed later, generally, the switching block 422 may also use the delayed switch on signal ON instead of the signal ON, thereby delaying also the switch-on of the output via the mute control signal MUTE.sub.INT.

[0131] Generally, the maximum count values of the counters 4246 and/or 4250, i.e., the delays introduced, may be fixed or settable.

[0132] As mentioned with respect to FIG. 11, the counter block 424 does not have to implement necessarily a single step counting operation.

[0133] In fact, in various embodiments, the counter block 124 is configured in order to set for a plurality of counting steps the increase/decrease, i.e., the ramp step, and/or the number clock cycles of the counting step, i.e., a step width. For example, the step-width may be specified by specifying a ramp-step of zero for one or more counting steps. For example, the values for the various ramp steps and/or step widths may be stored in a memory within the control unit 42. Generally, these values may also be programmed, e.g., by means of the control circuit 14 of the signal generator 10.

[0134] FIGS. 14a to 14m show possible switch-on profiles, which may be obtained with the circuits described in the foregoing.

[0135] For example, FIGS. 14a to 14f show different ramp steps. Specifically, in FIG. 14a, the ramp-step is fixed to one for all count steps. Conversely, in FIGS. 14b, 14d, and 14f the ramp step is set to two, four or A.sub.MAX, respectively.

[0136] Conversely, FIGS. 14c and 14e show that the ramp-step may also be different for the various steps, such as the steps (3, 3, 2) in FIG. 14c and (5, 3) in FIG. 14e. Generally, the ramp-step may also in this case be fixed, but the counter block 424 may limit the gain A.sub.INTr to the maximum value A.sub.MAX.

[0137] This is also shown in FIGS. 14g to 14j, in which the ramp-step is fixed to one, while only the maximum gain A.sub.MAX is varied.

[0138] Finally, FIGS. 14k to 14m show that also the ramp-width may be adapted. For example, in FIG. 14k the ramp-width of the second count step is set to two and in FIG. 14l to three. As mentioned in the foregoing this may be obtained by specifying a ramp-width or by setting the ramp-step to zero for one or more count steps. For example, the ramp shown in FIG. 14k could have the following profile: (1, 0, 1, 1, 1, 1, 1, 1, 1). Conversely, the ramp shown in FIG. 14m could have the following ramp profile: (1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1).

[0139] Generally, by specifying the ramp-step for each count step, it is also not necessary to specify the maximum gain value A.sub.MAX, which corresponds in this case to the count value reached at the last count step.

[0140] Evidently, the same behavior may also be used for the switch-off profile. Moreover, as mentioned in the foregoing, the ramp profiles may be specified with any other suitable data able to identify the switch-on and switch-off profiles. For example, the data may also contain directly the values of A.sub.INT, e.g., (2, 4, 6, 8) for the embodiment shown in FIG. 14b.

[0141] Finally, in the embodiments considered in the foregoing, the gain value A.sub.INT is set to the minimum value A.sub.MIN when the output of the power amplifier 20 is switched off via the internal mute signal MUTE.sub.INT. However, in general, the gain value A.sub.INT may also be set to other values in this case, e.g., to the maximum gain A.sub.MAX.

[0142] For example, this may be useful for a power amplifier 20 as shown in FIG. 15.

[0143] Specifically, in the embodiment being considered, the power amplifier includes a variable current source 200 configured to generate a current I.sub.BIAS as a function of the gain signal A.sub.INT. For example, in the embodiment being considered, the current source 200 is driven via a D/A converter 28 (and as shown in FIGS. 11, 12 and 13 an optional filter 202) by means of a digital gain signal A.sub.INT,D.

[0144] For example, FIG. 16 shows a possible embodiment of the current source 200.

[0145] Specifically, in the embodiment considered, the D/A 208 is a current digital-to-analog converter (IDAC), which generates a current as a function of the digital gain signal A.sub.INT,D.

[0146] In the embodiment considered, the current generated by the IDAC 28 is fed to a current mirror including two transistors M3 and M4, e.g., FET (field-effect transistor), wherein the output of the current mirror provides the current I.sub.BIAS.

[0147] For example, in the embodiment considered, two p-channel FET M3 and M4 are used. For example, in the embodiment considered, the sources of the transistors M3 and M4 are connected to a voltage supply V.sub.CC1, whereas the drain of the transistor M3 is connected both to the IDAC 28 and the gates of the transistors M3 and M4. Accordingly, the drain of the transistor M4 provides a current I.sub.BIAS, which is proportional to the current at the output of the IDAC 28.

[0148] In the embodiment being considered in FIG. 15, the current I.sub.BIAS generated by the current source 200 is fed to a current mirror including two transistors M1 and M2, e.g., bipolar junction transistors.

[0149] For example, in the embodiment considered, two npn bipolar transistors M1 and M2 are used. For example, in the embodiment being considered, the emitter of the transistors M1 and M2 are connected to ground, while the collector of the transistor M2 is connected both to the current source 200 and the bases of the transistors M1 and M2. Finally, the collector of the transistor M1 is connected to a node 206. Accordingly, the collector-emitter current I flowing through the transistor M1 will be proportional to the current I.sub.BIAS.

[0150] Generally, instead of using two current-mirrors (M1/M2 and M3/M4), also only one current mirror could be used or the IDAC 28 could directly be used in place of the transistor M1.

[0151] In the embodiment considered, the current I is applied to a differential amplifier stage including, e.g., two bipolar junction transistors Q1 and Q2, such as npn transistors, configured to amplify the signal IN.

[0152] Specifically, in the embodiment considered, the emitter terminals of the transistors Q1 and Q2 are connected to the node 206 to which is applied the current I, i.e., emitter terminals of the transistors Q1 and Q2 are connected to the drain of the transistor M1. Conversely, the base terminal of the transistor Q1 is connected to the positive terminal of the signal IN and the base terminal of the transistor Q2 is connected to the negative terminal of the signal IN. Accordingly, the variable current source 200, the current mirror M1/M2 and the differential amplifier stage Q1/Q2 implement the differential amplifier with variable gain 24.

[0153] In the embodiment being considered, the output of the differential amplifier stage Q1/Q2 is provided via a switching stage 26 to an output stage 204.

[0154] For example, in the embodiment being considered, the output stage 204 is based on a transformer having a primary winding with a central tap connected to the supply voltage V.sub.CC3 and wherein the secondary winding provides the output signal OUT. Accordingly, by changing the flow direction of the current I through the primary winding as a function of the signal IN, the alternating signal IN will be transferred to the output OUT, wherein the amplification depends on the value of the current I and the transformer ratio.

[0155] Generally, also other output stages 204 may be used. For example, reference can be made to FIG. 1 of document U.S. Pat. No. 7,312,660 B2, which is incorporated by reference herein in its entirety to the extent not inconsistent with the specific teachings and definitions of the present application. In fact, in general, the output stage 204 is configured to transfer a given current flow to the output of the power amplifier 20.

[0156] In the embodiment being considered, the switching stage 26 transfers thus selectively the current flow generated by the variable gain amplifier (200, M1/M2, Q1/Q2) to the output stage 204 as a function of the mute control signal MUTE.sub.INT. Specifically, in the embodiment considered, the output of the variable gain amplifier is connected either to the output stage 204 or a dummy load, represented in the embodiment considered by a supply voltage V.sub.CC2. For example, in case the mute control signal MUTE.sub.INT is greater than a given threshold, the output of the variable gain amplifier is connected to the output stage 204 and when the mute control signal MUTE.sub.INT is smaller than a given threshold, the output of the variable gain amplifier is connected to the supply voltage V.sub.CC2.

[0157] For example, in the embodiment considered, the switching stage 26 is implemented with four bipolar junction transistors Q3, Q4, Q5 and Q6, such as npn transistors.

[0158] Specifically, the emitter terminals of the transistors Q3 and Q5 are connected (e.g., directly) to the collector terminal of the transistor Q1 and the emitter terminals of the transistors Q4 and Q6 are connected (e.g., directly) to the collector terminal of the transistor Q2. The collector terminal of the transistor Q3 is connected (e.g., directly) to a first terminal of the output stage and the collector terminal of the transistor Q4 is connected (e.g., directly) to the second terminal of the output stage. Conversely, the collector terminal of the transistors Q5 and Q6 are connected (e.g., directly) to the dummy load, e.g., V.sub.CC2. Finally, the base terminals of the transistors Q3 and Q4 are connected to a first (e.g., negative) terminal of the signal MUTE.sub.INT and the base terminals of the transistors Q5 and Q6 are connected to the second (e.g., positive) terminal of the signal MUTE.sub.INT.

[0159] Accordingly, in the embodiment being considered, the transistors Q3 and Q4 are used to connect the output of the variable gain amplifier to the output stage 204 and the transistors Q5 and Q6 are used to connect the output of the variable gain amplifier to the dummy load. Specifically, considering the connection of the signal MUTE.sub.INT, the output of the power amplifier 20 is switched on when the signal MUTE.sub.INT is low.

[0160] For example, this is also shown schematically in the waveforms a)-f) in FIG. 15.

[0161] Specifically, FIG. 15f shows an exemplary waveform for the current I.sub.BIAS generated by the current source 200 as a function of the gain signal A.sub.INT.

[0162] This (settable) current will also flow through the differential amplifier stage including the transistors Q1 and Q2 (see FIG. 15c).

[0163] Conversely, the mute signal MUTE.sub.INT (an exemplary waveform of the signal MUTE.sub.INT is shown in FIG. 15d) determines whether this current flows through the switches Q3/Q4 and thus the output stage 204 (an exemplary waveform of the current flowing through the switch Q3 is shown in FIG. 15a) or Q5/Q6 (an exemplary waveform of the current flowing through the switch Q5 is shown in FIG. 15b).

[0164] In the embodiment considered, the signal IN is an oscillating signal, and as schematically shown in FIG. 15e also the signal OUT will be an oscillating signal when the switches Q3 and Q4 are closed, because the current I flows alternatively through the switches Q1 or Q2.

[0165] Accordingly, in the embodiment being considered, the amplitude of the current I is not varied by the switching stage 26, but is only determined by the current generator 200 (and possibly the current mirror M1/M2).

[0166] In the embodiment shown in FIG. 15 (see in particular FIG. 15f), it is thus advantageous to set the gain A.sub.INT to the maximum value A.sub.MAX (used when the output of the power amplifier 20 is switched on) when the output of the power amplifier 20 is switched off.

[0167] In fact, by maintaining the current provided by the current source 200 as much as possible constant (except for the rising and falling ramps discussed in the foregoing), thermal variations during switch on/off phases are reduced and the temperature of the power amplifier 20 may remain almost constant, avoiding, e.g., thermal pulling phenomena on the VCO 12, e.g., in case the respective PLL is embedded in the chip including also the power amplifier 20.

[0168] FIG. 17 shows a further embodiment, in which the control unit 42 is configured to vary the signal A.sub.INT during the switch-on and/or switch-off ramps as a function of a feedback signal S provided by the power amplifier 20.

[0169] For example, the feedback control signal S may be used to perform a closed loop control and thus may be used to replace the counters 4246 and/or 4250, which implement a predictive/open loop control. For example, the feedback signal S may be used to: [0170] delay the rising/switch-on ramp until the output current is stable once the output of the power amplifier 20 has been switched on, and/or [0171] delay the switch-off of the output of the power amplifier 20 until the output current/power has reached a given minimum power level.

[0172] For example, FIG. 18 shows an embodiment wherein the signal S is used to delay the rising/switch-on ramp until the output current is stable once the output of the power amplifier 20 has been switched on.

[0173] Specifically, as shown in FIG. 18 this may be achieved by replacing the counter 4250 with a combinational logic 4252, such as an AND gate, which receives at input the signal ON generated by the block 420 and the signal S, and provides at output the delayed version ON of the signal ON. A similar circuit may also be used to replace the counter 4246, i.e., a combinational logic may be used which receives at input the signal generated by the counter 4242 and the signal S, and provides at output the delayed switch-off signal OFF.

[0174] For example, in the embodiment being considered, the signal S indicates whether the current I.sub.BIAS or similarly the current I is smaller than a given value.

[0175] For example, as shown in FIG. 19a, this control is particularly useful for the power amplifier 20 disclosed with respect to FIG. 15. In fact, in this case, the gain A.sub.INT is set to the value A.sub.MAX when the output of the power amplifier 20 is deactivated via the mute signal MUTE.sub.INT. Conversely, when the output has to be switched on, the gain A.sub.INT is set to the value A.sub.MIN. However, the variation of the gain is not immediately transferred to the current I.sub.BIAS. Accordingly, the output of the power amplifier 20 is not switched on with a minimum current.

[0176] Conversely, as shown in FIG. 19b, in the embodiment considered, the signal S indicates whether the current I.sub.BIAS is smaller than a given threshold value. Accordingly, the switch on via the mute signal MUTE.sub.INT (e.g., generated by the switching block 422 in FIG. 18) and the generation of the rising ramp (e.g., via the counter block 4240 in FIG. 18) are delayed (e.g., by means of the generation of the delayed signal ON at the gate 4252 in FIG. 18) until the signal S indicates that the current I.sub.BIAS is smaller than a given threshold value, i.e., the switch from A.sub.MAX to A.sub.MIN has been completed.

[0177] For example, as shown in FIG. 16, the current I.sub.BIAS and similarly I may be sensed by providing an additional current mirror branch. For example, in the embodiment being considered a further transistor M5, a p-channel FET in the embodiment being considered, is connected with its gate to the drain of the transistor M3, while the source of the transistor M5 is connected to the voltage supply V.sub.CC1. Accordingly, the drain of the transistor M5 provides a current, which is proportional to the current I.sub.BIAS. This current is sensed by a current sensor, e.g., a shunt resistor R.sub.isense generating a signal being indicative of the current I.sub.BIAS.

[0178] For example, in the embodiment considered, a comparator 210, such as a Schmitt trigger, is used to generate a signal V.sub.isense (representing the feedback signal S) indicating whether the current I.sub.BIAS is greater than a first threshold or smaller than a second threshold (possibly being the same as the first threshold).

[0179] Of course, without prejudice to the principles of the present disclosure, the details of construction and embodiments of the present disclosure may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present disclosure.

[0180] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.