Circuit for generating at least two rectangular signals with adjustable phase shift and use of said circuit

Abstract

A circuit for generating at least two rectangular signals with adjustable phase shift, comprises a frequency divider circuit that receives a clock signal as input and provides a signal as output, at least two comparators that receive, respectively, a first threshold voltage and at least a second threshold voltage at one input, and a ramp signal, synchronized with the clock signal, at a second input, the at least two threshold voltages allowing the value of the phase shift between the at least two rectangular signals to be adjusted, and at least two D-type flip-flops that receive, respectively, the output signal from the first comparator and the output signal from the second comparator at their clock inputs, and the output signal from the frequency divider circuit at their D-input.

Claims

1. A circuit for generating at least two rectangular signals with adjustable phase shift, comprising: a frequency divider circuit that receives a first clock signal as input and provides a second clock signal as output; at least two comparators that receive, respectively, a first threshold voltage and at least a second threshold voltage at one comparison input, and a triangular ramp signal, synchronized with the first clock signal, at a second comparison input, the group of at least two threshold voltages allowing the value of the phase shift between the signals of the group of at least two rectangular signals with adjustable phase shift to be adjusted; at least two D-type flip-flops that receive, respectively, the output signal from the first comparator and the output signal from the second comparator at their clock inputs, and the output signal from the frequency divider circuit at their D-input, the group of at least two rectangular signals with adjustable phase shift being available at the Q-outputs of the group of at least two D-type flip-flops.

2. The circuit as claimed in claim 1, wherein the frequency divider circuit is a divide-by-two frequency divider.

3. The circuit as claimed in claim 1, wherein the frequency divider circuit comprises a D-type flip-flop whose D-input is connected to the complementary Q*-output.

4. The circuit as claimed in claim 1, additionally comprising a clock circuit configured to generate a triangular ramp signal, said clock circuit receiving the clock signal as input and the output of said clock circuit being connected to one of the two comparison inputs of each comparator.

5. A phase-shifted power converter, comprising a circuit for generating two rectangular signals with adjustable phase shift as claimed in claim 1, said rectangular signals being configured to control switches of the primary and secondary bridges of said power converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other particularities and advantages of the present invention will become more clearly apparent upon reading the description which follows, given by way of non-limiting illustration and with reference to the appended drawings in which:

(2) FIG. 1, described above, shows a circuit for generating at least two rectangular signals with adjustable phase shift known from the prior art;

(3) FIG. 2, described above, shows the appearance of the signals at various points in the circuit of FIG. 1;

(4) FIG. 3, described above, shows the appearance of the signals at various points in the circuit of FIG. 1 in a particular scenario;

(5) FIG. 4 shows an exemplary embodiment of a circuit for generating at least two rectangular signals with adjustable phase shift according to the invention;

(6) FIG. 5 shows examples of the appearance of the signals at various points in the circuit of FIG. 4;

(7) FIG. 6 shows examples of the appearance of the signals at various points in the circuit of FIG. 4 when interference occurs.

(8) FIG. 7 shows an exemplary embodiment of a phase-shifted power converter wherein the control signals of the switches of the DC/AC and AC/DC converters are phase-shifted using a circuit for generating at least two rectangular signals with adjustable phase shift according to one embodiment of the invention.

DETAILED DESCRIPTION

(9) FIG. 4 shows an exemplary embodiment of a circuit 40 for generating at least two rectangular signals with adjustable phase shift according to the invention. In order to simplify the explanations and so as not to overload the figures, a specific case in which the number of signals generated is equal to two is shown.

(10) In this embodiment, the circuit comprises a frequency divider circuit 46, two comparators C1, C2 and two D-type flip-flops D1, D2.

(11) According to one embodiment, the frequency divider circuit 46 may be a divide-by-two frequency divider circuit.

(12) According to one embodiment, the divider circuit 46 may be implemented using a D-type flip-flop whose D-input is connected to the complementary Q*-output.

(13) In the embodiment illustrated in FIG. 4, the frequency divider circuit 46 receives a first clock signal CLK as input and provides a second clock signal CLK_2 as output.

(14) The first comparator C1 receives, at one of its comparison inputs, a first signal Vs.sub.1 and, at the second input, a triangular ramp signal V.sub.rampe.

(15) The second comparator C2 receives, at one of its comparison inputs, a second signal Vs.sub.2 and, at the second input, the same triangular signal V.sub.rampe as above.

(16) Both signals Vs.sub.1 and Vs.sub.2 are analog voltages allowing the phase shift between the two rectangular signals with adjustable phase shift to be defined.

(17) The triangular ramp signal is synchronized with the first clock signal CLK of the frequency divider circuit 46. The first clock signal CLK may be used to generate the ramp signal.

(18) According to one embodiment, the circuit 40 for generating at least two rectangular signals S.sub.1, S.sub.2 with adjustable phase shift may comprise a clock circuit 45 that is configured to generate a triangular ramp signal V.sub.rampe. The clock circuit 45 may receive the first clock signal CLK as input and provide the triangular signal V.sub.rampe as output for the comparators C1 and C2. In order to do this, the output of the clock circuit 45 may be connected to one of the two comparison inputs of each comparator C1, C2.

(19) The triangular signal V.sub.rampe allows the possible range of variation in the phase shift between the two output signals to be defined. According to the duty cycle of the ramp signal, this range may extend up to 180.

(20) The circuit according to one embodiment of the invention may also comprise two D-type flip-flops. These flip-flops may be active on the rising or falling edge.

(21) The first flip-flop D1 receives, at its clock input, the output signal Cmp1 from the first comparator C1 and the second flip-flop D2 receives the output signal Cmp2 from the second comparator C2. The output signal CLK_2 from the frequency divider circuit 46 is sent to the D-input of each of the flip-flops D1 and D2.

(22) The operation of the circuit will now be explained with the aid of the exemplary timing diagrams of FIG. 5.

(23) The first timing diagram corresponds to the ramp signal V.sub.rampe. The next two timing diagrams show the signals as output from the first and second comparators C1, C2, respectively. The fourth and fifth timing diagrams illustrate the first clock signal CLK as input to the frequency divider circuit 46 and the output signal CLK_2 from said divider, respectively. The first clock signal CLK is synchronized with the ramp signal and the frequency of the output signal CLK_2 is divided by two with respect to the input signal CLK of the frequency divider circuit 46. The last two timing diagrams show the signals as output from the two flip-flops D1, D2.

(24) At time t.sub.1, the value of the ramp signal becomes higher than the value of the first threshold voltage V.sub.S1, the output signal from the first comparator C1 passes from the low state to the high state. The first flip-flop D1 detects the rising edge and reproduces, as output, the value of the second clock signal CLK_2, namely a high state, the signal as output from the flip-flop D1 therefore passes from the low state to the high state.

(25) At time t.sub.2, the value of the ramp signal becomes higher than the value of the second threshold voltage V.sub.S2. The output signal from the second comparator C2 therefore passes from the low state to the high state. The second flip-flop D2 is triggered and its output signal takes the same value as the second clock signal CLK_2, namely a high state.

(26) At time t.sub.3, the value of the ramp signal returns to zero, the output signals from the two comparators C1, C2 pass from the high state to the low state.

(27) At time t.sub.4, the value of the ramp signal once more becomes higher than the value of the first threshold voltage V.sub.S1, the output signal from the first comparator C1 passes to the high state and triggers the first flip-flop D1 which reproduces the value of the second clock signal CLK_2 as output. Its output signal passes from the high state to the low state.

(28) Likewise, at time t.sub.5, as the value of the ramp signal becomes higher than the value of the second threshold voltage V.sub.S2 it triggers a rising edge as output from the second comparator C2. This rising edge triggers the second flip-flop D2 and its output signal passes from the high state to the low state.

(29) Thus, two rectangular clock signals that are phase-shifted in time are obtained as output from the circuit 40. The phase shift between the two signals may be adjusted by modifying the value of the two threshold voltages V.sub.S1 et V.sub.S2. As shown above, the range of variation in the phase shift depends on the duty cycle of the ramp signal.

(30) Of course, this circuit 40 may be generalized to a number of rectangular signals that is greater than two. For a number n of rectangular signals phase-shifted in time, where n represents an integer that is greater than one, the circuit will comprise n comparators and n D-type flip-flops and will receive n threshold voltages as input.

(31) FIG. 6 illustrates, with exemplary timing diagrams, the case in which interference 30 occurs in the output signal Cmp1_Pb from the first comparator C1 of the circuit 40 of FIG. 4. In this figure, a ramp signal, the signal as output from the first comparator C1, an output signal CLK_2 from the frequency divider circuit 46, an output signal from the second flip-flop D2 and an output signal from the second flip-flop D2 in the case without interference are shown, respectively.

(32) It is assumed that an interference signal 30 occurs at time t.sub.1 in the output signal from the first comparator C1. The rising edge of this interference 30 triggers the flip-flop D1 which reproduces the value of the second clock signal CLK_2, namely a high state. The output signal S.sub.1.sub._.sub.Pb from the flip-flop D1 therefore changes state at time t.sub.1 instead of time t.sub.2.

(33) At time t.sub.2, the output signal from the comparator C1 has a rising edge once again. By detecting this rising edge, the flip-flop D1 reproduces the signal CLK_2 and remains in the high state. In contrast to the case of the circuit shown in FIG. 1, the output signal S.sub.1.sub._.sub.Pb does not change state on each rising edge that is present in the output signal from the comparator. Likewise, it may be noted that the output signal S.sub.1.sub._.sub.Pb is not disrupted definitively, but only temporarily. The rising edge following the interference signal 30 allows the flip-flop output signal S.sub.1 to be brought back to its normal level, i.e. to the logic state that it would have had if it there had not been any interference 30 in the output signal from the comparator C1.

(34) It may also be noted that depending on the instant at which the interference signal 30 occurs, it is possible that the latter not disrupt the signal output from the flip-flop. For example, the interference signal at instant t.sub.4 has no effect on the output signal S.sub.1.

(35) According to a wholly non-limiting example, this circuit may be applicable in a phase-shifted power converter. By way of illustration, FIG. 7 shows an exemplary embodiment of a phase-shifted power converter wherein a phase shift between the primary and secondary bridge legs is produced using a circuit 40 for generating at least two rectangular signals with adjustable phase shift according to one embodiment of the invention. In this circuit, the output signals S.sub.1, S.sub.2 from the circuit 40 for generating rectangular signals with adjustable phase shift are configured to control the various switches of the primary and secondary bridges of the power converter.

(36) Advantageously, the signal generation circuit according to the invention allows problems with synchronizing flip-flops, as well as problems linked to resetting flip-flops, to be overcome.

(37) This circuit also allows the consequences of one or more interference pulses to be minimized.