VIDEO PROCESSING CIRCUIT FOR PERFORMING SIZE-BASED PARALLEL IN PARALLEL OUT COMPUTATION WITH BUBBLE CYCLE REDUCTION

Abstract

A video processing circuit includes a first buffer and a computation circuit. Before a second one-dimensional processing operation is performed upon a plurality of consecutive blocks in a second direction, the first computation circuit generates a first processing result for each of the plurality of consecutive blocks by performing a first one-dimensional processing operation upon each of the plurality of consecutive blocks in a first direction that is different from the second direction, and further stores a plurality of first processing results of the plurality of consecutive blocks into the first buffer.

Claims

1. A video processing circuit comprising: a first buffer; and a first computation circuit, wherein before a second one-dimensional processing operation is performed upon a plurality of consecutive blocks in a second direction, the first computation circuit is arranged to generate a first processing result for each of the plurality of consecutive blocks by performing a first one-dimensional processing operation upon said each of the plurality of consecutive blocks in a first direction that is different from the second direction, and is further arranged to store a plurality of first processing results of the plurality of consecutive blocks into the first buffer.

2. The video processing circuit of claim 1, wherein after the first one-dimensional processing operation is performed upon the plurality of consecutive blocks, the first computation circuit retrieves each of the plurality of first processing results from the first buffer, and is reused to perform the second one-dimensional processing operation upon said each of the plurality of consecutive blocks according to the first processing result that is generated by the first one-dimensional processing operation for said each of the plurality of consecutive blocks.

3. The video processing circuit of claim 1, further comprising: a stage decision making switch circuit, arranged to set input data of the first computation circuit by adaptively switching between non-transposed data of the plurality of consecutive blocks provided from a previous stage of the video processing circuit and transposed data of the plurality of consecutive blocks provided from the first buffer.

4. The video processing circuit of claim 3, wherein the stage decision making switch circuit comprises: a second buffer, arranged to buffer information of the plurality of consecutive blocks that is provided from the previous stage; the stage decision making switch circuit refers to the information in the second buffer for adaptively selecting one of the non-transposed data and the transposed data as the input data of the first computation circuit.

5. The video processing circuit of claim 3, wherein the stage decision making switch circuit is further arranged to refer to a buffer status of the first buffer for adaptively selecting one of the non-transposed data and the transposed data as the input data of the first computation circuit.

6. The video processing circuit of claim 3, further comprising: a third buffer, coupled between the stage decision making switch circuit and the first computation circuit, wherein output data of the stage decision making switch circuit is serially pushed into the third buffer, all data of a complete line included in said each of the plurality of consecutive blocks is popped from the third buffer and transmitted to the first computation circuit in a parallel fashion, and the third buffer buffers data belonging to different lines at a same time.

7. The video processing circuit of claim 3, further comprising: a fourth buffer, coupled between the first computation circuit and a latter stage of the video processing circuit and also coupled between first computation circuit and the first buffer, wherein all data of a complete line included in said each of the plurality of consecutive blocks is generated from the first computation circuit and pushed into the fourth buffer in a parallel fashion, data buffered in the fourth buffer is serially popped from the fourth buffer, and the fourth buffer buffers data belonging to different lines at a same time.

8. The video processing circuit of claim 1, further comprising: a second computation circuit, arranged to retrieve each of the plurality of first processing results from the first buffer, and perform the second one-dimensional processing operation upon said each of the plurality of consecutive blocks in the second direction according to the first processing result that is generated by the first one-dimensional processing operation for said each of the plurality of consecutive blocks.

9. The video processing circuit of claim 8, further comprising: a fifth buffer, coupled between a previous stage of the video processing circuit and the first computation circuit, wherein output data of the previous stage is serially pushed into the fifth buffer, all data of a complete line included in said each of the plurality of consecutive blocks is popped from the fifth buffer and transmitted to the first computation circuit in a parallel fashion, and the fifth buffer buffers data belonging to different lines at a same time.

10. The video processing circuit of claim 8, further comprising: a sixth buffer, coupled between the first computation circuit and the first buffer, wherein all data of a complete line included in said each of the plurality of consecutive blocks is generated from the first computation circuit and pushed into the sixth buffer in a parallel fashion, data buffered in the sixth buffer is serially popped from the sixth buffer, and the sixth buffer buffers data belonging to different lines at a same time.

11. The video processing circuit of claim 8, further comprising: a seventh buffer, coupled between the first buffer and the second computation circuit, wherein output data of the first buffer is serially pushed into the seventh buffer, all data of a complete line included in said each of the plurality of consecutive blocks is popped from the seventh buffer and transmitted to the second computation circuit in a parallel fashion, and the seventh buffer buffers data belonging to different lines at a same time.

12. The video processing circuit of claim 8, further comprising: an eighth buffer, coupled between the second computation circuit and a latter stage of the video processing circuit, wherein all data of a complete line included in said each of the plurality of consecutive blocks is generated from the second computation circuit and pushed into the eighth buffer in a parallel fashion, data buffered in the eighth buffer is serially popped from the eighth buffer, and the eighth buffer buffers data belonging to different lines at a same time.

13. The video processing circuit of claim 1, wherein the video processing circuit is an inverse transform circuit or a transform circuit.

14. The video processing circuit of claim 1, wherein the first buffer is a ring first in, first out (FIFO) buffer.

15. A video processing circuit comprising: a computation circuit, arranged to generate a processing result for each of a plurality of consecutive blocks by performing a one-dimensional processing operation upon said each of the plurality of consecutive blocks in one direction; and a buffer, coupled to the computation circuit, wherein input data of the buffer is serially pushed into the buffer, all data of a complete line included in said each of the plurality of consecutive blocks is popped from the buffer and transmitted to the computation circuit in a parallel fashion, and the buffer buffers data belonging to different lines at a same time.

16. The video processing circuit of claim 15, wherein the video processing circuit is an inverse transform circuit or a transform circuit.

17. A video processing circuit comprising: a computation circuit, arranged to generate a processing result for each of a plurality of consecutive blocks by performing a one-dimensional processing operation upon said each of the plurality of consecutive blocks in one direction; and a buffer, coupled to the computation circuit, wherein all data of a complete line included in said each of the plurality of consecutive blocks is generated from the computation circuit and pushed into the buffer in a parallel fashion, data buffered in the buffer is serially popped from the buffer, and the buffer buffers data belonging to different lines at a same time.

18. The video processing circuit of claim 17, wherein the video processing circuit is an inverse transform circuit or a transform circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a diagram illustrating a video encoding apparatus according to an embodiment of the present invention.

[0011] FIG. 2 is a block diagram illustrating a video decoding apparatus according to an embodiment of the present invention.

[0012] FIG. 3 is a diagram illustrating an SPIPO computation procedure according to an embodiment of the present invention.

[0013] FIG. 4 is a diagram illustrating a video processing circuit with high performance serial architecture according to an embodiment of the present invention.

[0014] FIG. 5 is a flowchart illustrating a stage decision making method according to an embodiment of the present invention.

[0015] FIG. 6 is a timing diagram of a conventional design with degraded performance due to the bubble cycle issue resulting from switching between the 1.sup.st stage and the 2.sup.nd stage.

[0016] FIG. 7 is a timing diagram of the video processing circuit shown in FIG. 4.

[0017] FIG. 8 is a diagram illustrating another video processing circuit with high performance serial architecture according to an embodiment of the present invention.

[0018] FIG. 9 is a diagram illustrating an example of the SIVO buffer shown in FIG. 8.

[0019] FIG. 10 is a diagram illustrating an example of the VISO buffer shown in FIG. 8.

[0020] FIG. 11 is a flowchart illustrating a data transfer method according to an embodiment of the present invention.

[0021] FIG. 12 is a timing diagram of a conventional design with degraded performance due to the bubble cycle issue resulting from switching from a small block to a large block.

[0022] FIG. 13 is a timing diagram of the video processing circuit shown in FIG. 8.

[0023] FIG. 14 is a diagram illustrating a video processing circuit with high performance parallel architecture according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0024] Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

[0025] FIG. 1 is a diagram illustrating a video encoding apparatus according to an embodiment of the present invention. The video encoding apparatus 100 is a hardware circuit used to compress raw video data to generate compressed video data. It should be noted that the video encoder architecture shown in FIG. 1 is for illustrative purposes only, and is not meant to be a limitation of the present invention. For example, the architecture of the video encoding apparatus 100 may vary, depending upon the coding standard. The video encoding apparatus 100 encodes one frame IMG to generate one bitstream BS for transmission. As shown in FIG. 1, the video encoding apparatus 100 includes a residual calculation circuit 101, a transform circuit (labeled by “T”) 102, a quantization circuit (labeled by “Q”) 103, an entropy encoding circuit (labeled by “Entropy encode”) 104, an inverse quantization circuit (labeled by “IQ”) 105, an inverse transform circuit (labeled by “IT”) 106, a reconstruction circuit 107, an in-loop filter (e.g. a deblocking filter 108, labeled by “DBF”), a reference frame buffer 109, an inter prediction circuit 110 (which includes a motion estimation circuit (labeled by “ME”) 111 and a motion compensation circuit (labeled by “MC”) 112), an intra prediction circuit (labeled by “IP”) 113, and an intra/inter mode selection switch 114. One or both of the transform circuit 102 and the inverse transform circuit 106 may be implemented by the proposed size-based parallel in and parallel out (SPIPO) computation architecture. Since the present invention is focused on SPIPO computation (e.g. transform and/or inverse transform) and a person skilled in the art should readily understand principles of the rest of function blocks in the video encoding apparatus 100, further description of the video encoding apparatus 100 is omitted here for brevity.

[0026] FIG. 2 is a block diagram illustrating a video decoding apparatus according to an embodiment of the present invention. The video decoding apparatus 200 is a hardware circuit used to decompress encoded video data carried by the bitstream BS to generate decompressed video data. It should be noted that the video decoder architecture shown in FIG. 2 is for illustrative purposes only, and is not meant to be a limitation of the present invention. For example, the architecture of the video decoding apparatus 200 may vary, depending upon the coding standard. As shown in FIG. 2, the video decoding apparatus 200 may include an entropy decoding circuit (e.g. a variable length decoding circuit 202, labeled by “VLD”), an inverse scan circuit (labeled by “IS”) 204, an inverse quantization circuit (labeled by “IQ”) 206, an inverse transform circuit (labeled by “IT”) 208, a reconstruction circuit 210, an in-loop filter (e.g. de-blocking filter 212, labeled by “DBF”), a decoded picture buffer (DPB) 214, an intra prediction circuit (labeled by “IP”) 216, a motion vector calculation circuit (labeled by “MV calculation”) 218, a motion compensation circuit (labeled by “MC”) 220, and an inter/intra selection circuit (labeled by Inter/intra selection”) 222. The inverse transform circuit 208 may be implemented by the proposed SPIPO computation architecture. Since the present invention is focused on SPIPO computation (e.g. transform and/or inverse transform) and a person skilled in the art should readily understand principles of the rest of function blocks in the video decoding apparatus 200, further description of the video decoding apparatus 200 is omitted here for brevity.

[0027] FIG. 3 is a diagram illustrating an SPIPO computation procedure according to an embodiment of the present invention. The transform circuit 102 may follow the SPIPO computation procedure. Similarly, the inverse transform circuit 106/208 may also follow the SPIPO computation procedure. The SPIPO computation procedure includes two stages, including a 1.sup.st stage performed for one of a horizontal 1D transform and a vertical 1D transform, and a 2.sup.nd stage performed for the other of the horizontal 1D transform and the vertical 1D transform. One picture/frame may be divided into a plurality of coding units (CUs), each CU may be divided into a plurality of transform units (TUs), and each TU may consist of multiple transform blocks (TBs). For example, one TU may consist of one luma TB and two chroma TBs. One line of a transform block in a first direction (e.g. one column in the vertical direction) is processed by the 1.sup.st stage, and one line of the transform block in a second direction (e.g. one row in the horizontal direction) is processed by the 2.sup.nd stage. Hence, a transpose memory (TM) buffer 302 is used to buffer output data of the 1.sup.st stage (e.g. vertical 1D transform), and provide transposed data as input data of the 2.sup.nd stage (e.g. horizontal 1D transform).

[0028] FIG. 4 is a diagram illustrating a video processing circuit with high performance serial architecture according to an embodiment of the present invention. For example, the transform circuit 102 of the video encoding apparatus 100 may be implemented by the video processing circuit 400. For another example, the inverse transform circuit 106 of the video encoding apparatus 100 may be implemented by the video processing circuit 400. For yet another example, the inverse transform circuit 208 of the video decoding apparatus 200 may be implemented by the video processing circuit 400. In accordance with the high performance serial architecture, the video processing circuit 400 includes an SPIPO computation circuit 402, a stage decision making switch circuit 404, and a ring first in, first output (FIFO) TM buffer 406. The SPIPO computation circuit 402 is a transform kernel that can deal with transform from a spatial domain to a frequency domain or inverse transform from a frequency domain to a spatial domain. The SPIPO computation circuit 402 may include a plurality of transform logic circuits (labeled by “Transform logic”) 408_1-408_n for a plurality of coding standards, respectively. For example, the transform logic circuit 408_1 is designed for dealing with transform/inverse transform in compliance with versatile video coding (VVC) standard (also known as H.266 standard), and the transform logic circuit 408_n is designed for dealing with transform/inverse transform in compliance with a different video coding standard.

[0029] To address the bubble cycle issue resulting from switching between the 1.sup.st stage and the 2.sup.nd stage, the SPIPO computation circuit 402 is designed to support processing of consecutive blocks (i.e. consecutive TBs) in a row at the same stage, the ring FIFO TM buffer 406 is designed to support buffering of 1.sup.st stage processing results of consecutive blocks (i.e. consecutive TBs), and/or the stage decision making switch circuit 404 is designed to support adaptive switching between 1.sup.st stage processing and 2.sup.nd stage processing. In this embodiment, the SPIPO computation circuit 402 is used to deal with a first one-dimensional processing operation in a first direction (e.g. 1.sup.st stage transform in a vertical direction), and is re-used to deal with a second one-dimensional processing operation in a second direction (e.g. 2.sup.nd stage transform in a horizontal direction) for saving the computation resource. Before the 2.sup.nd stage processing operation (e.g. horizontal 1D transform) is performed upon a plurality of consecutive blocks (e.g. BLK0, BLK1, and BLK2) in the second direction (e.g. horizontal direction), the SPIPO computation circuit 402 generates a 1.sup.st stage processing result for each of the consecutive blocks (e.g. BLK0, BLK1, and BLK2) by performing the first one-dimensional processing operation (e.g. 1.sup.st stage transform in a horizontal direction), and stores a plurality of 1.sup.st stage processing results of the consecutive blocks (e.g. BLK0, BLK1, and BLK2) into the ring FIFO TM buffer 406. Regarding the ring FIFO TM buffer 406, one write pointer PTR W can be updated to point to a next address at which new data should be stored, and one read pointer PTR R can be updated to point to a next address at which stored data should be read. The buffer size of the ring FIFO TM buffer 406 may be properly set to accommodate the 1.sup.st stage processing result of a transform block with a largest transform block size (e.g. 64×64). In accordance with VVC standard, the possible width and height of one transform block range from 1, 2, 4, 8, 16, 32, to 64. Hence, when the consecutive blocks (e.g. BLK0, BLK1, and BLK2) are small blocks (e.g. 4×4 blocks), the ring FIFO TM buffer 406 can be used to store 1.sup.st stage processing results of consecutive blocks (e.g. BLK0, BLK1, and BLK2) before the 1.sup.st stage processing results are transposed and output to the SPIPO computation circuit 402 for undergoing the 2.sup.nd stage processing.

[0030] The stage decision making switch circuit 404 controls an input data source to be adaptively switched between a previous stage and the ring FIFO TM buffer 406. In a case where the stage decision making switch circuit 404 selects the previous stage as the input data source of the SPIPO computation circuit 402, the SPIPO computation circuit 402 enables the 1.sup.st stage for processing the non-transposed data from the previous stage to generate and output 1.sup.st stage processing results of consecutive blocks to the ring FIFO TM buffer 406. In another case where the stage decision making switch circuit 404 selects the ring FIFO TM buffer 406 as the input data source of the SPIPO computation circuit 402, the SPIPO computation circuit 402 enables the 2.sup.nd stage for processing the transposed data from the ring FIFO TM buffer 406 to provide a latter stage with output data of the consecutive blocks. For example, the previous stage is the residual calculation circuit 101 and the latter stage is the quantization circuit 103 when the video processing circuit 400 is used as the transform circuit 102. For another example, the previous stage is the inverse quantization circuit 105 and the latter stage is the reconstruction circuit 107 when the video processing circuit 400 is used as the inverse transform circuit 106. For yet another example, the previous stage is the inverse quantization circuit 206 and the latter stage is the reconstruction circuit 210 when the video processing circuit 400 is used as the inverse transform circuit 208.

[0031] In this embodiment, the stage decision making switch circuit 404 may include a look-ahead buffer 410 arranged to buffer information of the consecutive blocks (e.g. BLK0, BLK1, and BLK2) that is provided from the previous stage. The information stored into the look-ahead buffer 410 by the previous stage may include the number of consecutive blocks (e.g. BLK0, BLK1, and BLK2) ready to be transferred from the previous stage to the video processing circuit 400, the block size of each of the consecutive blocks (e.g. BLK0, BLK1, and BLK2), etc. The stage decision making switch circuit 404 refers to the information in the look-ahead buffer 410 for adaptively selecting one of the non-transposed data (which is provided from the previous stage) and the transposed data (which is provided from the ring FIFO TM buffer 406) as the input data of the SPIPO computation circuit 402.

[0032] FIG. 5 is a flowchart illustrating a stage decision making method according to an embodiment of the present invention. The stage decision making method may be employed by the stage decision making circuit 404. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 5. Initially, the stage decision making circuit 404 enters an idle state (Step 502). At step 504, the stage decision making circuit 404 checks if the look-ahead buffer 410 is empty. If yes, the stage decision making circuit 404 enters the idle state to wait for information provided from the previous stage. If no, the stage decision making circuit 404 selects the non-transposed data transmitted from the previous stage as the input data of the SPIPO computation circuit 402, thereby enabling the 1.sup.st stage transform at the SPIPO computation circuit 402 (Step 506). At step 508, the stage decision making circuit 404 checks if the ring FIFO TM buffer 406 is full or the look-ahead buffer 410 becomes empty. If the ring FIFO TM buffer 406 is full, it implies that the ring FIFO TM buffer 406 is unable to buffer more 1.sup.st stage processing results, and the SPIPO computation circuit 402 should pause the 1.sup.st stage transform and enable the 2.sup.nd stage transform for processing any 1.sup.st stage processing result buffered in the ring FIFO TM buffer 406. If the look-ahead buffer 410 becomes empty, it implies that there is no non-transposed data waiting to undergo the 1.sup.st stage transform at this moment, and the SPIPO computation circuit 402 should end the 1.sup.st stage transform and enable the 2.sup.nd stage transform for processing any 1.sup.st stage processing result buffered in the ring FIFO TM buffer 406. At step 510, the stage decision making circuit 404 selects the transposed data transmitted from the ring FIFO TM buffer 406 as the input data of the SPIPO computation circuit 402, thereby enabling the 2.sup.nd stage transform at the SPIPO computation circuit 402. At step 512, the stage decision making circuit 404 checks if the ring FIFO TM buffer 406 is empty. If the ring FIFO TM buffer 406 is not empty yet, the stage decision making circuit 404 keeps transferring the transposed data from the ring FIFO TM buffer 406 to the SPIPO computation circuit 402. If the ring FIFO TM buffer 406 becomes empty, it implies that each 1.sup.st stage processing result in the ring FIFO TM buffer 406 has been transposed and output to the SPIPO computation circuit 402 for 2.sup.nd stage transform. Hence, the flow proceeds with step 504.

[0033] After a 1.sup.st stage processing result of a block is stored into the ring FIFO TM buffer 406, the ring FIFO TM buffer 406 requires some clock cycles to process the 1.sup.st stage processing result for preparing and outputting transposed data to undergo the 2.sup.nd stage transform. Since the SPIPO computation circuit 402 can apply 1.sup.st stage transform to consecutive blocks, the clock cycles needed by the ring FIFO TM buffer 406 for preparing transposed data of the first block of the consecutive blocks may be hidden in the clock cycles needed by the SPIPO computation circuit 402 for performing 1.sup.st stage transform upon other block(s) of the consecutive blocks, thereby solving the bubble cycle issue resulting from switching between the 1.sup.st stage and the 2.sup.nd stage. Please refer to FIG. 6 in conjunction with FIG. 7. FIG. 6 is a timing diagram of a conventional design with degraded performance due to the bubble cycle issue resulting from switching between the 1.sup.st stage and the 2.sup.nd stage. FIG. 7 is a timing diagram of the video processing circuit 400 shown in FIG. 4. Compared to the conventional design, the proposed high performance serial architecture enables the transform circuit 102 and/or the inverse transform circuit 106/208 to have better performance due to bubble cycle reduction.

[0034] FIG. 8 is a diagram illustrating another video processing circuit with high performance serial architecture according to an embodiment of the present invention. For example, the transform circuit 102 of the video encoding apparatus 100 may be implemented by the video processing circuit 800. For another example, the inverse transform circuit 106 of the video encoding apparatus 100 may be implemented by the video processing circuit 800. For yet another example, the inverse transform circuit 208 of the video decoding apparatus 200 may be implemented by the video processing circuit 800. The major difference between the video processing circuits 400 and 800 is that the video processing circuit 800 further includes a serial in variable out (SIVO) buffer 802 and a variable in serial out (VISO) buffer 804.

[0035] The SIVO buffer 802 is coupled between the stage decision making switch circuit 404 and the SPIPO computation circuit 402. The output data of the stage decision making switch circuit 404 is serially pushed into the SIVO buffer 802 in a constant throughput, and all data of a complete line included in each of the consecutive blocks (e.g. BLK0, BLK2, and BLK2) is popped from the SIVO buffer 802 and transmitted to the SPIPO computation circuit 402 in a parallel fashion.

[0036] The VISO buffer 804 is coupled between the SPIPO computation circuit 402 and the ring FIFO TM buffer 406, and is also coupled between the SPIPO computation circuit 402 and a latter stage. All data of a complete line included in each of the consecutive blocks (e.g. BLK0, BLK2, and BLK2) is generated from the SPIPO computation circuit 402 and pushed into the VISO buffer 804 in a parallel fashion, and data buffered in the VISO buffer 804 is serially popped from the VISO buffer 804 to a latter stage or the ring FIFO TM buffer 406 in a constant throughput.

[0037] To address the bubble cycle issue resulting from switching from a small block to a large block, the SIVO buffer 802 is designed to have a buffer size large enough to buffer data belonging to different lines at the same time, and the VISO buffer 804 is designed to have a buffer size large enough to buffer data belonging to different lines at the same time. Specifically, a spare buffer size of the SIVO buffer 802/VISO buffer 804 can be used for bubble cycle reduction. FIG. 9 is a diagram illustrating an example of the SIVO buffer 802 shown in FIG. 8. FIG. 10 is a diagram illustrating an example of the VISO buffer 804 shown in FIG. 8. The SPIPO computation circuit 402 needs to wait for a complete line (e.g., a complete row or a complete column) to start the computation, and generates and outputs a processing result of the complete line, where the possible width and height of one transform block may range from 1, 2, 4, 8, 16, 32, to 64 in VVC. In a case where the transform block size is 4×4, the SIVO buffer 802 outputs 4 samples (non-transposed data or transposed data) to the SPIPO computation circuit 402 in a parallel fashion when all of the 4 samples are ready in the SIVO buffer 802, and the SPIPO computation circuit 402 outputs 4 samples to the VISO buffer 804 in a parallel fashion when all of the 4 samples are ready in the SPIPO computation circuit 402. In another case where the transform block size is 8×8, the SIVO buffer 802 outputs 8 samples (non-transposed data or transposed data) to the SPIPO computation circuit 402 in a parallel fashion when all of the 8 samples are ready in the SIVO buffer 802, and the SPIPO computation circuit 402 outputs 8 samples to the VISO buffer 804 in a parallel fashion when all of the 8 samples are ready in the SPIPO computation circuit 402. The spare buffer size in the SIVO buffer 802 can be used to buffer samples of other line(s). Similarly, the spare buffer size in the VISO buffer 804 can be used to buffer samples of other line(s).

[0038] FIG. 11 is a flowchart illustrating a data transfer method according to an embodiment of the present invention. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown in FIG. 11. Initially, the SIVO buffer 802 and the VISO buffer 804 enter an idle state (Step 1102). At step 1104, the stage decision making circuit 404 pushes data into the SIVO buffer 802 in a constant throughput. At step 1106, the SIVO buffer 802 determines if it has data of at least one variable-size line. If the SIVO buffer 802 does not have data of at least one variable-size line, the flow proceeds with step 1104. If the SIVO buffer 802 has data of at least one variable-size line, the SIVO buffer 802 pops data of one complete variable-size line and pushes the data of one complete variable-size line into the SPIPO computation circuit 402 for 1.sup.st stage processing or 2.sup.nd stage processing (Step 1108). At step 1110, the SPIPO computation circuit 402 generates processed data of one complete variable-size line, and pushes the processed data of one complete variable-size line into the VISO buffer 804.

[0039] After a 2.sup.nd stage processing result of a last complete line of a current block is generated by the SPIPO computation circuit 402, the SPIPO computation circuit 402 needs to wait for a 1.sup.st complete line of a next block to be ready, and the ring FIFO TM buffer 406 needs to wait for a 1.sup.st stage processing result of the 1.sup.st complete line of the next block to be ready. With the help of the SIVO buffer 802 and/or the VISO buffer 804, the data preparation may be hidden in the clock cycles needed by the SPIPO computation circuit 402 for performing 1.sup.st stage transform and 2.sup.nd stage transform. Please refer to FIG. 12 in conjunction with FIG. 13. FIG. 12 is a timing diagram of a conventional design with degraded performance due to the bubble cycle issue resulting from switching from a small block to a large block. FIG. 13 is a timing diagram of the video processing circuit 800 shown in FIG. 8. Compared to the conventional design, the proposed high performance serial architecture enables the transform circuit 102 and/or the inverse transform circuit 106/208 to have better performance due to bubble cycle reduction.

[0040] The video processing circuit 800 with the high performance serial architecture may be employed by a video decoder to achieve 4K @ 60 FPS (frames per second). For certain video applications that require 8K @ 30 FPS, the present invention proposes high performance parallel architecture.

[0041] FIG. 14 is a diagram illustrating a video processing circuit with high performance parallel architecture according to an embodiment of the present invention. For example, the transform circuit 102 of the video encoding apparatus 100 may be implemented by the video processing circuit 1400. For another example, the inverse transform circuit 106 of the video encoding apparatus 100 may be implemented by the video processing circuit 1400. For yet another example, the inverse transform circuit 208 of the video decoding apparatus 200 may be implemented by the video processing circuit 1400. Compared to the high performance serial architecture having one common SPIPO computation circuit 402 shared by 1.sup.st stage transform and 2.sup.nd stage transform, the high performance parallel architecture employs two SPIPO computation circuits dedicated to 1.sup.st stage transform and 2.sup.nd stage transform, respectively. As shown in FIG. 14, the video processing circuit 1400 includes two SPIPO computation circuits 402_1, 402_2 each having the same architecture of the SPIPO computation circuit 402, the ring FIFO TM buffer 406, two SIVO buffers 802_1, 802_2 each having the same architecture of SIVO buffer 802, and two VISO buffers 804_1, 804_2 each having the same architecture of VISO buffer 804.

[0042] To address the bubble cycle issue resulting from switching between the 1.sup.st stage and the 2.sup.nd stage, each of the SPIPO computation circuits 402_1, 402_2 is designed to support processing of consecutive blocks (i.e. consecutive TBs) in a row at the same stage, and the ring FIFO TM buffer 406 is designed to support buffering of 1.sup.st stage processing results of consecutive blocks (i.e. consecutive TBs). To address the bubble cycle issue resulting from switching from a small block to a large block, each of the SIVO buffers 802_1, 802_2 is designed to have a buffer size large enough to buffer data belonging to different lines at the same time, and each of the VISO buffers 804_1, 804_2 is designed to have a buffer size large enough to buffer data belonging to different lines at the same time. Since a person skilled in the pertinent art can readily understand technical features of the video processing circuit 1400 after reading paragraphs directed to the video processing circuits 400 and 800, further description is omitted here for brevity.

[0043] In above embodiments, a video processing circuit (e.g. transform circuit or inverse transform circuit) may employ all techniques proposed by the present invention to address both of the bubble cycle issues. However, these are for illustrative purposes only, and are not meant to be limitations of the present invention. For example, a video processing circuit (e.g. transform circuit or inverse transform circuit) may employ some of the techniques proposed by the present invention to address only one of the bubble cycle issues. These alternative designs all fall within the scope of the present invention.

[0044] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.