REFERENCE VOLTAGES

Abstract

A voltage reference circuit comprises a voltage-controlled current source; a first reference metal-oxide-semiconductor field-effect transistor having a first threshold voltage; a second reference metal-oxide-semiconductor field-effect transistor having a second threshold voltage, wherein the second threshold voltage is different to the first threshold voltage; a current mirror; and a load. The voltage-controlled current source is arranged to generate a first current proportional to a difference between the first and second threshold voltages, and the current mirror is arranged to generate a second current that is a scaled version of the first current through the load so as to produce a reference voltage.

Claims

1. A voltage reference circuit comprising: a voltage-controlled current source; a first reference metal-oxide-semiconductor field-effect transistor having a first threshold voltage; a second reference metal-oxide-semiconductor field-effect transistor having a second threshold voltage, said second threshold voltage being different to said first threshold voltage; a current mirror; and a load, wherein the voltage-controlled current source is arranged to generate a first current proportional to a difference between said first and second threshold voltages, and the current mirror is arranged to generate a second current that is a scaled version of the first current through the load so as to produce a reference voltage.

2. The voltage reference circuit as claimed in claim 1, wherein the voltage-controlled current source is an operational transconductance amplifier.

3. The voltage reference circuit as claimed in claim 1, wherein said first threshold voltage is greater than said second threshold voltage.

4. The voltage reference circuit as claimed in claim 3, wherein the first threshold voltage is between 300 mV and 800 mV.

5. The voltage reference circuit as claimed in claim 3, wherein the second threshold voltage is between 200 mV and 700 mV.

6. The voltage reference circuit as claimed in claim 1, wherein the load is resistive.

7. The voltage reference circuit as claimed in claim 6, wherein the load is a variable resistor.

8. The voltage reference circuit as claimed in claim 1, wherein the current mirror comprises a first mirror transistor and a second mirror transistor.

9. The voltage reference circuit as claimed in claim 8, wherein the first mirror transistor is in a diode-connected configuration.

10. The voltage reference circuit as claimed in claim 8, wherein the second mirror transistor is in a common source configuration.

11. The voltage reference circuit as claimed in claim 8, wherein the first mirror transistor has a first width and the second mirror transistor has a second width, wherein said first and second widths are different.

12. The voltage reference circuit as claimed in claim 8, wherein the first mirror transistor has a first width and the second mirror transistor has a second width, wherein the first and second widths are the same.

13. The voltage reference circuit as claimed in claim 8 wherein the first mirror transistor and a second mirror transistor are arranged such that their respective gate terminals are connected to a shared gate voltage.

14. The voltage reference circuit as claimed in claim 1, wherein the current mirror comprises a first mirror transistor and a second mirror transistor, wherein the first mirror transistor has a first width and the second mirror transistor has a second width, wherein said first and second widths are different.

Description

[0019] An embodiment of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0020] FIG. 1 shows a circuit diagram of a voltage reference circuit in accordance with the present invention; and

[0021] FIG. 2 shows a simulated graph of the reference voltage as a function of temperature across a typical operating range.

[0022] FIG. 1 shows a circuit diagram of a voltage reference circuit 1 in accordance with the present invention. The voltage reference circuit 1 comprises an operational amplifier 2 configured as an operational transconductance amplifier; an HVT transistor 4; an SVT transistor 6; first and second current source transistors 8, 10; a current mirror transistor 12, a fixed resistor 14, and a digitally controllable variable resistor 16 having a digital control input 18.

[0023] The first and second current source transistors 8, 10 supply the HVT and SVT transistors 4, 6 respectively with current, which in turn generate input voltages 20, 22 that are supplied to the operational amplifier 2. The HVT and SVT transistors 4, 6 are arranged such that their individual gate and drain terminals are connected, and are further connected to the non-inverting and inverting inputs of the operational amplifier 2 respectively. In the case of the SVT transistor 6, the common gate and drain terminals are connected to the inverting input of the operational amplifier 2 via the fixed resistor 14.

[0024] The current supplied by the second current source transistor 10 passes through the fixed resistor 14 and generates a voltage drop across it in accordance with Ohm's law. This voltage drop provides the inverting input 22 to the operational amplifier 2. As the amplifier output voltage 26 from the operational amplifier 2 is connected to the gates of the first and second current source transistors 8, 10, the channel widths of said transistors are altered so as to drive the non-inverting and inverting input voltages 20, 22 toward convergence. Since the HVT and SVT transistors 4, 6 have different threshold voltages due to their physical differences, the difference in the voltages 20, 22 must be compensated for by altering the voltage drop across the fixed resistor 14.

[0025] The current mirror transistor 12 is physically wider than the second current source transistor 10 by a factor B. Due to this difference in widths, the current through the current mirror transistor 12 is B times greater than the current through the second current source transistor 10. This greater mirrored current is then passed through the variable resistor 16, producing the reference voltage output 24.

[0026] An n-bit digital control signal 18 is supplied to the variable resistor 16, which in turn causes the resistance to change as desired. This variable resistance allows for fine tuning of the reference voltage output 24 at run-time.

[0027] Thus it can be seen that the reference voltage output 24 is based on the threshold voltage difference between the HVT and SVT transistors 4, 6.

[0028] Here it is assumed that the HVT and SVT transistors 4, 6 are in weak inversion. This means that the potential difference across the gate and source terminals of each transistor is less than the threshold voltage of said transistor (i.e. V.sub.Gs<V.sub.th). As such, the transistors are operating within their respective subthreshold regions and their respective drain currents are given by Equation 1, recited from Solid State Electronic Devices (Streetman Banerjee, page 311).

[00001]$\begin{array}{cc}{I}_D=\left(C_D+C_{\mathrm{it}}\right).Math.\frac{W}{L}.Math.{\left(\frac{\mathrm{KT}}{q}\right)}^2.Math.\left(1-e^{\frac{-V_D}{\frac{\mathrm{KT}}{q}}}\right).Math.\left(e^{\frac{q\left(V_G-V_{\mathrm{TH}}\right)}{\mathrm{nKT}}}\right)& \mathrm{Equation}.Math..Math.1\end{array}$

[0029] Where n is a variable which depends on the depletion capacitance of the channel C.sub.d, interface-state MOS capacitance C.sub.it and insulator capacitance C.sub.i, given by Equation 2 below.

[00002]$\begin{array}{cc}n=\left[1+\frac{C_d+C_{\mathrm{it}}}{C_i}\right]& \mathrm{Equation}.Math..Math.2\end{array}$

[0030] To simplify I.sub.D, the first term is defined as I.sub.0 as in Equation 3.

[00003]$\begin{array}{cc}{I}_0=\left(C_D+C_{\mathrm{it}}\right).Math.\frac{W}{L}.Math.{\left(\frac{\mathrm{KT}}{q}\right)}^2& \mathrm{Equation}.Math..Math.3\end{array}$

[0031] If it is assumed that

[00004]$\begin{array}{cc}{V}_D>\frac{\mathrm{KT}}{q},\mathrm{then}.Math..Math.\left(1-e^{\frac{-V_D}{\frac{\mathrm{KT}}{q}}}\right)1.& \end{array}$

By making this approximation and substituting Equation 3 into Equation 1, the drain current I.sub.D can be expressed as follows in Equation 4.

[00005]$\begin{array}{cc}{I}_D=I_0.Math.e^{\frac{q\left(V_G-V_{\mathrm{TH}}\right)}{\mathrm{nKT}}}& \mathrm{Equation}.Math..Math.4\end{array}$

[0032] Then the gate-source voltages V.sub.GS for each of the HVT and SVT transistors 4, 6 can be expressed as shown below in Equations 5 and 6 respectively.

[00006]$\begin{array}{cc}{V}_{\mathrm{GS\_HVT}}=V_{\mathrm{TH\_HVT}}+\frac{n_{\mathrm{HVT}}.Math.\mathrm{KT}}{q}.Math.\ln \left(\frac{I_{\mathrm{D\_HVT}}}{I_{0.Math.\mathrm{\_HVT}}}\right)& \mathrm{Equation}.Math..Math.5\\ V_{\mathrm{GS\_SVT}}=H_{\mathrm{TH\_SVT}}+\frac{n_{\mathrm{SVT}}.Math.\mathrm{KT}}{q}.Math.\ln \left(\frac{I_{\mathrm{D\_SVT}}}{I_{0.Math.\mathrm{\_SVT}}}\right)& \mathrm{Equation}.Math..Math.6\end{array}$

[0033] Equation 7 introduces a parameter s, where s represents the subthreshold slope and is given by.

[00007]$\begin{array}{cc}s=\ln \left(10\right).Math.\frac{\mathrm{KT}}{q}\left[\frac{1+\left(C_d+C_{\mathrm{it}}\right)}{C_i}\right]& \mathrm{Equation}.Math..Math.7\end{array}$

[0034] By substituting Equation 2 into Equation 7 and solving for n, the expression of Equation 8 is obtained.

[00008]$\begin{array}{cc}n=\frac{s.Math.\frac{q}{\mathrm{KT}}}{\ln \left(10\right)}& \mathrm{Equation}.Math..Math.8\end{array}$

[0035] By substituting Equation 8 into Equations 5 and 6, the following expressions for V.sub.GS.sub._.sub.HVT and V.sub.GS.sub._.sub.SVT as provided in Equations 9 and 10 respectively are found.

[00009]$\begin{array}{cc}{V}_{\mathrm{GS\_HVT}}=V_{\mathrm{TH\_HVT}}+\frac{s_{\mathrm{HVT}}}{\ln \left(10\right)}.Math.\ln \left(\frac{I_{\mathrm{D\_HVT}}}{I_{0.Math.\mathrm{\_HVT}}}\right)& \mathrm{Equation}.Math..Math.9\\ V_{{\mathrm{GS}}_{\mathrm{SVT}}}=V_{{\mathrm{TH}}_{\mathrm{SVT}}}+\frac{s_{\mathrm{SVT}}}{\ln \left(10\right)}.Math.\ln \left(\frac{I_{D_{\mathrm{SVT}}}}{I_{0_{\mathrm{SVT}}}}\right)& \mathrm{Equation}.Math..Math.10\end{array}$

[0036] As the operational transconductance amplifier in FIG. 1 ensures that the voltages 20 and 22 are equal, the gate-source voltage of the HVT transistor 4 must equal the sum of the gate-source voltage of the SVT transistor 6 and the voltage drop across the fixed resistor 14 (i.e. V.sub.GS.sub._.sub.HVT=V.sub.GS.sub._.sub.SVT+V.sub.R0). Thus the voltage across the resistor 14 V.sub.R0 denoted is given by Equation 11 below.

V.sub.R0=V.sub.GS.sub._.sub.HVTV.sub.GS.sub._.sub.SVT Equation 11

[0037] Assuming that the subthreshold slopes of both transistors 4, 6 are similar (i.e. s.sub.HVTs.sub.SVT), the voltage drop V.sub.R0 across the fixed resistor 14 is given by Equation 12.

[00010]$\begin{array}{cc}{V}_{R.Math..Math.0}=\left(V_{\mathrm{TH\_HVT}}-V_{\mathrm{TH\_SVT}}\right)+\frac{s}{\ln \left(10\right)}.Math.\ln \left(\frac{I_{0.Math.\mathrm{\_SVT}}}{I_{0.Math.\mathrm{\_HVT}}}\right)& \mathrm{Equation}.Math..Math.12\end{array}$

[0038] This can also be expressed in logarithmic form as below in Equation 13 using the relationship

[00011]$\log \left(x\right)=\frac{\ln \left(x\right)}{\ln \left(10\right)}.$

[00012]$\begin{array}{cc}{V}_{R.Math..Math.0}=.Math..Math.V_{{\mathrm{TH}}_{\mathrm{HVT}/\mathrm{SVT}}}+s.Math.\log \left(\frac{I_{0.Math.\mathrm{\_SVT}}}{I_{0.Math.\mathrm{\_HVT}}}\right)& \mathrm{Equation}.Math..Math.13\end{array}$

[0039] Replacing I.sub.0 with

[00013]$\left(C_D+C_{\mathrm{it}}\right).Math.\frac{W}{L}.Math.{\left(\frac{\mathrm{KT}}{q}\right)}^2$

V.sub.R0 provides Equation 14 below.

[00014]$\begin{array}{cc}{V}_{R.Math..Math.0}=.Math..Math.V_{{\mathrm{TH}}_{\mathrm{HVT}/\mathrm{SVT}}}+s.Math.\log \left(\frac{{}_{0.Math.\mathrm{\_SVT}}\left(C_{\mathrm{D\_SVT}}+C_{\mathrm{it}}\right).Math.\frac{W_{\mathrm{SVT}}}{L_{\mathrm{SVT}}}}{{}_{0.Math.\mathrm{\_HVT}}\left(C_{\mathrm{D\_HVT}}+C_{\mathrm{it}}\right).Math.\frac{W_{\mathrm{HVT}}}{L_{\mathrm{HVT}}}}\right)& \mathrm{Equation}.Math..Math.14\end{array}$

[0040] It is now assumed that the lengths of the HVT and SVT transistors 4, 6 are the same. Since the variable resistor 16 sees a scaled version of the current in the fixed transistor 14, the reference voltage output 24 denoted as V.sub.REF is expressed as Equation 15.

[00015]$\begin{array}{cc}{V}_{\mathrm{REF}}=R_1.Math.{\mathrm{BI}}_D=\frac{R_1}{R_0}.Math.B\left[.Math..Math.V_{{\mathrm{TH}}_{\mathrm{HVT}/\mathrm{SVT}}}+s.Math.\log \left(\frac{{}_{0_{\mathrm{SVT}}}\left(C_{D_{\mathrm{SVT}}}+C_{\mathrm{it}}\right).Math.W_{\mathrm{SVT}}}{{}_{0_{\mathrm{HVT}}}\left(C_{D_{\mathrm{HVT}}}+C_{\mathrm{it}}\right).Math.W_{\mathrm{HVT}}}\right)\right]& \mathrm{Equation}.Math..Math.15\end{array}$

[0041] FIG. 2 shows a simulated graph of the reference voltage 24 as a function of temperature 26 across a typical operating range. From simulation it can be observed that the difference between the threshold voltages of the HVT and SVT transistors 4, 6 (i.e. V.sub.TH.sub.HVT/SVT) will decrease with temperature, while the second term

[00016]$\left(s.Math.\log \left(\frac{{}_{0_{\mathrm{SVT}}}\left(C_{D_{\mathrm{SVT}}}+C_{\mathrm{it}}\right).Math.W_{\mathrm{SVT}}}{{}_{0_{\mathrm{HVT}}}\left(C_{D_{\mathrm{HVT}}}+C_{\mathrm{it}}\right).Math.W_{\mathrm{HVT}}}\right)\right)$

will increase with temperature if the logarithmic term is greater than one.

[0042] The trace 28 within FIG. 2 shows that each of these effects dominates at opposing extremes, increasing the reference voltage 24, as the temperature varies either side of a minimal point 30.

[0043] Thus it will be seen that voltage reference circuit has been described. Although a particular embodiment has been described in detail, many variations and modifications are possible within the scope of the invention.