STACKED SEMICONDUCTOR STRUCTURE

Abstract

A stacked semiconductor structure having a number of semiconductor diodes connected to one another in series, wherein each semiconductor diode has a p-n junction, and a tunnel diode is formed between sequential pairs of semiconductor diodes. The semiconductor diodes and the tunnel diodes jointly form a stack with a top and a bottom, and the number of semiconductor diodes is greater than or equal to two. When the stack is illuminated with light, at 300 K the stack has a source voltage of greater than 2 volts, and from the top of the stack to the bottom, a total thickness of the p and n absorption layers of a semiconductor diode increases from the topmost to the bottommost diode. The semiconductor diodes have substantially the same band gap, and the stack is formed on a substrate.

Claims

1. A stacked semiconductor structure comprising: a number of semiconductor diodes connected to one another in series, each semiconductor diode of the number of semiconductor diodes has a p-n junction, a p-doped absorption layer, and an n absorption layer, the n absorption layer being passivated by an n-doped passivation layer with a larger band gap than a band gap of the n absorption layer, and the p absorption layer of the semiconductor diode being passivated by a p-doped passivation layer with a larger band gap than a band gap of the p absorption layer; and a tunnel diode formed between sequential pairs of semiconductor diodes, the tunnel diode having multiple semiconductor layers with a higher band gap than a band gap of the p/n absorption layers, the semiconductor layers with the higher band gap are each made of a material with a modified stoichiometry and/or a different elemental composition than the p/n absorption layers of the semiconductor diode, wherein the semiconductor diode and the tunnel diodes are monolithically integrated together, and jointly form a stack with a top and a bottom, and the number of semiconductor diodes is greater than or equal to two, wherein, when the stack is illuminated with light at 300 K, the stack has a source voltage of greater than 2 volts, the light being incident on a top surface of the stack, wherein, a size of the illuminated surface on the top surface corresponds essentially to a size of an area of the stack at its top, wherein, in a direction of incident light, from the top surface towards a bottom of the stack, a total thickness of the p and n absorption layers of a semiconductor diode increases from the topmost diode towards the bottommost diode, wherein the semiconductor diodes have a same band gap or a difference of less than 0.1 eV in the band gap, wherein the stack has a total thickness of less than 20 m, and is formed on a substrate, wherein, formed in a vicinity of the bottom of the stack, is a continuous, shoulder-like primary step with a platform surface, an edge of the primary step being a minimum of 5 m and a maximum of 500 m distant from an immediately adjacent lateral face of the stack, wherein the lateral faces of the semiconductor layers that form the stack are produced via an etching process and have an average roughness value Ra between 0.002 m and 0.2 m, and wherein the stack is arranged with its bottom on a substrate, and the substrate includes a semiconductor material.

2. The stacked semiconductor structure according to claim 1, wherein an intermediate layer is arranged between the substrate and the bottom of the stack to achieve a monolithic bond between the bottom of the stack and the top of the substrate, and wherein the intermediate layer includes a nucleation layer and/or a buffer layer.

3. The stacked semiconductor structure according to claim 2, wherein the platform surface of a primary step is formed on the top of the substrate or in the substrate or on the top of the intermediate layer or in the intermediate layer.

4. The stacked semiconductor structure according to claim 1, wherein a normal of the lateral face of the stack is in an angular range between 75 and 115 or in an angular range between 95 and 105 in comparison to a normal of the platform surface.

5. The stacked semiconductor structure according to claim 1, wherein the platform surface of the primary step is flat in design or the platform surface has a difference in depth around a perimeter of less than a factor of 4, or has no difference in depth.

6. The stacked semiconductor structure according to claim 1, wherein secondary steps with a step depth of less than 5 m are formed on the lateral faces of the stack between two immediately successive semiconductor layers.

7. The stacked semiconductor structure according to claim 1, wherein the semiconductor diodes have a partial voltage, and wherein a deviation in partial voltage between the semiconductor diodes is less than 10%.

8. The stacked semiconductor structure according to claim 1, wherein the semiconductor diodes each have the same semiconductor material.

9. The stacked semiconductor structure according to claim 1, wherein the stack has a base area smaller than 4 mm.sup.2 or smaller than 2 mm.sup.2.

10. The stacked semiconductor structure according to claim 1, wherein the base area of the stack is quadrilateral or circular in design.

11. The stacked semiconductor structure according to claim 1, wherein a first terminal contact is formed on the top of the stack as a continuous, first metal contact in the vicinity of the edge or as a single contact area on the edge.

12. The stacked semiconductor structure according to claim 1, wherein a second terminal contact is formed on the bottom of the substrate.

13. The stacked semiconductor structure according to claim 1, wherein the stack includes III-V materials or is made of III-V materials.

14. The stacked semiconductor structure according to claim 1, wherein the substrate includes germanium or gallium arsenide.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

[0039] FIG. 1 is an electrotechnical equivalent circuit diagram of a stack ST1 of a semiconductor structure HL according to the invention,

[0040] FIG. 2 is a cross-sectional view of a semiconductor structure HL,

[0041] FIG. 3 is a perspective view of a semiconductor structure HL, and

[0042] FIGS. 4a-e show a detailed cross-sectional view of the etching depth for the formation of the continuous step with respect to the etching depth.

DETAILED DESCRIPTION

[0043] The illustration in FIG. 1 shows an electrotechnical equivalent circuit diagram of a stack ST1 of a semiconductor structure HL according to the invention.

[0044] The semiconductor structure HL includes a stack ST1 with a top and a bottom with a number N equal to three diodes. The stack ST1 has a series circuit formed of a first diode D1 and a first tunnel diode T1 and a second diode D2 and a second tunnel diode T2 and a third diode D3. Formed on the top of the stack ST1 is a first terminal contact K1 and on the bottom of the stack ST1 is a second terminal contact K2. The source voltage VQ of the stack ST1 in the present case is composed of the partial voltages of the individual diodes D1 to D3 combined. For this purpose, the first stack ST1 is exposed to a photon flux, which is to say the light L.

[0045] The stack ST1 of the diodes D1 to D3 and the tunnel diodes T1 and T2 is implemented as a monolithic block, preferably made of the same semiconductor material.

[0046] In the illustration in FIG. 2, a cross-sectional view of a semiconductor structure HL is shown. Only the differences from the illustration in FIG. 1 are explained below. The semiconductor structure HL includes the stack ST1 and a semiconductor substrate formed below the stack ST1.

[0047] The first stack ST1 comprises a total of five diodes D1 to D5 connected in series. The light L is incident on the surface OB of the first diode D1, which in the present case also forms the top of the stack ST1. The surface OB is completely or almost completely illuminated. One tunnel diode T1-T4 is formed in each case between the diodes D1-D5.

[0048] The thickness of the absorption region increases with increasing distance of the individual diodes D1 to D5 from the surface OB, so that the bottommost diode D5 has the thickest absorption region. Taken as a whole, the total thickness of the first stack ST1 is less than or equal to 20 m.

[0049] The substrate SUB is formed beneath the bottommost diode D5, which in the present case also forms the bottom of the stack ST1. The lateral extent of the substrate SUB is greater than the lateral extent of the stack on the bottom thereof so that a continuous primary step STU is formed.

[0050] The primary step STU is monolithically joined to the stack. In order to form the stack, an etching down to the substrate is carried out after the full-area, preferably epitaxial, production of all layers of the semiconductor structure HL.

[0051] For this purpose, a resist mask is created by means of a masking process and then wet chemical etching is performed to create the trenches. The etching stops in the substrate or on the substrate or in an intermediate layer formed between the substrate and the stack bottom.

[0052] In the illustration in FIG. 3, a perspective view of a semiconductor structure HL is shown. Only the differences from the embodiments shown in the preceding figures are explained below.

[0053] A first metal terminal contact K1 is formed on the surface of the stack ST1 at the edge R. The substrate SUB has, on the top, a platform surface AUF of the primary step STU.

[0054] The stack ST1 has a square base area with four vertical lateral faces. By the means that the individual semiconductor layers of the stack ST1 have somewhat different lateral etching rates, a plurality of secondary steps NSTU with a shallow step depth are formed along the vertical direction of the lateral faces.

[0055] The top of the substrate SUB is integrally joined to the bottommost diode, which is to say the fifth diode D5.

[0056] In an embodiment that is shown later, an intermediate layer having a thin nucleation layer and/or a buffer layer is formed on the substrate SUB, which is to say the bottom of the stack ST1 is integrally joined to the intermediate layer.

[0057] The top OS of the substrate SUB has a larger surface than the area at the bottom of the stack ST1. In this way, the continuous primary step STU is formed. The edge of the primary step STU is more than 5 m and less than 500 m distant from the immediately adjacent lateral face of the first stack ST1 of the primary step, shown as the depth of the platform surface AUF.

[0058] A second, full-area metal terminal contact K2 is formed on the bottom of the substrate SUB.

[0059] The illustrations in FIG. 4a-e show detailed cross-sectional views of various embodiments for the formation of the continuous primary step with respect to the etching depth. The lateral faces of the stack ST1 are shown only partially with regard to the height.

[0060] In the illustration in FIG. 4a, the primary step STU is formed at the boundary between the substrate SUB and the bottom of the stack ST1. No intermediate layer ZW is present between the substrate SUB and the first stack ST1, which is to say the substrate SUB is integrally joined to the bottom of the stack ST1. In other words, the etching process was very selective and anisotropic, and stopped at the material of the substrate SUB.

[0061] In the illustration in FIG. 4b, the primary step STU is formed in the substrate SUB. The etching process was not selective or was only slightly selective between the layers of the stack ST1 and the material of the substrate SUB.

[0062] In an embodiment that is not shown, the primary step STU is formed in the substrate SUB, and the substrate SUB is integrally joined to the bottom of the intermediate layer ZW, and the bottom of the stack ST1 is integrally joined to the top of the intermediate layer ZW.

[0063] In the illustration in FIG. 4c, the primary step STU is formed at the boundary between the intermediate layer ZW and the bottom of the stack ST1. The intermediate layer ZW is formed between the substrate SUB and the stack ST1, which is to say the substrate SUB is integrally joined to the bottom of the intermediate layer ZW, and the bottom of the stack ST1 is integrally joined to the top of the intermediate layer ZW. In other words, the etching process was very selective and anisotropic, and stopped at the material of the intermediate layer ZW.

[0064] In the illustration in FIG. 4d, the primary step STU is formed at the boundary between the substrate SUB and the bottom of the intermediate layer ZW. The lateral faces of the stack are inclined towards one another, and form an angle greater than 90 with the surface of the substrate.

[0065] The intermediate layer ZW is formed between the substrate SUB and the stack ST1, which is to say the substrate SUB is integrally joined to the bottom of the intermediate layer ZW, and the bottom of the stack ST1 is integrally joined to the top of the intermediate layer ZW. The intermediate layer is completely removed or nearly completely removed above the platform surface AUF of the primary step. In other words, the etching process was very selective and anisotropic, and stopped at the substrate SUB.

[0066] In the illustration in FIG. 4e, the primary step STU is formed at the boundary between the substrate SUB and the bottom of the intermediate layer ZW. The lateral faces of the stack are inclined away from one another, and form an angle less than 90 with the surface of the substrate.

[0067] The intermediate layer ZW is formed between the substrate SUB and the stack ST1, which is to say the substrate SUB is integrally joined to the bottom of the intermediate layer ZW, and the bottom of the stack ST1 is integrally joined to the top of the intermediate layer ZW. The intermediate layer is completely removed or nearly completely removed above the platform surface AUF of the primary step. In other words, the etching process was very selective and anisotropic, and stopped at the substrate SUB.

[0068] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.