CONTROL METHOD, CONTROLLER, AND CONTROL SYSTEM

Abstract

A control method, a controller, and a control system including a converter and the controller are provided to improve load responsiveness of control by the converter. The converter has a primary circuit that includes a voltage generation circuit for generating a square wave and a resonant circuit for converting a waveform of the generated square wave, and a secondary circuit that is electromagnetically coupled to the primary circuit and that generates an induced electromotive force. The controller controls the voltage generation circuit by a control target power factor. To implement power factor-based control, the controller controls the voltage generation circuit, based on a derived power factor derived from an active power and an apparent power relevant to the resonant circuit in the primary circuit or a derived power factor derived from a phase of the primary circuit.

Claims

1. A control method for controlling a power converter that includes a voltage generation circuit for generating a voltage waveform containing an alternating current and a resonant circuit for converting the generated voltage waveform, the method comprising: controlling the voltage generation circuit by a control target power factor that is a desired value for control.

2. A controller for controlling a power converter that includes a voltage generation circuit for generating a voltage waveform containing an alternating current and a resonant circuit for converting the generated voltage waveform, the controller comprising: a voltage generation circuit control unit that controls the voltage generation circuit by a control target voltage corresponding to a control target power factor that is a desired value for control.

3. A controller for controlling a power converter that includes a voltage generation circuit for generating a voltage waveform containing an alternating current and a resonant circuit for converting the generated voltage waveform, the controller comprising: a comparator unit that compares a value relating to an output from the power converter, with a target value thereof; a target control unit that derives a control target voltage that is a desired value for control, based on a result of a comparison by the comparator unit; and a voltage generation circuit control unit that controls the voltage generation circuit by a control target power factor corresponding to the control target voltage derived by the target control unit.

4. The controller according to claim 2, wherein the voltage generation circuit control unit controls the voltage generation circuit such that a derived power factor achieves the control target power factor, and the derived power factor is derived in the resonant circuit, from an active power and an apparent power relevant to an alternating current wave supplied from the voltage waveform generated by the voltage generation circuit.

5. The controller according to claim 2, wherein the voltage generation circuit control unit controls the voltage generation circuit, based on a derived power factor, and the derived power factor is derived as a ratio of an active power to an apparent power, the active power being derived from a voltage across a resonant capacitor provided in the resonant circuit or a current through the resonant circuit and from a voltage waveform that is generated in the voltage generation circuit and that changes over time, the apparent power being derived from the resonant capacitor voltage and an amplitude of the resonant capacitor.

6. The controller according to claim 2, wherein the voltage generation circuit control unit comprises: an amplitude acquisition circuit that acquires a voltage across a resonant capacitor provided in the resonator circuit and then acquires, from the resonant capacitor voltage, an amplitude of the resonant capacitor voltage; a control target derivation circuit that derives, from the amplitude of the resonant capacitor voltage, a control target resonant capacitor voltage that is a desired value for control; and a control signal output circuit for controlling the voltage generation circuit, the control signal output circuit outputting at least one voltage generation circuit control signal for controlling the voltage generation circuit, based on a result of a comparison in which an absolute value of the resonant capacitor voltage is compared with the control target resonant capacitor voltage derived by the control target derivation circuit.

7. The controller according to claim 2, wherein the voltage generation circuit control unit controls the voltage generation circuit such that a derived power factor achieves the control target power factor, and the derived power factor is derived from a current through the resonant circuit.

8. The controller according to claim 2, wherein the voltage generation circuit control unit comprises: a reference phase acquisition circuit that acquires a voltage across a resonant capacitor provided in the resonant circuit and then acquires a reference phase based on the resonant capacitor voltage, the reference phase serving as a reference for a phase of a current through the resonant circuit; a waveform generation circuit that generates, from the reference phase acquired by the reference phase acquisition circuit, a time-varying waveform that changes over time; a phase difference calculation circuit that calculates, based on a target phase difference that is a desired phase difference and also based on the time-varying waveform generated by the waveform generation circuit, a target value in the time-varying waveform as a value corresponding to the target phase difference; and a control signal output circuit for controlling the voltage generation circuit, the control signal output circuit outputting at least one voltage generation circuit control signal for controlling the voltage generation circuit, based on the time-varying waveform generated by the waveform generation circuit and the target value calculated by the phase difference calculation circuit.

9. The controller according to claim 8, wherein the waveform generation circuit generates a sawtooth wave as the time-varying waveform, a voltage of the sawtooth wave changing over time along a substantially uniform slope in a time period from the reference phase acquired by the reference phase acquisition circuit until a next reference phase, the phase difference calculation circuit calculates a value of a voltage corresponding to the target phase difference as a target phase difference voltage, in the voltage of the sawtooth wave that changes over time along the substantially uniform slope, and the control signal output circuit for controlling the voltage generation circuit outputs the voltage generation circuit control signal, based on a result of a comparison in which the voltage of the sawtooth wave generated by the waveform generation circuit is compared with the target phase difference voltage calculated by the phase difference calculation circuit.

10. A control system comprising: a power converter that includes a voltage generation circuit for generating a voltage waveform containing an alternating current and a resonant circuit for converting the generated voltage waveform; and the controller according to claim 2 for controlling the voltage generation circuit.

11. The controller according to claim 3, wherein the voltage generation circuit control unit controls the voltage generation circuit such that a derived power factor achieves the control target power factor, and the derived power factor is derived in the resonant circuit, from an active power and an apparent power relevant to an alternating current wave supplied from the voltage waveform generated by the voltage generation circuit.

12. The controller according to claim 3, wherein the voltage generation circuit control unit controls the voltage generation circuit, based on a derived power factor, and the derived power factor is derived as a ratio of an active power to an apparent power, the active power being derived from a voltage across a resonant capacitor provided in the resonant circuit or a current through the resonant circuit and from a voltage waveform that is generated in the voltage generation circuit and that changes over time, the apparent power being derived from the resonant capacitor voltage and an amplitude of the resonant capacitor.

13. The controller according to claim 3, wherein the voltage generation circuit control unit comprises: an amplitude acquisition circuit that acquires a voltage across a resonant capacitor provided in the resonator circuit and then acquires, from the resonant capacitor voltage, an amplitude of the resonant capacitor voltage; a control target derivation circuit that derives, from the amplitude of the resonant capacitor voltage, a control target resonant capacitor voltage that is a desired value for control; and a control signal output circuit for controlling the voltage generation circuit, the control signal output circuit outputting at least one voltage generation circuit control signal for controlling the voltage generation circuit, based on a result of a comparison in which an absolute value of the resonant capacitor voltage is compared with the control target resonant capacitor voltage derived by the control target derivation circuit.

14. The controller according to claim 3, wherein the voltage generation circuit control unit controls the voltage generation circuit such that a derived power factor achieves the control target power factor, and the derived power factor is derived from a current through the resonant circuit.

15. The controller according to claim 3, wherein the voltage generation circuit control unit comprises: a reference phase acquisition circuit that acquires a voltage across a resonant capacitor provided in the resonant circuit and then acquires a reference phase based on the resonant capacitor voltage, the reference phase serving as a reference for a phase of a current through the resonant circuit; a waveform generation circuit that generates, from the reference phase acquired by the reference phase acquisition circuit, a time-varying waveform that changes over time; a phase difference calculation circuit that calculates, based on a target phase difference that is a desired phase difference and also based on the time-varying waveform generated by the waveform generation circuit, a target value in the time-varying waveform as a value corresponding to the target phase difference; and a control signal output circuit for controlling the voltage generation circuit, the control signal output circuit outputting at least one voltage generation circuit control signal for controlling the voltage generation circuit, based on the time-varying waveform generated by the waveform generation circuit and the target value calculated by the phase difference calculation circuit.

16. The controller according to claim 15, wherein the waveform generation circuit generates a sawtooth wave as the time-varying waveform, a voltage of the sawtooth wave changing over time along a substantially uniform slope in a time period from the reference phase acquired by the reference phase acquisition circuit until a next reference phase, the phase difference calculation circuit calculates a value of a voltage corresponding to the target phase difference as a target phase difference voltage, in the voltage of the sawtooth wave that changes over time along the substantially uniform slope, and the control signal output circuit for controlling the voltage generation circuit outputs the voltage generation circuit control signal, based on a result of a comparison in which the voltage of the sawtooth wave generated by the waveform generation circuit is compared with the target phase difference voltage calculated by the phase difference calculation circuit.

17. A control system comprising: a power converter that includes a voltage generation circuit for generating a voltage waveform containing an alternating current and a resonant circuit for converting the generated voltage waveform; and the controller according to claim 3 for controlling the voltage generation circuit.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0033] FIG. 1 is a block diagram showing a configuration example of a control system according to the present disclosure.

[0034] FIG. 2 is a circuit diagram showing an example of an equivalent circuit of a converter provided in the control system according to the present disclosure.

[0035] FIG. 3 is a circuit diagram showing an example of an equivalent circuit of the converter provided in the control system according to the present disclosure.

[0036] FIG. 4 is a graph showing an example of a waveform relating to the converter provided in the control system according to the present disclosure.

[0037] FIG. 5 is a graph showing an example of waveforms relating to the converter provided in the control system according to the present disclosure.

[0038] FIG. 6 is a circuit diagram showing a circuit example implementable in a controller provided in the control system according to the present disclosure.

[0039] FIG. 7 is a graph showing an example of a waveform relating to the controller provided in the control system according to the present disclosure.

[0040] FIG. 8 is a graph showing an example of a waveform relating to the controller provided in the control system according to the present disclosure.

[0041] FIG. 9 is a block diagram showing a circuit example implementable in the controller provided in the control system according to the present disclosure.

[0042] FIG. 10 is a circuit diagram showing a circuit example implementable in the controller provided in the control system according to the present disclosure.

[0043] FIG. 11 is a graph showing an example of waveforms relating to the controller provided in the control system according to the present disclosure.

[0044] FIG. 12 is a circuit diagram showing a circuit example implementable in the controller provided in the control system according to the present disclosure.

[0045] FIG. 13 is a graph showing an example of simulation conditions for the control system according to the present disclosure.

[0046] FIG. 14 is a graph showing an example of simulation results in the control system according to the present disclosure.

[0047] FIG. 15 is a graph showing an example of simulation results in the control system according to the present disclosure.

[0048] FIG. 16 is a graph showing an example of simulation results in the control system according to the present disclosure.

[0049] FIG. 17 is a graph showing an example of simulation results in the control system according to the present disclosure.

[0050] FIG. 18 is a graph showing an example of simulation results in the control system according to the present disclosure.

[0051] FIG. 19 is a circuit diagram showing a circuit example implementable in the controller provided in the control system according to the present disclosure.

[0052] FIG. 20 is a graph showing an example of waveforms relating to the controller provided in the control system according to the present disclosure.

[0053] FIG. 21 is a circuit diagram showing a circuit example implementable in the controller provided in the control system according to the present disclosure.

[0054] FIG. 22 is a graph showing an example of waveforms relating to the controller provided in the control system according to the present disclosure.

[0055] FIG. 23 is a block diagram showing a circuit example implementable in the controller provided in the control system according to the present disclosure.

[0056] FIG. 24 is a circuit diagram showing a circuit example implementable in the controller provided in the control system according to the present disclosure.

[0057] FIG. 25 is a graph showing an example of waveforms relating to the controller provided in the control system according to the present disclosure.

[0058] FIG. 26 is a circuit diagram showing a circuit example implementable in the controller provided in the control system according to the present disclosure.

[0059] FIG. 27 is a graph showing an example of simulation conditions for the control system according to the present disclosure.

[0060] FIG. 28 is a graph showing an example of simulation results in the control system according to the present disclosure.

[0061] FIG. 29 is a graph showing an example of simulation results in the control system according to the present disclosure.

[0062] FIG. 30 is a graph showing an example of simulation results in the control system according to the present disclosure.

[0063] FIG. 31 is a graph showing an example of simulation results in the control system according to the present disclosure.

[0064] FIG. 32 is a graph showing an example of simulation results in the control system according to the present disclosure.

DESCRIPTION OF EMBODIMENTS

[0065] Embodiments of the present invention are hereinafter described with reference to the drawings.

APPLICATION EXAMPLE

[0066] A control method according to the present disclosure is applied to control, for example, a resonant converter. The resonant converter has a primary circuit using an LC resonant circuit such as an LLC converter and a secondary circuit electromagnetically coupled to the primary circuit, and converts power by rectifying an output from the secondary circuit. Such a resonant converter is applied to a DC/DC converter, a Point-of-Load power supply, and other like uses. In the following description of the control method according to the present disclosure, a control system CS that includes a converter 1 and a controller 2 for controlling the converter 1 is taken as an example and described with reference to the drawings.

<Control System>

[0067] FIG. 1 is a block diagram showing a configuration example of the control system CS according to the present disclosure. The control system CS in the present disclosure includes, for example, a converter 1 serving as a DC/DC converter and a controller 2 for controlling the converter 1. The converter 1 includes various components such as an input power source 10, a primary circuit 11, a coupling circuit 12, and a secondary circuit 13. The controller 2 includes various components such as a comparator unit 20, a target control unit 21, and a control signal output circuit 22 for controlling a voltage generation circuit.

<Converter>

[0068] In the converter 1, the input power source 10 is a DC power source and supplies DC power to the converter 1. The input power source 10 is, for example, a DC power source of about 140V obtained by rectification of a commercial AC power source of 100V. In this case, the voltage needs to be stepped down.

[0069] The coupling circuit 12 insulates an input and an output of the converter 1 from each other. The input-side primary circuit 11 includes a voltage generation circuit 110 connected to the input power source 10 and serving as a switching circuit, a resonant circuit 111 connected to the voltage generation circuit 110, and other like components.

[0070] The voltage generation circuit 110 is configured as a half-bridge circuit in which a first switching element Q1 and a second switching element Q2 are connected in series with the input power source 10. The switching elements Q1, Q2 are semiconductor switches such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), or other like devices. In the embodiments described herein, the switching elements Q1, Q2 are n-channel MOSFETs. Gate terminals of the switching elements Q1, Q2 are connected to the controller 2, specifically to the control signal output circuit 22 for controlling the voltage generation circuit.

[0071] The resonant circuit 111 is an LLC resonant converter in which a resonant capacitor C.sub.r, a leakage inductance L.sub.r, and a magnetizing inductance L.sub.m are connected in series.

[0072] The coupling circuit 12 is a transformer that includes a primary winding L.sub.p and two series-connected secondary windings L.sub.s1, L.sub.s2. The coupling circuit 12 electromagnetically couples the primary circuit 11 and the secondary circuit 13. The primary winding L.sub.p is connected in parallel with the magnetizing inductance L.sub.m of the resonant circuit 111. The secondary windings L.sub.s1, L.sub.s2 are connected to the secondary circuit 13. The turns ratio of the primary winding L.sub.p to the secondary windings L.sub.s1, L.sub.s2 is N:1.

[0073] The secondary circuit 13 includes output diodes D1, D2, an output capacitor C.sub.o, and other like components. The secondary circuit 13 is connected to a load R.sub.L to which the power is output. The output diodes D1, D2 are a pair of rectifier elements connected to opposite ends of the secondary windings L.sub.s1, L.sub.s2. In the secondary circuit 13, the alternating current generated in the coupling circuit 12 is rectified by the output diodes D1, D2 and smoothed by the output capacitor C.sub.o to produce a DC output voltage V.sub.o. The DC output voltage V.sub.o is output to the load R.sub.L.

<Controller>

[0074] The controller 2, to be described below, includes the comparator unit 20, the target control unit 21, the control signal output circuit 22 for controlling the voltage generation circuit, and other components.

[0075] The comparator unit 20 is an error comparator circuit that compares the output voltage V.sub.o received from the secondary circuit 13 with a target voltage V.sub.o* representing a desired output, from the converter 1. The target voltage V.sub.o* may be set in advance or may be input externally. The comparator unit 20 compares the output voltage V.sub.o with the target voltage V.sub.o*, derives a result of the comparison (for example, a difference between the output voltage V.sub.o and the target voltage V.sub.o*), and outputs the derived comparison result to the target control unit 21.

[0076] The target control unit 21 is configured, for example, using an PI controller. By PI control based on the comparison result supplied from the comparator unit 20 and an integral thereof, the target control unit 21 derives a control target voltage that is a desired value for control. The derived control target voltage is output to the control signal output circuit 22 for controlling the voltage generation circuit.

[0077] The control signal output circuit 22 for controlling the voltage generation circuit is a circuit for controlling the converter 1 by a control target power factor that corresponds to the control target voltage. The control target power factor is a power factor that is a desired value for control. The controller 2 controls the converter 1 by power factor-based control. The control signal output circuit 22 for controlling the voltage generation circuit is connected to the voltage generation circuit 110 provided in the primary circuit 11 of the converter 1. The control signal output circuit 22 for controlling the voltage generation circuit outputs control signals for controlling the voltage generation circuit (hereinafter referred to as “voltage generation circuit control signal(s)”) to the gate terminals of the switching elements Q1, Q2 that constitute the voltage generation circuit 110, and thereby controls the switching elements Q1, Q2. The voltage generation circuit control signals, which are output from the control signal output circuit 22 for controlling the voltage generation circuit, are intended to control the voltage generation circuit 110 provided in the converter 1. Note that the voltage generation circuit control signals, which are output from the control signal output circuit 22 for controlling the voltage generation circuit, include signals for causing the voltage generation circuit 110 to function as a switching power supply. This type of signal is called “switching signal” in the following description.

<Principle of Power Factor Control>

[0078] The next description relates to the principle of power factor control in the control system CS according to the present disclosure. FIG. 2 is a circuit diagram showing an example of an equivalent circuit of the converter 1 provided in the control system CS according to the present disclosure. In the equivalent circuit of the converter 1 shown in FIG. 2, a square wave source 112 represents the DC input power source 10 and the voltage generation circuit 110. For simplicity, the following description refers to the equivalent circuit in FIG. 2, on the assumption that the magnetizing inductance L.sub.m is large enough and an input voltage V.sub.inv transmitted from the square wave source 112 contains only the fundamental component.

[0079] In the equivalent circuit illustrated in FIG. 2, an active power in the steady state is equal to an output power consumed by the load R.sub.L. In this case, the output voltage V.sub.o can be represented by Formula 1 below using a power factor. It is obvious that the power factor control according to Formula 1, which does not involve a resistance of the load R.sub.L, can control the output power irrespective of the load R.sub.L.

V.sub.o=(V.sub.inv/N)cos θ  Formula 1

where

[0080] V.sub.o: output voltage

[0081] V.sub.inv: input voltage

[0082] N: turns ratio

[0083] θ: phase difference between an amplitude of the input voltage and an amplitude of a primary current

[0084] cos θ: power factor

[0085] In the equivalent circuit illustrated in FIG. 2, the input power can be represented by Formula 2 below using the input voltage V.sub.inv, the amplitude of the primary current I.sub.r, and the power factor cos θ. The secondary transmitted power P.sub.se transmitted to the secondary circuit 13 can be represented by Formula 3 below using the output voltage V.sub.o.

P.sub.in=(2/π)V.sub.invI.sub.r cos θ  Formula 2

where

[0086] P.sub.in: input power

[0087] V.sub.inv: input voltage

[0088] I.sub.r: amplitude of the primary current

P.sub.se=(2/π)NI.sub.rV.sub.o  Formula 3

[0089] where

[0090] P.sub.se: secondary transmitted power

[0091] N: turns ratio

[0092] I.sub.r: amplitude of the primary current

[0093] V.sub.o: output voltage

[0094] The difference between the input power P.sub.in and the secondary transmitted power P.sub.se represents power stored in the primary circuit 11. The power stored in the primary circuit 11 is equal to power stored in the resonant circuit 111. These relationships can be represented by Formula 4 below.

[00001]$\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{Formula}1\right]& \\ P_{\mathrm{in}}-P_{\mathrm{se}}=P_r=\frac{d}{\mathrm{dt}}\left(\frac{1}{2}{L}_r{I}_r^2\right)& \mathrm{Formula}4\end{array}$

where

[0095] P.sub.in: input power

[0096] P.sub.se: induced electromotive force

[0097] P.sub.r: power consumed in the primary circuit

[0098] L.sub.r: leakage inductance

[0099] I.sub.r: amplitude of the primary current

[0100] The relationships of Formulas 2 to 4 give Formula 5 below.

[00002]$\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{Formula}2\right]& \\ P_{\mathrm{in}}-P_{\mathrm{se}}=\frac{2}{\pi }{V}_{\mathrm{inv}}{I}_r\cos \theta -\frac{2}{\pi }{\mathrm{NI}}_r{V}_o=\frac{d}{\mathrm{dt}}\left(\frac{1}{2}{L}_r{I}_r^2\right)& \mathrm{Formula}5\end{array}$

where

[0101] P.sub.in: input power

[0102] P.sub.se: induced electromotive force

[0103] V.sub.inv: input voltage

[0104] I.sub.r: amplitude of the primary current

[0105] cosθ: power factor

[0106] N: turns ratio

[0107] V.sub.o: output voltage

[0108] L.sub.r: leakage inductance

[0109] In the secondary circuit 13, power consumed by the load R.sub.L can be represented by Formula 6 below, and power stored in the output capacitor C.sub.o can be represented by Formula 7 below.

P.sub.out=V.sub.oI.sub.o  Formula 6

where

[0110] P.sub.out: power consumed by the load

[0111] V.sub.o: output voltage

[0112] I.sub.o: DC component of the output current

[00003]$\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{Formula}3\right]& \\ P_{\mathrm{cap}}=\frac{d}{\mathrm{dt}}\left(\frac{1}{2}{C}_o{V}_o^2\right)& \mathrm{Formula}7\end{array}$

where

[0113] P.sub.cap: power consumed by the output capacitor

[0114] C.sub.o: capacitance of the output capacitor

[0115] V.sub.o: output voltage

[0116] Power stored in the secondary circuit 13 is equal to the sum of the power consumed by the load R.sub.L and the power stored in the output capacitor C.sub.o. Accordingly, the power stored in the output capacitor C.sub.o is calculated by a subtraction of the power P.sub.out consumed by the load R.sub.L from the secondary transmitted power P.sub.se. These relationships give Formula 8 below.

[00004]$\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{Formula}4\right]& \\ P_{\mathrm{se}}-P_{\mathrm{out}}=\frac{2}{\pi }{\mathrm{NI}}_r{V}_o-V_o{I}_o=\frac{d}{\mathrm{dt}}\left(\frac{1}{2}{C}_o{V}_o^2\right)& \mathrm{Formula}8\end{array}$

where

[0117] P.sub.se: induced electromotive force

[0118] P.sub.out: power consumed by the load

[0119] N: turns ratio

[0120] L: amplitude of the primary current

[0121] V.sub.o: output voltage

[0122] I.sub.o: DC component of the output current

[0123] C.sub.o: capacitance of the output capacitor

[0124] Formulas 5 and 8 are rearranged using the DC component of the current flowing from the rectifier circuit to the output capacitor C.sub.o in the secondary circuit 13. Thus obtained Formulas 9 and 10 provide circuit characteristics of the resonant circuit 111 implemented as the LLC resonant converter.

[00005]$\begin{array}{cc}\left[\mathrm{Mathematical}\mathrm{Formula}5\right]& \\ \frac{{\pi }^2}{4N}{L}_r\frac{{\mathrm{dI}}_s}{\mathrm{dt}}=V_{\mathrm{inV}}\cos \theta -{\mathrm{NV}}_o& \mathrm{Formula}9\end{array}$$\begin{array}{cc}{C}_o\frac{{\mathrm{dV}}_o}{\mathrm{dt}}=I_s-I_o& \mathrm{Formula}10\end{array}$

where

[0125] N: turns ratio

[0126] L.sub.r: leakage inductance

[0127] I.sub.s: DC component of the secondary current flowing from the rectifier circuit to the output capacitor

[0128] V.sub.inv: input voltage

[0129] cos θ: power factor

[0130] V.sub.o: output voltage

[0131] C.sub.o: capacitance of the output capacitor

[0132] I.sub.o: DC component of the output current

[0133] As described above, the control system CS according to the present disclosure includes the converter 1 such as a DC/DC converter and the controller 2 for controlling the converter 1. The controller 2 controls the converter 1 by the power factor-based control.

Embodiments

[0134] The following description is directed to examples of specific embodiments for conducting the power factor control.

First Embodiment

[0135] The power factor can be represented as a ratio of the active power to the apparent power, by Formula 11 below. The first embodiment controls the power factor by controlling the active power, based on the ratio of the active power to the apparent power.

power factor=cos θ=active power/apparent power  Formula 11

[0136] FIG. 3 is a circuit diagram showing an example of an equivalent circuit of the converter 1 provided in the control system CS according to the present disclosure. FIG. 4 is a graph showing an example of a waveform relating to the converter 1 provided in the control system CS according to the present disclosure. In the equivalent circuit of the converter 1 shown in FIG. 3, the square wave source 112 represents the input power source 10 and the voltage generation circuit 110. FIG. 4 shows the input voltage V.sub.inv(t) with its changes over time, where the horizontal axis indicates the time t and the vertical axis indicates the input voltage V.sub.inv(t) across the square wave source 112. The converter 1 illustrated in FIG. 3 operates in response to an input of the square wave illustrated in FIG. 4. By measuring the active power and the apparent power and implementing feedback control according to Formula 11, the converter 1 can achieve the power factor control based on power control. To simplify this power factor control, the first embodiment is configured to control the power factor by indirectly controlling the power in accordance with the voltage across the resonant capacitor C.sub.r.

[0137] FIG. 5 is a graph showing an example of waveforms relating to the converter 1 provided in the control system CS according to the present disclosure. FIG. 5 shows the input voltage V.sub.inv(t) and the resonant capacitor voltage V.sub.cr(t) with their changes over time, where the horizontal axis indicates the time t and the vertical axis indicates the voltage, and where the input voltage V.sub.inv(t) and the resonant capacitor voltage V.sub.cr(t) are aligned for comparison. The resonant capacitor voltage V.sub.cr(t) shown in FIG. 5 represents a potential difference between electrodes of the resonant capacitor C.sub.r provided in the resonant circuit 111. The active power in the primary circuit 11 can be represented by Formula 12 below using a cycle T in the square wave source 112, the resonant capacitor voltage Vcr(t), the moment t, when the input voltage V.sub.inv starts rising (hereinafter, the start of rising may be referred to as “rise(s)” or “rising”), and the moment td when the input voltage V.sub.inv starts dropping (hereinafter, the start of dropping may be referred to as “drop(s)” or “dropping”).

P.sub.u=(V.sub.inv/T).Math.[V.sub.cr(t.sub.d)−V.sub.cr(t.sub.d)]  Formula 12

where

[0138] P.sub.u: active power

[0139] V.sub.inv: input voltage

[0140] T: cycle of the square wave

[0141] V.sub.cr(t): resonant capacitor voltage at the moment t

[0142] t.sub.r: moment of rising

[0143] t.sub.d: moment of dropping

[0144] The apparent power is equal to the active power at the power factor of 1. When the power factor is 1, the input voltage V.sub.inv rises at local minima of the resonant capacitor voltage and drops at local maxima thereof, as illustrated in FIG. 5. Accordingly, the apparent power can be represented by Formula 13 below using an amplitude V.sub.cr of the resonant capacitor voltage.

P.sub.h=(V.sub.inv/T).Math.2V.sub.cr  Formula 13

where

[0145] P.sub.h: apparent power

[0146] V.sub.inv: input voltage

[0147] T: cycle of the square wave

[0148] V.sub.cr: amplitude of the resonant capacitor voltage

[0149] As indicated by Formulas 12 and 13, the active power and the apparent power can be derived from the amplitude V.sub.cr of the resonant capacitor voltage, the moment of rising t.sub.r, and the moment of dropping t.sub.d. In this case, the active power and the apparent power do not have to be detected directly, and can be detected indirectly by detection of the resonant capacitor voltage V.sub.cr. The detected active power and apparent power are used to conduct the power factor control.

[0150] A specific example of the circuit configuration is given below. The power factor derived as the ratio of the active power to the apparent power (derived power factor) can be represented by Formula 14 below using the moment of rising t.sub.r and the moment of dropping t.sub.d of the square wave, the resonant capacitor voltage V.sub.cr(t), and the amplitude V.sub.cr of the resonant capacitor voltage.

power factor=P.sub.u/P.sub.h=[V.sub.cr(t.sub.d)−V.sub.cr(t.sub.r)]/2V.sub.cr  Formula 14

where

[0151] P.sub.u: active power

[0152] P.sub.h: apparent power

[0153] V.sub.cr(t): resonant capacitor voltage at the moment t

[0154] t.sub.r: moment of rising

[0155] t.sub.d: moment of dropping

[0156] V.sub.cr: amplitude of the resonant capacitor voltage

[0157] In Formula 14, suppose that the magnitude of the resonant capacitor voltage is approximated to be equal at the moment of rising t.sub.r and at the moment of dropping t.sub.d. Then, the power factor (derived power factor) can be represented by Formula 15 below.

power factor=P.sub.u/P.sub.h=[2|V.sub.cr(t.sub.r)|]/2V.sub.cr=|V.sub.cr(t.sub.r)|/V.sub.cr  Formula 15

where

[0158] P.sub.u: active power

[0159] P.sub.h: apparent power

[0160] V.sub.cr(t): resonant capacitor voltage at the moment t

[0161] t.sub.r: moment of rising

[0162] V.sub.cr: amplitude of the resonant capacitor voltage

[0163] The power factor obtained according to Formula 15 is the ratio of the resonant capacitor voltage V.sub.cr(t) at the moment t to the amplitude V.sub.cr of the resonant capacitor voltage. As a result, the controller 2 implements the voltage generation circuit 110 that sets the capacitor voltage at the moment of rising t.sub.r, based on the amplitude V.sub.cr of the resonant capacitor voltage, and that outputs switching signals to the gate terminals of the switching elements Q1, Q2 when the capacitor voltage reaches the set capacitor voltage. This configuration enables the controller 2 to control the power factor by the power control. The voltage generation circuit 110 implemented in the controller 2 needs a function of acquiring the amplitude V.sub.cr of the resonant capacitor voltage. By acquiring the amplitude V.sub.cr of the resonant capacitor voltage, the controller 2 can derive a control target resonant capacitor voltage that is necessary to achieve the control target power factor that is a desired value for control. The controller 2 further needs a function of outputting the switching signals when the capacitor voltage reaches the control target resonant capacitor voltage.

[0164] FIG. 6 is a circuit diagram showing a circuit example implementable in the controller 2 provided in the control system CS according to the present disclosure. FIG. 6 illustrates an example of an amplitude acquisition circuit EC1 that acquires the amplitude of the resonant capacitor voltage. The amplitude acquisition circuit EC1 acquires the resonant capacitor voltage V.sub.cr(t) from the resonant capacitor C.sub.r provided in the converter 1, and detects a maximum value (local maximum) V.sub.crpeak of the resonant capacitor voltage with the DC component removed. The amplitude acquisition circuit EC1 is composed of various circuits and components including a rectifier circuit for performing full-wave rectification of the acquired resonant capacitor voltage V.sub.cr(t), a voltage sensor for detecting a full-wave rectified resonant capacitor voltage V.sub.all(t), and a detector circuit and a limiter circuit for detecting a maximum value V.sub.crpeak of the detected full-wave rectified resonant capacitor voltage V.sub.all(t) and outputting the maximum value V.sub.crpeak. The thus configured amplitude acquisition circuit EC1 can acquire the amplitude of the resonant capacitor voltage by obtaining the absolute value of the maximum resonant capacitor voltage V.sub.crpeak that is output from the detector circuit. The example illustrated in FIG. 6 uses a diode detector circuit including a diode, a capacitor, and a resistance. Owing to the full-wave rectification in the rectifier circuit, the amplitude acquisition circuit EC1 can acquire the amplitude of the resonant capacitor voltage from both the positive resonant capacitor voltage and the negative resonant capacitor voltage, and is hence expected to improve immediate responsiveness.

[0165] FIGS. 7 and 8 are graphs showing waveform examples relating to the controller 2 provided in the control system CS according to the present disclosure. FIG. 7 shows the resonant capacitor voltage with its changes over time, where the horizontal axis indicates the time t and the vertical axis indicates the resonant capacitor voltage V.sub.cr(t). FIG. 8 shows the resonant capacitor voltage and its maximum value with their changes over time, where the horizontal axis indicates the time t and the vertical axis indicates the full-wave rectified resonant capacitor voltage V.sub.all(t) that changes over time and the absolute value of the maximum resonant capacitor voltage V.sub.crpeak that is output from the detector circuit. As illustrated in FIG. 7, the amplitude acquisition circuit EC1 acquires the resonant capacitor voltage from the converter 1 as a sinusoidal wave. Then, the amplitude acquisition circuit EC1 subjects the sinusoidal resonant capacitor voltage to full-wave rectification, and outputs a maximum value (local maximum) of the full-wave rectified resonant capacitor voltage as the amplitude, as illustrated in FIG. 8. In the manner described above, the amplitude acquisition circuit EC1 outputs the amplitude V.sub.cr of the resonant capacitor voltage, based on the resonant capacitor voltage.

[0166] FIG. 9 is a block diagram showing a circuit example implementable in the controller 2 provided in the control system CS according to the present disclosure. The block diagram of FIG. 9 conceptually illustrates a control target derivation circuit EC2 that derives and outputs the control target resonant capacitor voltage. The control target derivation circuit EC2 compares the maximum resonant capacitor voltage V.sub.crpeak with the control target resonant capacitor voltage and, from a result of the comparison, derives the control target resonant capacitor voltage V.sub.crref that is a desired value for control. As descried above, the absolute value of the maximum resonant capacitor voltage V.sub.crpeak is obtained in the amplitude acquisition circuit EC1. The control target resonant capacitor voltage V.sub.crref may be set in advance or may be derived from the control target voltage that is based on the output voltage V.sub.o from the secondary circuit 13. For example, the control target resonant capacitor voltage V.sub.crref is derived from the amplitude of the resonant capacitor voltage and from the control target voltage derived as a voltage corresponding to the control target power factor.

[0167] FIG. 10 is a circuit diagram showing a circuit example implementable in the controller 2 provided in the control system CS according to the present disclosure. FIG. 10 illustrates an example of a switching signal output circuit EC3 that outputs switching signals V.sub.gs-High, V.sub.gs-Low, based on the resonant capacitor voltage V.sub.cr(t) and the control target resonant capacitor voltage V.sub.crref. The switching signal output circuit EC3 is composed of various circuits and components including a rectifier circuit, a voltage sensor, a comparator, a pulse generator, and a D flip-flop. The rectifier circuit and the voltage sensor are shared with the amplitude acquisition circuit EC1. The comparator compares the absolute value of the resonant capacitor voltage V.sub.cr(t) that is output from the voltage sensor, with the control target resonant capacitor voltage V.sub.crref. The comparator then outputs a high-level signal or a low-level signal to the pulse generator. Specifically, when the absolute value of the resonant capacitor voltage V.sub.cr(t) exceeds the control target resonant capacitor voltage V.sub.crref, the comparator changes the level of the output signal to the pulse generator from low to high. At the moment when the level of the signal from the comparator changes from low to high, the pulse generator outputs a pulse, as a rising signal, to the D flip-flop. Every time the resonant capacitor voltage V.sub.cr reaches the control target, the thus configured switching signal output circuit EC3 outputs the switching signals V.sub.gs-High, V.sub.gs-Low to invert the voltage generation circuit 110.

[0168] FIG. 11 is a graph showing an example of waveforms relating to the controller 2 provided in the control system CS according to the present disclosure. FIG. 11 shows the resonant capacitor voltage V.sub.cr(t), the absolute value of the full-wave rectified resonant capacitor voltage |V.sub.cr(t)|, the control target resonant capacitor voltage V.sub.crref, the rising signal V.sub.t, and the switching signal V.sub.gs-High, with their changes over time. In the graph, the horizontal axis indicates the time t, and the vertical axis indicates the above-mentioned value, voltages, and signals. As shown by the graph in FIG. 11, an output of the rising signal V.sub.t and an inversion of the voltage generation circuit 110 occur when the absolute value of the resonant capacitor voltage |V.sub.cr(t)| reaches the control target resonant capacitor voltage V.sub.crref. As also shown by the graph in FIG. 11, the level of the switching signal V.sub.gs-High that is output to the first switching element Q1 is changed to high at the moment when the voltage generation circuit 110 is inverted.

[0169] FIG. 12 is a circuit diagram showing a circuit example implementable in the controller 2 provided in the control system CS according to the present disclosure. The example shown in FIG. 12 is a combination of the amplitude acquisition circuit EC1, the control target derivation circuit EC2, and the switching signal output circuit EC3. The circuits illustrated in FIG. 12 are connected to the resonant capacitor C.sub.r in the voltage generation circuit 110 provided in the converter 1. The amplitude acquisition circuit EC1, the control target derivation circuit EC2, and the switching signal output circuit EC3 illustrated in FIG. 12 are incorporated in the control signal output circuit 22 for controlling the voltage generation circuit, and thus implemented in the controller 2.

[0170] The amplitude acquisition circuit EC1 and the switching signal output circuit EC3 share the rectifier circuit and the voltage sensor. The rectifier circuit is connected to the resonant capacitor C.sub.r in the voltage generation circuit 110 and detects the voltage across the resonant capacitor C.sub.r. A voltage for the circuits illustrated in FIG. 12 is supplied from detection capacitors that are connected in parallel with the resonant capacitor C.sub.r. The detection capacitors are composed of two series-connected capacitors and configured to detect a divided resonant capacitor voltage. Voltage division of the resonant capacitor voltage can remove the DC component contained in the resonant capacitor voltage and can also reduce the voltage to be detected.

[0171] The amplitude acquisition circuit EC1 receives an input of the resonant capacitor voltage, and outputs the amplitude V.sub.crpeak of the resonant capacitor voltage to the control target derivation circuit EC2. The control target derivation circuit EC2 receives an input of the amplitude V.sub.crpeak of the resonant capacitor voltage, and outputs the control target resonant capacitor voltage V.sub.crref to the switching signal output circuit EC3. The switching signal output circuit EC3 receives inputs of the resonant capacitor voltage and the control target resonant capacitor voltage V.sub.crref, and outputs the switching signals V.sub.gs-High, V.sub.gs-Low to the voltage generation circuit 110.

[0172] In the manner described above, the control system CS according to the first embodiment controls the power of the converter 1, and thereby achieves the power factor control based on the power control.

[0173] <Simulation Results>

[0174] To compare the performance, the above-described power factor control and the conventional frequency control were applied to the control system CS according to the present disclosure. The power factor control corresponds to the application example of the control method according to the present disclosure. The method for the power factor control was based on the power control described in the first embodiment. In both of the power factor control and the frequency control, the same converter 1 was used under the following conditions.

[0175] Input voltage: 100 [V] AC, to be rectified into DC

[0176] Resonant capacitor: 125 [nF]

[0177] Leakage inductance in the primary circuit: 20 [uH]

[0178] Magnetizing inductance: 40 [uH]

[0179] Leakage inductance in the secondary circuit: 0.0001 [nH]

[0180] Turns ratio: 2:1:1

[0181] Output capacitor: 12.5 [uF]

[0182] Output voltage: 12.5 [V] DC

[0183] FIG. 13 a graph showing an example of simulation conditions for the control system CS according to the present disclosure. FIG. 13 shows the first order transfer functions for the power factor control and the frequency control, where the horizontal axis indicates the frequency [Hz] of the AC voltage source and the vertical axis indicates the gain [dB]. In this graph, the symbol “∘” represents the first order transfer function for the power factor control, and the symbol “×” represents the first order transfer function for the frequency control. As a condition for the comparative experiment between the power factor control and the frequency control, the respective crossover frequencies (circled in the graph of FIG. 13) were matched substantially so as to avoid a difference in control response speed.

[0184] FIGS. 14 to 16 are graphs showing examples of simulation results in the control system CS according to the present disclosure. FIGS. 14 to 16 show frequency characteristics with respect to the load R.sub.L under the power factor control and the frequency control, where the horizontal axis indicates the frequency [Hz] of the AC current source and the vertical axis indicates the output impedance [dBω]. FIGS. 14, 15, and 16 show frequency characteristics with the loads R.sub.L of 0.5 [Ω], 2.0 [Ω], and 4.0 [Ω], respectively. In these graphs, the symbol “∘” represents frequency characteristics of the output impedance under the power factor control, and the symbol “×” represents frequency characteristics of the output impedance under the frequency control. As shown in FIGS. 14 to 16, the power factor control can keep lower output impedances for all types of loads R.sub.L, particularly in the low-frequency band.

[0185] FIGS. 17 and 18 are graphs showing examples of simulation results in the control system CS according to the present disclosure. FIGS. 17 and 18 show responsiveness to the load R.sub.L under the power factor control and the frequency control, where the horizontal axis indicates the time [s] and the vertical axis indicates the output voltage V.sub.o [V]. FIG. 17 shows responsiveness when the load R.sub.L changed stepwise from 2 [Ω] to 0.5 [Ω] at 0.020 [s]. FIG. 18 shows responsiveness when the load R.sub.L changed stepwise from 2 [Ω] to 4 [Ω] at 0.020 [s]. In each graph, the solid line represents the output voltage V.sub.o that changed over time under the power factor control, and the dashed line represents the output voltage V.sub.o that changed over time under the frequency control. As shown in FIGS. 17 and 18, the power factor control responded more quickly to the load changes, both the increase and decrease in the load, than the frequency control.

Second Embodiment

[0186] The power factor can be represented as a phase difference between the amplitude of the input voltage in the primary circuit (primary voltage) and the amplitude of the primary current. The second embodiment controls the power factor by controlling the phase difference.

[0187] A method for the power factor control based on the phase difference control involves measuring the phase of an input current as a reference phase, obtaining a phase difference between the measured reference phase and a phase of a voltage generated by the voltage generation circuit 110, and implementing feedback control of the converter 1 based on the phase difference. To control the converter 1 by the voltage generation circuit control signals that are output from the controller 2, the second embodiment is configured to control the power factor by controlling a time from the reference phase of the primary current until the moment when the input voltage starts rising, and thereby indirectly controlling the phase.

[0188] The power factor control based on the phase control can be implemented, for example, by acquiring a reference phase, acquiring a time elapsed from the reference phase, and outputting voltage generation circuit control signals based on the reference phase and the elapsed time.

[0189] Ideally, the reference phase necessary for the phase difference control is acquired by detection of an electric current by a current sensor. However, the current sensor, due to its significant delay, is unsuitable to control an LLC converter operated at high frequencies. In the second embodiment, the control system CS acquires the reference phase by detecting a phase of the resonant capacitor voltage that is obtained as an integral of the primary current.

[0190] FIG. 19 is a circuit diagram showing a circuit example implementable in the controller 2 provided in the control system CS according to the present disclosure. FIG. 19 shows an example of a reference phase acquisition circuit EC4 that acquires a reference phase. The reference phase acquisition circuit EC4 includes a comparator that acquires the resonant capacitor voltage V.sub.cr from the resonant capacitor C.sub.r provided in the converter 1 and that compares the acquired resonant capacitor voltage V.sub.cr with a ground potential. The circuit illustrated in FIG. 19 acquires the resonant capacitor voltage V.sub.cr as a divided voltage. Based on the comparison between the resonant capacitor voltage V.sub.cr and the ground potential, the comparator outputs a high-level or low-level polar signal V.sub.zero to a modulator circuit. Specifically, when the resonant capacitor voltage V.sub.cr is higher than the ground potential (i.e., positive), the comparator outputs a low-level polar signal V.sub.zero when the resonant capacitor voltage V.sub.cr is lower than the ground potential (i.e., negative), the comparator outputs a high-level polar signal V.sub.zero. The modulator circuit is configured using an XOR circuit. The modulator circuit modulates the pulse width of a pulse that is output as the polar signal V.sub.zero that inverts between high-level and low-level, and outputs the modulated pulse as a reference phase signal V.sub.reset. Specifically, as the reference phase signal V.sub.reset, the modulator circuit outputs a pulse that indicates the moment when the level of the polar signal V.sub.zero changes from low to high.

[0191] FIG. 20 is a graph showing an example of waveforms relating to the controller 2 provided in the control system CS according to the present disclosure. FIG. 20 shows the primary current I.sub.r, the resonant capacitor voltage V.sub.cr, the polar signal V.sub.zero, and the reference phase signal V.sub.reset, with their changes over time. In the graph, the horizontal axis indicates the time t, and the vertical axis indicates the above-mentioned current, voltage, and signals. As shown by the graph in FIG. 20, the comparator outputs the polar signal V.sub.zero that is a pulse inverted according to the polarity of the resonant capacitor voltage V.sub.cr. As also illustrated in FIG. 20, the moment when the pulse rises from low-level to high-level corresponds to the moment when the resonant capacitor voltage V.sub.cr is inverted from positive to negative. The modulator circuit outputs the pulse-width-modulated reference phase signal V.sub.reset at the moment when the pulse for the polar signal V.sub.zero is inverted from low-level to high-level. The reference phase signal V.sub.reset is always output at the moment when the resonant capacitor voltage V.sub.cr is inverted from positive to negative, which means that the reference phase signal V.sub.reset is always output at the same phase of the primary current I.sub.r. In other words, the reference phase signal V.sub.reset serves as a reference phase acquisition signal.

[0192] FIG. 21 is a circuit diagram showing a circuit example implementable in the controller 2 provided in the control system CS according to the present disclosure. FIG. 21 shows an example of a waveform generation circuit EC5 that generates a time-varying waveform that changes over time. The waveform generation circuit EC5 can acquire a time elapsed from the reference phase, from this time-varying waveform. As the time-varying waveform, the waveform generation circuit EC5 generates a sawtooth wave in which the voltage varies along a uniform slope relative to the time in a given time period. From the voltage of the sawtooth wave generated as the time-varying waveform, the waveform generation circuit EC5 can acquire the elapsed time. The waveform generation circuit EC5 illustrated in FIG. 21 includes a reset circuit using a charging power source, a charging capacitor, and a MOSFET. While the charging capacitor is charged by the charging power source, a voltage across the charging capacitor rises proportionately to the elapsed time. When the reference phase signal V.sub.reset is input to the gate terminal of the reset circuit, the charging capacitor discharges. As a result, the waveform of the voltage across the charging capacitor is a sawtooth wave that rises along a uniform slope relative to the time elapsed from the input of the reference phase signal V.sub.reset. The waveform generation circuit EC5 thus generates the time-varying sawtooth wave, and outputs a sawtooth wave voltage V.sub.saw based on the generated sawtooth wave. Note that the waveform generated by the waveform generation circuit EC5 is not limited to the sawtooth wave, and may be any waveform that changes with time.

[0193] FIG. 22 is a graph showing an example of waveforms relating to the controller 2 provided in the control system CS according to the present disclosure. FIG. 22 shows the resonant capacitor voltage V.sub.cr, the reference phase signal V.sub.reset, and the sawtooth wave voltage V.sub.saw, with their changes over time. In the graph, the horizontal axis indicates the time t, and the vertical axis indicates the above-mentioned signal and voltages. As shown in FIG. 22, the waveform generation circuit EC5 receives an input of the reference phase signal V.sub.reset, every time the resonant capacitor voltage V.sub.cr is inverted from positive to negative. In a time period after the input of the reference phase signal V.sub.reset until an input of a next reference phase signal V.sub.reset, the waveform generation circuit EC5 outputs the sawtooth wave voltage V.sub.saw that increases proportionately to the elapsed time, as represented by the Formula 16 below. Eventually, the waveform generation circuit EC5 can output the elapsed time t from the reference phase, in the form of the sawtooth wave voltage V.sub.saw.

V.sub.saw=kt  Formula 16

where

[0194] V.sub.saw: voltage of the sawtooth wave

[0195] k: slope of the sawtooth wave

[0196] t: time elapsed from the reference phase

[0197] FIG. 23 is a block diagram showing a circuit example implementable in the controller 2 provided in the control system CS according to the present disclosure. The block diagram of FIG. 23 shows an example of a phase difference calculation circuit EC6 provided in the controller 2. The phase difference calculation circuit EC6 receives a desired phase difference and outputs a direct current at a voltage value in proportion to the phase difference. To be specific, the phase difference calculation circuit EC6 receives an input of the desired phase difference (target phase difference θ), and outputs a target phase difference voltage V.sub.t that is a DC voltage corresponding to the target phase difference θ. In other words, the phase difference calculation circuit ECG outputs a target value corresponding to the target phase difference θ. The target phase difference θ is converted to the target phase difference voltage V.sub.t according to Formula 17 below. The target phase difference θ may be set in advance or may be derived from the phase difference that is a desired value for control and that is derived from the output voltage V.sub.o supplied from the secondary circuit 13. For implementation, the target phase difference θ may be substituted with the elapsed time t from the reference phase, as described later. This is why the input is represented by “t” in FIG. 23.

V.sub.t=V.sub.max_saw×(θ/2Π)k  Formula 17

where

[0198] V.sub.t: target phase difference voltage

[0199] V.sub.max_saw: maximum voltage value of the sawtooth wave voltage

[0200] θ: target phase difference θ (phase difference from the reference phase)

[0201] FIG. 24 is a circuit diagram showing a circuit example implementable in the controller 2 provided in the control system CS according to the present disclosure. FIG. 24 illustrates an example of a switching signal output circuit EC7 that outputs switching signals V.sub.gs-High, V.sub.gs-Low, based on the sawtooth wave voltage V.sub.saw and the target phase difference θ. The switching signal output circuit EC7 is composed of various circuits and components including a first comparator, a second comparator, an AND gate, a NOT gate, and a T/2 generation circuit. The first comparator compares the sawtooth wave voltage V.sub.saw that is output from the waveform generation circuit EC5, with the target phase difference voltage V.sub.t that is output from the phase difference calculation circuit ECG. The first comparator then outputs a high-level signal or a low-level signal to the AND gate. Specifically, when the sawtooth wave voltage V.sub.saw exceeds the target phase difference voltage V.sub.t, the first comparator changes the level of the output signal to the AND gate from low to high. In other words, the first comparator outputs a high-level signal after a predetermined elapsed time t has passed from the reference phase. The T/2 generation circuit outputs a T/2 voltage V.sub.T/2, which corresponds to a half of the maximum value of the sawtooth wave voltage V.sub.saw. The voltage V.sub.T/2 corresponding to a half of the maximum value of the sawtooth wave voltage V.sub.saw serves as a replacement value for a half-cycle time of the primary current I.sub.r. The second comparator compares the sum of the target phase difference voltage V.sub.t and the T/2 voltage V.sub.T/2 with the sawtooth wave voltage V.sub.saw. When the sawtooth wave voltage V.sub.saw exceeds the sum of the target phase difference voltage V.sub.t and the T/2 voltage V.sub.T/2, the second comparator changes the level of the output signal to the AND gate from high to low. In other words, the second comparator outputs a low-level signal to the AND gate after a half cycle has passed since the output signal from the first comparator was changed to the high-level signal. This configuration ensures a half-cycle time difference after the level of the signal from the first comparator was changed to high until the level of the signal from the second comparator is changed to low. The half-cycle time difference allows the AND gate to output pulses with a 50% duty cycle. The AND gate outputs a switching signal V.sub.gs-High to the gate terminal of the first switching element Q1, and outputs a switching signal V.sub.gs-Low to the gate terminal of the second switching element Q2. The switching signal V.sub.gs-High represents a logical conjunction of the input signals from the first and second comparators. The switching signal V.sub.gs-Low is an inversion of the switching signal V.sub.gs-High that represents the logical conjunction.

[0202] FIG. 25 is a graph showing an example of waveforms relating to the controller 2 provided in the control system CS according to the present disclosure. FIG. 25 shows the primary current I.sub.r, the resonant capacitor voltage V.sub.cr, the sawtooth wave voltage V.sub.saw, and the switching signal V.sub.gs-High, with their changes over time. In the graph, the horizontal axis indicates the time t, and the vertical axis indicates the above-mentioned current, voltages, and signal. As shown by the graph in FIG. 25, the sawtooth wave voltage V.sub.saw increases proportionately to the elapsed time from the reference phase of the primary current I.sub.r until its next reference phase. After a predetermined elapsed time t has passed from the reference phase, the sawtooth wave voltage V.sub.saw reaches the target phase difference voltage V.sub.t, and the level of the switching signal V.sub.gs-High is changed to high. Later, when a half cycle has passed since the level of the switching signal V.sub.gs-High was changed to high, the sawtooth wave voltage V.sub.saw reaches the sum of the target phase difference voltage V.sub.t and the T/2 voltage V.sub.T2, and the level of the switching signal V.sub.gs-High is changed to low.

[0203] FIG. 26 is a circuit diagram showing a circuit example implementable in the controller 2 provided in the control system CS according to the present disclosure. The example shown in FIG. 26 is a combination of the reference phase acquisition circuit EC4, the waveform generation circuit ECS, the phase difference calculation circuit EC6, and the switching signal output circuit EC7. For convenience of illustration, the phase difference calculation circuit EC6 is separated from the other circuits, but actually the target phase difference voltage V.sub.t is output from the phase difference calculation circuit EC6 to the switching signal output circuit EC7. The reference phase acquisition circuit EC4, the waveform generation circuit EC5, the phase difference calculation circuit ECG, and the switching signal output circuit EC7 illustrated in FIG. 26 are incorporated in the control signal output circuit 22 for controlling the voltage generation circuit, and thus implemented in the controller 2.

[0204] The reference phase acquisition circuit EC4 is connected to the resonant capacitor C.sub.r in the voltage generation circuit 110 and detects the resonant capacitor voltage V.sub.cr. The circuits illustrated in FIG. 26 acquire a divided voltage from the detection capacitors that are connected in parallel with the resonant capacitor C.sub.r.

[0205] The reference phase acquisition circuit EC4 receives an input of the resonant capacitor voltage V.sub.cr, and outputs the reference phase signal V.sub.reset that represents the reference phase to the waveform generation circuit EC5. The waveform generation circuit EC5 receives an input of the reference phase signal V.sub.reset, and outputs the sawtooth wave voltage V.sub.saw to the switching signal output circuit EC7. The sawtooth wave voltage V.sub.saw serves as a replacement value for the time elapsed from the reference phase. The phase difference calculation circuit EC6 receives an input of the target time difference (predetermined elapsed time t from the reference phase) corresponding to the desired phase difference, and outputs the target phase difference voltage V.sub.t to the switching signal output circuit EC7. The switching signal output circuit EC7 receives inputs of the sawtooth wave voltage V.sub.saw and the target phase difference voltage V.sub.t, and outputs the switching signals V.sub.gs-High, V.sub.gs-Low to the voltage generation circuit 110.

[0206] In the manner described above, the control system CS according to the second embodiment controls the phase of the converter 1, and thereby achieves the power factor control based on the phase control.

[0207] <Simulation Results>

[0208] To compare the performance, the power factor control and the frequency control were applied to the control system CS according to the present disclosure. The method for the power factor control was based on the phase control described in the second embodiment. In both of the power factor control and the frequency control, the same converter 1 was used under the following conditions.

[0209] Input voltage: 100 [V] AC, to be rectified into DC

[0210] Resonant capacitor: 125 [nF]

[0211] Leakage inductance in the primary circuit: 20 [uH]

[0212] Magnetizing inductance: 40 [uH]

[0213] Leakage inductance in the secondary circuit: 0.0001 [nH]

[0214] Turns ratio: 2:1:1

[0215] Output capacitor: 12.5 [uF]

[0216] Output voltage: 12.5 [V] DC

[0217] FIG. 27 a graph showing an example of simulation conditions for the control system CS according to the present disclosure. FIG. 27 shows the first order transfer functions for the power factor control and the frequency control, where the horizontal axis indicates the frequency [Hz] of the AC voltage source and the vertical axis indicates the gain [dB]. In this graph, the symbol “∘” represents the first order transfer function for the power factor control, and the symbol “×” represents the first order transfer function for the frequency control. As a condition for the comparative experiment between the power factor control and the frequency control, the respective crossover frequencies (circled in the graph of FIG. 27) were matched substantially so as to avoid a difference in control response speed.

[0218] FIGS. 28 to 30 are graphs showing examples of simulation results in the control system CS according to the present disclosure. FIGS. 28 to 30 show frequency characteristics with respect to the load R.sub.L under the power factor control and the frequency control, where the horizontal axis indicates the frequency [Hz] of the AC current source and the vertical axis indicates the output impedance [dBΩ]. FIGS. 28, 29, and 30 show frequency characteristics with the loads R.sub.L of 0.5 [Ω], 2.0 [Ω], and 4.0 [Ω], respectively. In these graphs, the symbol “∘” represents frequency characteristics of the output impedance under the power factor control, and the symbol “×” represents frequency characteristics of the output impedance under the frequency control. As shown in FIGS. 28 to 30, the power factor control can keep lower output impedances for all types of loads R.sub.L. This tendency is particularly noticeable in the low-frequency band.

[0219] FIGS. 31 and 32 are graphs showing examples of simulation results in the control system CS according to the present disclosure. FIGS. 31 and 32 show responsiveness to the load R.sub.L under the power factor control and the frequency control, where the horizontal axis indicates the time [s] and the vertical axis indicates the output voltage V.sub.o [V]. FIG. 31 shows responsiveness when the load R.sub.L changed stepwise from 2 [Ω] to 0.5 [Ω] at 0.020 [s]. FIG. 32 shows responsiveness when the load R.sub.L changed stepwise from 2 [Ω] to 4 [Ω] at 0.020 [s]. In each graph, the solid line represents the output voltage V.sub.o that changed over time under the power factor control, and the dashed line represents the output voltage V.sub.o that changed over time under the frequency control. As shown in FIGS. 31 and 32, the power factor control responded more quickly to the load changes, both the increase and decrease in the load, than the frequency control.

[0220] The control method according to the present disclosure has been described by way of the examples in the first and second embodiments above. In this control method, the converter 1 including the resonant circuit 111 such as the LLC converter is controlled by the power factor-based control. As a result, the control method according to the present disclosure provides remarkable effects and, for example, is expected to improve load responsiveness.

[0221] The present invention is not limited to the above-described embodiments, and can be embodied and practiced in other different forms. Therefore, the above-described embodiments are considered in all respects as illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than by the foregoing description. All variations and modifications falling within the equivalency range of the appended claims are intended to be embraced therein.

[0222] For example, the above embodiments relate to the examples of the power factor control based on the voltage control and the power factor control based on the phase control. However, the present invention is not limited to such examples and can be developed to implement the power factor control in various manners.

[0223] Further, for example, the above embodiments relate to the examples using an LLC converter as the resonant circuit 111. However, the present invention is not limited to such examples, and can be embodied with use of various types of resonant circuit 111 such as a CLLC converter. Alternatively, the resonant circuit 111 may be a circuit without a transformer such as a non-isolated resonant converter, in which case the LC resonant circuit is directly subjected to rectification to produce an output.

[0224] Further, for example, the above embodiments relate to the examples in which the current through the resonant circuit is converted to a DC voltage by the rectifier circuit and the rectified DC voltage is output through the output circuit. However, the output does not necessarily have to be the DC voltage and, for example, may be an unrectified AC voltage. Alternatively, the output may be an alternating current flowing through the resonant circuit.

[0225] Further, the present invention is also applicable to, for example, a magnetic resonant wireless power feeding device, which is a power converter that excites resonance between a transmitter coil and a resonant capacitor by using an inverter and that transmits power to a remote receiver by using an AC magnetic field generated by a resonant current. In this case, the present invention is applied in order to control an amplitude of the resonant current at a given value, and is configured to set the control target power factor in accordance with a difference between the amplitude of the resonant current and a target amplitude of the resonant current.

[0226] In the above embodiments, the target power factor is set in accordance with the difference between the DC output voltage and its target value, but this is not necessarily the case. For example, when the output is an AC voltage, the target power factor may be set in accordance with a difference between an output AC amplitude and its target value. Alternatively, the target power factor may be set in accordance with a difference between an output current (e.g., an output direct current or an output alternating current) and its target value, or in accordance with a difference between power (e.g., DC power or AC power) and its target value. Furthermore, the target power factor may be set in accordance with the difference from any of the above-mentioned target values together with an additional value, rather than the difference alone. A possible example is to subject the difference between the DC output voltage and its target value to proportional and integral actions, then to add/subtract, to/from the resulting value, a value corresponding to the amplitude of the resonant current, and finally to set the power factor in accordance with a value resulting from the addition/subtraction.

[0227] Further, the above embodiments use a half-bridge circuit as the switching circuit. However, the switching circuit in the present invention is not necessarily limited thereto, and may be a full-bridge circuit or a circuit capable of outputting a freely-selected AC voltage. Furthermore, the voltage generation circuit does not necessarily have to be a switching circuit, but may be any circuit capable of generating a voltage that contains an alternating current for driving the resonant circuit 111.

[0228] The various circuits described in the above embodiments can be also implemented as their equivalent circuits.

REFERENCE SIGNS LIST

[0229] CS control system [0230] 1 converter [0231] 10 input power source [0232] 11 primary circuit [0233] 110 voltage generation circuit [0234] 111 resonant circuit [0235] 12 coupling circuit [0236] 13 secondary circuit [0237] 2 controller [0238] 20 comparator unit [0239] 21 target control unit [0240] 22 control signal output circuit for controlling the voltage generation circuit [0241] EC1 amplitude acquisition circuit [0242] EC2 control target derivation circuit [0243] EC3 switching signal output circuit [0244] EC4 reference phase acquisition circuit [0245] EC5 waveform generation circuit [0246] EC6 phase difference calculation circuit [0247] EC7 switching signal output circuit