Printed Circuit Board and Method Manufacturing the Same

Abstract

A printed circuit board is provided which comprises a core layer of a conductive metal having a thickness between 30 micrometer and 120 micrometer, an upper dielectric layer and a lower dielectric layer sandwiching the core layer; an upper conductive layer arranged above the upper dielectric layer and a lower conductive layer arranged below the lower dielectric layer; at least one via passing from the upper conductive layer to the lower conductive layer and filled at least partially with the dielectric material of the upper and/or lower dielectric layer; and at least one and blind via, connecting the upper conductive layer with the core layer.

Claims

1. A printed circuit board comprising: a core layer of a conductive metal having a thickness between 30 micrometer and 120 micrometer, an upper dielectric layer and a lower dielectric layer sandwiching the core layer, an upper conductive layer arranged above the upper dielectric layer and a lower conductive layer arranged below the lower dielectric layer; at least one through via passing from the upper conductive layer to the lower conductive layer and filled at least partially with the dielectric material of the upper and/or lower dielectric layer; and at least one and blind via, connecting the upper conductive layer with the core layer.

2. The printed circuit board according to claim 1, wherein the dielectric material is selected out of the group consisting of: FR-4 materials; resin; bismaleimide triazine resin; cyanate ester; glass; glass fibers; prepreg materials; polyimide; liquid crystal polymers; epoxy based build-up film; ceramic material; Teflon; metal oxide; and a combination thereof.

3. The printed circuit board according to claim 1, wherein a diameter of the at least one through via is below 500 micrometer.

4. The printed circuit board according to claim 1, further comprising: an upper outer conductive layer; and a lower outer conductive layer, wherein the upper outer conductive layer is arranged above the upper conductive layer and the lower outer conductive layer is arranged below the lower conductive layer.

5. The printed circuit board according to claim 1, wherein in the through via a conductive hole wall is formed by an electrically conductive material surrounded by the filled dielectric material.

6. The printed circuit board according to claim 1, wherein the at least one blind via has a diameter in the range of 10 micrometer to 150 micrometer.

7. The printed circuit board according to claim 1, wherein the printed circuit board further comprises a second blind via connecting the lower conductive layer with the core layer.

8. An electronic assembly, comprising: a printed circuit board having a core layer of a conductive metal having a thickness between 30 micrometer and 120 micrometer, an upper dielectric layer and a lower dielectric layer sandwiching the core layer, an upper conductive layer arranged above the upper dielectric layer and a lower conductive layer arranged below the lower dielectric layer, at least one through via passing from the upper conductive layer to the lower conductive layer and filled at least partially with the dielectric material of the upper and/or lower dielectric layer, at least one and blind via, connecting the upper conductive layer with the core layer, and an electronic circuitry arranged on the printed circuit board.

9. The electronic component according to claim 8, wherein the electronic circuitry forms at least one electronic component which is selected out of the group consisting of: active electronic component; passive electronic component; data storage; filter; integrated circuit; signal processing component; power management component; optoelectrical interface; voltage converter; cryptographic component; capacity; resistance; sending unit; receiving unit; transceiving unit; electro-mechanical converter; inductivity; switch; microelectromechanical system; battery; camera; and antenna.

10. A method of manufacturing a printed circuit board, the method comprising: providing a metallic core layer having a thickness between 30 micrometer and 120 micrometer and having arranged thereon at least one dielectric layer on a main surface of the metallic core layer; forming a through hole through the metallic core layer; forming a second dielectric layer on a second main surface opposite to the upper main surface of the metallic core layer; and at least partially filling the through hole with material of the second dielectric layer.

11. The method according to claim 10, the method further comprising: forming the metallic core layer having the at least one dielectric layer arranged thereon by removing an auxiliary layer.

12. The method according to claim 10, the method further comprising: forming a first conductive layer on the first dielectric layer and a second conductive layer on the second dielectric layer.

13. The method according to claim 12, further comprising: forming a second through hole from the first conductive layer to the second conductive layer at a position of the through hole which is at least partially filled with dielectric material and which forms the through via.

14. The method according to claim 13, wherein the through hole which is at least partially filled with dielectric material and which forms the through via has a larger diameter than the second through hole.

15. The method according to claim 12, further comprising: forming at least one blind hole reaching from the first conductive layer to the metallic core.

16. The method according to claim 10 further comprising: etching the second main surface before forming the second dielectric layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The drawing is not necessarily to scale. Instead emphasis is generally being placed upon illustrating the principles of the invention. In the following description, various embodiments are described with reference to the following drawings, in which:

[0051] FIG. 1 schematically illustrates a cross sectional view of a printed circuit board according to an exemplary embodiment;

[0052] FIG. 2 schematically illustrate a detail of the cross sectional view of FIG. 1; and

[0053] FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D and FIG. 3E schematically illustrate a manufacturing process of a printed circuit board according to an exemplary embodiment.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0054] The illustration in the drawing is presented schematically and not necessarily to scale. It is noted that in different figures, similar or identical elements or features are provided with the same reference signs. In order to avoid unnecessary repetitions elements or features which have already been elucidated with respect to a previously described figure are not elucidated again at a later position of the description.

[0055] Further, spatially relative terms, such as front and back, above and below, left and right, et cetera are used to describe an element's relationship to another element(s) as illustrated in the figures. Thus, the spatially relative terms may apply to orientations in use, which differ from the orientation depicted in the figures. Obviously, though, all such spatially relative terms refer to the orientation shown in the figures for ease of description and are not necessarily limiting as an apparatus according to an embodiment of the invention can assume orientations different than those illustrated in the figures when in use.

[0056] FIG. 1 schematically illustrates a cross sectional view of a printed circuit board (PCB) 100 according to an exemplary embodiment. In particular, the PCB 100 comprises a central core layer 101, e.g. comprising or consisting of copper, aluminum or another suitable material having a high thermal and/or electrical conductivity, and having a thickness in the range of 75 micrometer to 125 micrometer. The core layer 101 has a plate like structure comprising two main surfaces (upper and lower in FIG. 1) whereon an upper dielectric layer 102 and a lower dielectric layer 103 are formed, e.g. by a lamination process. One or both dielectric layers may comprise or may consist of FR-4 material. Furthermore, the PCB 100 comprises an upper (structured) conductive layer 104 and a lower (structured) conductive layer 105. The conductive layers may have integrated circuits formed thereon or therein.

[0057] For thermally connecting the conductive layers 104 and 105 with the core layer 101 blind vias 106 and 107 are formed in the upper and lower dielectric layers, respectively. For example, the blind vias may be formed by using a laser typically resulting in a slightly conical shape as shown in FIG. 1. Preferably the blind vias are filled with heat conductive material in order to provide a good thermal connection to the core layer. However, they may as well be partially or fully unfilled.

[0058] For electrically connecting the conductive layers 104 and 105 to each other a through via 108 is formed through the dielectric layers and the core layer. The through via may be formed by forming a through hole at least through the core layer 101. The through hole may be etched or mechanically drilled. In a later step the through hole is at least partially filled with a dielectric material. For example, some of the dielectric material may fill or cover at least the sidewalls of the formed through hole. In case a (radially) central portion or part of the through hole is still unfilled or void by the dielectric material a conductive material may flow into the void and forms a conductive path through the core layer 101 which is electrically isolated from the core layer 101 by the dielectric material partially filling the through hole. The conductive material forming the conductive path may fully fill the void or may only form a cover layer leaving as well a (radially) central part or portion free of material. As described the dielectric material partially filling the through hole is preferably the same as the dielectric material of at least one of the dielectric layers 102 and 103 and may be filled in a through hole during the forming (e.g. by laminating) of the respective at least one dielectric layer.

[0059] It should be noted that of course additional dielectric layer(s) and conductive layer(s) may be formed on upper and lower conductive layers, which as well may be thermally and/or electrically connected with each other and/or the core layer by blind via(s) and/or through via(s). Such additional layer(s) may enable an electronic device having higher integration of circuitry. Furthermore, additional passive and/or electric components may be integrated or embedded in the PCB as well. For example, passive components like resistances, coils, capacitors or the like and/or electronic circuitry like IC chips or dies may be embedded or integrated already into the PCB.

[0060] FIG. 2 schematically illustrate a detail of the cross sectional view of FIG. 1. In particular, FIG. 2 shows the through via 108 in an enlarged view. As can be seen in FIG. 2, the through via 108 is formed in a through hole formed in the core layer 101 and the first and second dielectric layers 102 and 103 sandwiching the core layer. However some of the dielectric material of one of the dielectric layers, e.g. the upper dielectric layer 102, forms a cover layer or isolation layer 210 on the core layer 101 electrically isolating the same from a (radially) center portion of the through via 108. For forming an electrically conductive path 211 from the upper conductive layer 104 through the dielectric layers 102 and 103 and the core layer 101 to the lower conductive layer 105. As indicated in FIG. 2 the conductive path is formed by a layer of electrically conductive material, like copper, formed on the dielectric material of the isolation layer 210. The thickness of the conductive path 211 or conductive hole wall may be selected according to the wished electrical resistance. However, it should be noted that the conductive path may as well completely fill the through hole.

[0061] FIG. 3A to FIG. 3E schematically illustrates a manufacturing process of a printed circuit board according to an exemplary embodiment. In particular, FIG. 3A shows a commonly used multilayer structure 300 comprising a central dielectric layer 303, e.g. comprising or consisting of an FR-4 material, having attached on main surfaces thereof an upper conductive layer 301 and a lower conductive layer 320. The conductive layers 301 and 320 may comprise or may consist of any suitable conductive material like metal, e.g. copper. A thickness of the conductive layers may be about 100 micrometer.

[0062] FIG. 3B shows the multilayer structure 300 of FIG. 3A after removing one of the conductive layers, e.g. the lower conductive layer, so that only the dielectric layer 303 and the conductive layer 301 remain.

[0063] FIG. 3C shows the multilayer structure 300 of FIG. 3B after a hole or recess is formed through the conductive layer 301. The through hole may be formed by etching or mechanical or laser drilling.

[0064] FIG. 3D shows the multilayer structure 300 of FIG. 3C after a further dielectric layer 302 is formed on the conductive layer 301, which is now a core conductive layer. In additional also on the dielectric layer 303 additional dielectric material may be formed which may be useful for levelling the thicknesses of the dielectric layers 302 and 303. For example the dielectric layers may be formed by applying sheet like dielectric material thereon, which may then subsequently pressed together. It should be noted that core conductive layer 301 may be roughened before the further dielectric layer 302 is formed. During the forming of the further dielectric layer 302 (and/or the forming of the depositing of the additional dielectric material on the lower dielectric layer 303) some dielectric material flows into the through hole formed in the core conductive layer 301.

[0065] In particular, the dielectric material flowing into the through hole may completely or only partially fill the through hole. However, at least a layer covering the (in FIG. 3 vertically) sidewalls of the through hole in the region of the conductive core layer 301 forming thereby an isolation layer electrically isolating the conductive core layer 301 from a conductive path formed later in the through hole to form a via electrically connecting the upper side and the lower side of the PBC. Such a via is used to electrically connect an upper (structured) conductive layer 304 and a lower (structured) conductive layer 305.

[0066] FIG. 3E shows the multilayer structure 300 of FIG. 3D after process steps for forming the through via and some blind holes. In particular, FIG. 3E shows that a first blind hole 306 is formed in the upper conductive layer 304 and a second blind hole 307 is formed in the lower conductive layer 305. Both blind holes are preferably formed by a laser process, but may be mechanically drilled or etched as well. The blind holes provide thermal coupling of the central core layer 301 with the upper and lower conductive layers 304 and 305, respectively. The blind holes 306 and 307 may be unfilled, partially filled or completely filled with material, e.g. thermally and electrically conductive material and may then function as a ground connection as well.

[0067] Furthermore, the above described isolation layer 310 isolating the central core layer 301 from a conductive hole wall 311 of the through via can be seen in FIG. 3E. In addition, a void is schematically shown in FIG. 3E. For forming the conductive hole wall 311 electrically connecting the upper conductive layer 304 and the lower conductive layer 305 a further through hole is formed in the region of the first through hole which is partially filled by the isolation layer 310 was formed beforehand. The further through hole can be mechanically drilled, etched or preferably formed by a laser process. It should be noted that the central void is optional and may be filled as well with an electrically conductive or isolating material depending on the desired resistance value the electrical connection between the two outer conductive layers 304 and 305.

[0068] It should further be noted that the (outermost) conductive layers may as well have holes not filled with any material and forming the central portion of the through via(s) or may form complete plate-like or sheet-like layers completely covering the PCB. Furthermore, it should be noted that the further through hole may be formed before forming the upper and lower conductive layers 304 and 305. Thus, it may be possible that the conductive hole wall 311 is formed during the forming of the conductive layers automatically by material of the conductive layers flowing into the further through hole.

[0069] It should also be noted that the term comprising does not exclude other elements or features and the a or an does not exclude a plurality. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs shall not be construed as limiting the scope of the claims. While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

LIST OF REFERENCE SIGNS

[0070] 100 Printed circuit board [0071] 101 Core layer [0072] 102, 103 Dielectric layers [0073] 104, 105 Conductive layers [0074] 106, 107 Blind vias [0075] 108 Through via [0076] 210 cover or isolation layer [0077] 211 conductive path [0078] 300 multilayer structure [0079] 301 conductive layer [0080] 302, 303 dielectric layers [0081] 304, 305 conductive layers [0082] 306, 307 blind holes [0083] 310 isolation layer [0084] 311 conductive hole wall