Abstract
An amplifying circuit allows its loading circuit to contribute a transconductance to increase the bandwidth of the amplifying circuit, and thereby achieves common-mode stabilization. The amplifying circuit includes a first and a second amplifying circuit. The first amplifying circuit is coupled between a high-voltage terminal and a low-voltage terminal, and outputs a first amplified signal according to an input signal. The second amplifying circuit includes: an input-stage circuit configured to receive the input signal and output an input-stage output signal to intermediate nodes; a transconductance and loading circuit coupled between the high-voltage terminal and the input-stage circuit, and configured to output a transconductance-enhancement signal to the intermediate nodes according to the first amplified signal; and an output-stage circuit coupled between the high-voltage terminal and the low-voltage terminal and coupled to the intermediate nodes, and configured to output an output signal according to the input-stage output signal and the transconductance-enhancement signal.
Claims
1. An amplifying circuit, comprising: a first amplifying circuit coupled between a high-voltage terminal and a low-voltage terminal and configured to output a first amplified signal according to an input signal; and a second amplifying circuit including: an input-stage circuit configured to receive the input signal and accordingly output an input-stage output signal to a set of intermediate node(s); a transconductance and loading circuit coupled between the high-voltage terminal and the input-stage circuit, and configured to output a transconductance-enhancement signal to the set of intermediate node(s) according to the first amplified signal; and an output-stage circuit coupled between the high-voltage terminal and the low-voltage terminal and further coupled to the set of intermediate node(s), and configured to output an output signal according to the input-stage output signal and the transconductance-enhancement signal.
2. The amplifying circuit of claim 1, wherein the first amplifying circuit includes: a signal input circuit including a set of input terminal(s) and a set of output terminal(s), the signal input circuit configured to receive the input signal with the set of input terminal(s) and output the first amplified signal with the set of output terminal(s); and a diode-connected circuit coupled between the high-voltage terminal and the set of output terminal(s), and configured to determine a transconductance of the first amplifying circuit in conjunction with the signal input circuit.
3. The amplifying circuit of claim 2, wherein the diode-connected circuit and the transconductance and loading circuit of the second amplifying circuit jointly function as a current mirror.
4. The amplifying circuit of claim 2, wherein the signal input circuit is a pair of NMOS transistors, and the set of input terminal(s) and the set of output terminal(s) are gate terminals of the pair of NMOS transistors and drain terminals of the pair of NMOS transistors respectively; and the diode-connected circuit is a pair of PMOS transistors.
5. The amplifying circuit of claim 2, wherein the first amplifying circuit further includes: a bias circuit coupled between the signal input circuit and the low-voltage terminal, and configured to regulate a current from the signal input circuit to the low-voltage terminal.
6. The amplifying circuit of claim 5, wherein the first amplifying circuit further includes: a common-mode reference voltage generating circuit configured to generate a common-mode reference voltage according to the output signal; and a comparison circuit configured to compare the common-mode reference voltage with a predetermined voltage to output a feedback voltage to the bias circuit so as to allow the bias circuit to regulate the current according to the feedback voltage.
7. The amplifying circuit of claim 1, wherein the first amplifying circuit includes: a signal input circuit including a set of input terminal(s) and a set of output terminal(s), the signal input circuit configured to receive the input signal with the set of input terminal(s) and output the first amplified signal with the set of output terminal(s); and a loading circuit coupled between the high-voltage terminal and the set of output terminal(s), and configured to determine an output impedance of the first amplifying circuit in conjunction with the signal input circuit.
8. The amplifying circuit of claim 7, wherein the loading circuit includes: a pair of loading transistors coupled between the high-voltage terminal and the set of output terminal(s); and a resistor circuit coupled between gate terminals of the pair of loading transistors and drain terminals of the pair of loading transistors, and further coupled with the input-stage circuit of the second amplifying circuit.
9. The amplifying circuit of claim 8, wherein the signal input circuit is a pair of NMOS transistors, and the set of input terminal(s) and the set of output terminal(s) are gate terminals of the pair of NMOS transistors and drain terminals of the pair of NMOS transistors respectively; and the pair of loading transistors is a pair of PMOS transistors.
10. The amplifying circuit of claim 7, wherein the first amplifying circuit further includes: a bias circuit coupled between the signal input circuit and the low-voltage terminal, and configured to regulate a current from the signal input circuit to the low-voltage terminal.
11. The amplifying circuit of claim 10, wherein the first amplifying circuit further includes: a common-mode reference voltage generating circuit configured to generate a common-mode reference voltage according to the output signal; and a comparison circuit configured to compare the common-mode reference voltage with a predetermined voltage to output a feedback voltage to the bias circuit so as to allow the bias circuit to regulate the current according to the feedback voltage.
12. The amplifying circuit of claim 1, wherein the second amplifying circuit further includes: a bias circuit coupled between the input-stage circuit and the low-voltage terminal, and configured to regulate a current from the input-stage circuit to the low-voltage terminal.
13. The amplifying circuit of claim 1, further comprising: a capacitor circuit coupled between the set of intermediate node(s) and a set of output node(s), wherein the set of output node(s) is used for outputting the output signal.
14. The amplifying circuit of claim 1, further comprising: a cascode transistor coupled between the high-voltage terminal and the first amplifying circuit.
15. The amplifying circuit of claim 1, wherein the input signal is an input differential signal composed of complementary input signals, and the output signal is an output differential signal composed of complementary output signals.
16. The amplifying circuit of claim 1, wherein the input-stage circuit, the transconductance and loading circuit, and the output-stage circuit jointly contribute to a transconductance of the second amplifying circuit.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 shows an embodiment of the amplifying circuit of the present disclosure.
[0007] FIG. 2 shows an embodiment of the first amplifying circuit of FIG. 1.
[0008] FIG. 3 shows an embodiment of a feedback-voltage generating circuit for generating the feedback voltage of FIG. 2.
[0009] FIG. 4 shows another embodiment of the first amplifying circuit of FIG. 1.
[0010] FIG. 5 shows another embodiment of the amplifying circuit of the present disclosure.
[0011] FIG. 6 shows the relation between the gain and the frequency with respect to the prior art, the amplifying circuit of FIG. 2, and the amplifying circuit of FIG. 4.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0012] The present specification discloses an amplifying circuit including a loading circuit capable of contributing to the transconductance of the amplifying circuit. Accordingly, the bandwidth of the amplifying circuit is increased, and the efficacy of common-mode stabilization including the efficacy of direct-current (DC) stabilization is improved.
[0013] FIG. 1 shows an embodiment of the amplifying circuit of the present disclosure. The amplifying circuit 100 of FIG. 1 includes a first amplifying circuit 110 and a second amplifying circuit 120.
[0014] Referring to FIG. 1, the first amplifying circuit 110 is coupled between a high-voltage terminal VDD (e.g., a power supply terminal) and a low-voltage terminal GND (e.g., a ground terminal). The first amplifying circuit 110 is configured to output a first amplified signal (e.g., a differential signal composed of complementary signals V.sub.1p, V.sub.1n) varying based on a DC voltage to the second amplifying circuit 120 in accordance with an input signal (e.g., a differential signal composed of complementary signals V.sub.1p, V.sub.1n).
[0015] Referring to FIG. 1, the second amplifying circuit 120 includes an input-stage circuit 122, a bias circuit 124, a transconductance and loading circuit 126, and an output-stage circuit 128. A nonrestrictive embodiment of the input-stage circuit 122 is a pair of NMOS transistors M.sub.1, M.sub.2; and this pair of NMOS transistors M.sub.1, M.sub.2 is configured to receive the input signal V.sub.1p, V.sub.in and accordingly output an input-stage output signal (i.e., signals at the drain terminals of the pair of NMOS transistors M.sub.1, M.sub.2) to a set of intermediate node(s) N.sub.1, N.sub.2. The input-stage circuit 122 can be realized with a pair of PMOS transistors (i.e., a pair of p-channel MOSFETs) according to implementation needs in an alternative embodiment.
[0016] Referring to FIG. 1, a nonrestrictive embodiment of the bias circuit 124 is an NMOS transistor (i.e., an n-channel MOSFET) configured to regulate the current I.sub.i passing through the input-stage circuit 122 in accordance with a predetermined bias V.sub.b1, wherein the predetermined bias V.sub.b1 is determined according to implementation needs.
[0017] Referring to FIG. 1, a nonrestrictive embodiment of the transconductance and loading circuit 126 is a pair of PMOS transistors M.sub.3, M.sub.4 coupled between the high-voltage terminal VDD and the input-stage circuit 122, wherein the pair of PMOS transistors is configured to output a transconductance-enhancement signal (not shown in FIG. 1) to the set of intermediate node(s) N.sub.1, N.sub.2 according to the first amplified signal V.sub.1p, V.sub.1n.
[0018] Referring to FIG. 1, a nonrestrictive embodiment of the output-stage circuit 128 includes a pair of PMOS transistors Ms, M.sub.6 and a pair of NMOS transistors M.sub.7, M.sub.8, and is coupled between the high-voltage terminal VDD and the low-voltage terminal GND and further coupled to the set of intermediate node(s) N.sub.1, N.sub.2. The pair of PMOS transistors Ms, M.sub.6 is configured to output an output signal V.sub.op, V.sub.on according to the input-stage output signal outputted by the input-stage circuit 122 and the transconductance-enhancement signal outputted by the transconductance and loading circuit 126. The pair of NMOS transistors M.sub.7, Ma is configured to regulate the current passing through the output-stage circuit 128 in accordance with a predetermined bias V.sub.b2 which is determined according to implementation needs.
[0019] It is noted that the second amplifying circuit 120 of FIG. 1 is a two-stage operational amplifier, wherein the input-stage circuit 122, the transconductance and loading circuit 126, and the output-stage circuit 128 jointly contribute to the transconductance of the second amplifying circuit 120. This feature can be appreciated from the equation (2) and equation (4) mentioned in the later paragraphs.
[0020] FIG. 2 shows an embodiment of the first amplifying circuit 110 of FIG. 1. The first amplifying circuit 110 of FIG. 2 includes a signal input circuit 210 and a diode-connected circuit 220. A nonrestrictive embodiment of the signal input circuit 210 is a pair of NMOS transistors M.sub.9, M.sub.10. The pair of NMOS transistors M.sub.9, M.sub.10 is configured to receive the input signal V.sub.1p, V.sub.1n with its gate terminals and output the first amplified signal V.sub.1p, V.sub.1n with its drain terminals. It is noted that the signal input circuit 210 can be realized with a pair of PMOS transistors according to implementation needs. A nonrestrictive embodiment of the diode-connected circuit 220 is a pair of PMOS transistors M.sub.1, M.sub.12. The pair of PMOS transistors M.sub.11, M.sub.12 is coupled between the high-voltage terminal VDD and the signal input circuit 210, and is configured to determine the transconductance of the first amplifying circuit 110 (e.g., Gm.sub.9,10/Gm.sub.11,12 in the equations (1)(2)) in conjunction with the signal input circuit 210, which can be appreciated from the equations (1)(2) mentioned in the next paragraph. It is noted that: the diode-connected circuit 220 and the aforementioned transconductance and loading circuit 126 jointly function as a current mirror; the common-mode feedback signal (i.e., the feedback voltage Vb mentioned in the next paragraph) is inputted to the below-mentioned bias circuit 230, and used to achieve the efficacy of DC stabilization through the current mirror.
[0021] Referring to FIG. 2, the first amplifying circuit 110 further includes a bias circuit 230. A nonrestrictive embodiment of the bias circuit 230 is an NMOS transistor that is coupled between the signal input circuit 210 and the low-voltage terminal GND and configured to regulate the current I1 passing through the signal input circuit 210 according to a feedback voltage V.sub.fb. In addition, in order to stabilize the amplifying circuit 100, a capacitor circuit 240 can optionally be set between the set of intermediate node(s) N.sub.1, N.sub.2 and a set of output node(s) N.sub.3, N.sub.4 for outputting the output signal V.sub.op, V.sub.on as shown in FIG. 2. Based on the circuit configuration of FIG. 2, the bandwidth F.sub.T and the gain Av of the amplifying circuit 100 can be represented by the following equation (1) and equation (2) respectively:
[00001]
[0022] In the equations (1)(2), .sub.T denotes an angular frequency, Gm.sub.i,j denotes the transconductance contributed by the transistors M.sub.i, M.sub.j of FIG. 2 (e.g., Gm.sub.1,2 contributed by the transistors M.sub.1, M.sub.2), C.sub.C denotes the capacitance of the capacitor circuit 240, Ro.sub.p,q denotes the output impedance contributed by the transistors M.sub.p, M.sub.q of FIG. 2 (e.g., Ro.sub.1,2 contributed by the transistors M.sub.1, M.sub.2).
[0023] FIG. 3 shows a feedback voltage generating circuit 300 which can be included in the first amplifying circuit 110 or be set outside the first amplifying circuit 110. The feedback voltage generating circuit 300 includes a common-mode reference voltage generating circuit 310 and a comparison circuit 320. The common-mode reference voltage generating circuit 310 includes two sets of resistor-and-capacitor circuits that are connected in series, wherein each of the two sets of resistor-and-capacitor circuits includes a resistor and a capacitor connected in parallel. The two sets of resistor-and-capacitor circuits are configured to generate a common-mode reference voltage V.sub.CI according to the aforementioned output signal V.sub.op, V.sub.on. The comparison circuit 320 is configured to compare the common-mode reference voltage V.sub.CI with a predetermined voltage V.sub.BIAS to generate the aforementioned feedback voltage V.sub.fb, wherein the predetermined voltage V.sub.BIAS is determined according to implementation needs.
[0024] FIG. 4 shows another embodiment of the first amplifying circuit 110 of FIG. 1. The first amplifying circuit 110 of FIG. 4 includes a signal input circuit 410 and a loading circuit 420. A nonrestrictive embodiment of the signal input circuit 410 is a pair of NMOS transistors M.sub.9, M.sub.10. The pair of NMOS transistors M.sub.9, M.sub.10 is configured to receive the input signal V.sub.ip, Vin with its gate terminals and output the first amplified signal V.sub.1p, V.sub.1n with its drain terminals. It is noted that the signal input circuit 210 can be realized with a pair of PMOS transistors according to implementation needs. A nonrestrictive embodiment of the loading circuit 420 includes a pair of PMOS transistors M.sub.11, M.sub.12 and a resistor circuit (e.g., a circuit composed of R.sub.1, R.sub.2 in FIG. 4). The pair of PMOS transistors M.sub.11, M.sub.12 is coupled between the high-voltage terminal VDD and the signal input circuit 410, and is configured to determine the output impedance of the first amplifying circuit 110 (e.g., (Ro.sub.9,10Ro.sub.11,12) in the equations (3)(4)) in conjunction with the signal input circuit 410, which can be appreciated from the equations (3)(4) mentioned in the next paragraph. It is noted that: the resistor circuit is coupled between the gate terminals of the pair of PMOS transistors M.sub.11, M.sub.12 and the drain terminals of the pair of PMOS transistors M.sub.11, M.sub.12, and is further coupled with the input-stage circuit 122 of the aforementioned second amplifying circuit 120; accordingly, the resistor circuit uses the characteristic of a differential signal to assist the amplifying circuit 100 in achieving a large bandwidth through a smaller current. From a viewpoint based on a DC common-mode analysis, the loading circuit 420 and the transconductance and loading circuit 126 jointly function as a current mirror and achieve the efficacy of common-mode stabilization.
[0025] Referring to FIG. 4, the first amplifying circuit 110 further includes a bias circuit 430. The bias circuit 430 is coupled between the signal input circuit 410 and the low-voltage terminal GND, and configured to regulate the current I.sub.1 passing through the signal input circuit 410 according to a feedback voltage V.sub.fb, wherein the feedback voltage V.sub.fb can be generated by the circuit configuration of FIG. 3. In addition, in order to stabilize the amplifying circuit 100, a capacitor circuit 440 can optionally be set between the set of intermediate node(s) N.sub.1, N.sub.2 and the set of output node(s) N.sub.3, N.sub.4 for outputting the output signal V.sub.op, V.sub.on as shown in FIG. 4. Based on the circuit configuration of FIG. 4, the bandwidth F.sub.T and the gain Av of the amplifying circuit 100 can be represented by the following equation (3) and equation (4) respectively:
[00002]
In the equations (3)(4), WT denotes an angular frequency, Gm.sub.i,j denotes the transconductance contributed by the transistors M.sub.i, M.sub.j of FIG. 4 (e.g., Gm.sub.1,2 contributed by the transistors M.sub.1, M.sub.2), C.sub.C denotes the capacitance of the capacitor circuit 440, Ro.sub.p,q denotes the output impedance contributed by the transistors M.sub.p, M.sub.q of FIG. 4 (e.g., Ro.sub.9,10 contributed by the transistors M.sub.9, M.sub.10).
[0026] FIG. 5 shows another embodiment of the amplifying circuit of the present disclosure. In comparison with FIG. 1, the amplifying circuit 500 of FIG. 5 further includes a cascode transistor M.sub.13 coupled between the high-voltage terminal VDD and the first amplifying circuit 110. Since those having ordinary skill in the art can refer to the disclosure of the embodiments of FIGS. 14 to appreciate the detail and the modification of the embodiment of FIG. 5, repeated and redundant description is omitted here.
[0027] It is noted that people having ordinary skill in the art can selectively use some or all of the features of any embodiment in this specification or selectively use some or all of the features of multiple embodiments in this specification to implement the present invention as long as such implementation is practicable; in other words, the way to implement the present invention is flexible based on the present disclosure.
[0028] FIG. 6 shows the relation between the gain (Av) and the frequency with respect to the prior art (e.g., the two-stage operational amplifier mentioned in the description of related art of this specification), the amplifying circuit 100 of FIG. 2, and the amplifying circuit 100 of FIG. 4. As shown in FIG. 6, provided the 3 dB frequencies of the prior art, the amplifying circuit 100 of FIG. 2, and the amplifying circuit 100 of FIG. 4 are the same, the gain of the prior art is the smallest one, the gain of the amplifying circuit 100 of FIG. 2 is the medium one, and the gain of the amplifying circuit 100 of FIG. 4 is the largest one. In addition, as shown in FIG. 6, the cutoff frequency F.sub.T (or alternatively, the bandwidth) of the prior art is the smallest one, the cutoff frequency F.sub.T (or alternatively, the bandwidth) of the amplifying circuit 100 of FIG. 2 is the medium one, and the cutoff frequency F.sub.T (or alternatively, the bandwidth) of the amplifying circuit 100 of FIG. 4 is the largest one.
[0029] To sum up, the amplifying circuit of the present disclosure allows its loading circuit (i.e., the transconductance and loading circuit 126 composed of transistors M.sub.3, M.sub.4 in FIG. 1) to contribute to the transconductance of the amplifying circuit, and thereby increases the bandwidth of the amplifying circuit.
[0030] The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of the present invention are all consequently viewed as being embraced by the scope of the present invention.
