SEMICONDUCTOR DEVICE, BATTERY MONITORING SYSTEM, MEASUREMENT METHOD, AND EQUALIZATION METHOD

Abstract

An increase in the load of the booster circuit may be suppressed, and the voltage measurement accuracy may be improved. A battery monitoring IC of a battery monitoring system includes a first buffer amplifier and a second buffer amplifier driven by a power supply voltage or a boost voltage and having an input terminal connected to one terminal of any one of battery cells of an assembled battery. The control part selects the battery cell to be connected to the input terminals of the first and second buffer amplifiers. The control part switches a voltage for driving the first and second buffer amplifiers to the boost voltage when an upper battery cell is selected, and switches the voltage for driving the first and second buffer amplifiers to the power supply voltage when a battery cell other than the upper battery cell is selected.

Claims

1. A semiconductor device comprising: a buffer amplifier that is driven by a power supply voltage or a boost voltage higher than the power supply voltage, and has an input terminal connected to one terminal of any one of a plurality of battery cells of an assembled battery in which the plurality of battery cells are connected in series; a selection part that selects the battery cell to be connected to the input terminal of the buffer amplifier from the plurality of battery cells; and a switching part that switches a voltage for driving the buffer amplifier to the boost voltage when an upper battery cell is selected by the selection part, and switches the voltage for driving the buffer amplifier to the power supply voltage when a battery cell other than the upper battery cell is selected by the selection part.

2. The semiconductor device according to claim 1, wherein the buffer amplifier comprises: a first transistor driven by the power supply voltage; and a second transistor driven by the boost voltage, wherein drains of the first transistor and the second transistor are connected to an output terminal.

3. A battery monitoring system comprising: an assembled battery in which a plurality of battery cells are connected in series; the semiconductor device according to claim 1; and a diagnosis part that instructs the semiconductor device to measure a battery voltage of the battery cell.

4. The battery monitoring system according to claim 3, wherein the buffer amplifier comprises: a first transistor driven by the power supply voltage; and a second transistor driven by the boost voltage, wherein drains of the first transistor and the second transistor are connected to an output terminal.

5. A semiconductor device comprising: a selection part that selects at least one battery cell as a used cell from a plurality of battery cells of an assembled battery in which the plurality of battery cells are connected in series; and a switching element provided for each of the plurality of battery cells, wherein the switching element makes the battery cell driven by a power supply voltage or a boost voltage higher than the power supply voltage and not selected as the used cell into an unused cell, wherein the switching element provided for an upper battery cell is driven by the boost voltage, the switching element provided for a battery cell other than the upper battery cell is driven by the power supply voltage, and the selection part selects the upper battery cell as the used cell with priority.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 is a circuit diagram of an example of a battery monitoring IC according to the first embodiment.

[0018] FIG. 2 is a circuit diagram of a specific example of an internal circuit on the output terminal side of the first buffer amplifier and the second buffer amplifier.

[0019] FIG. 3 is a flowchart of an example of a flow of battery voltage diagnosis processing in the battery monitoring IC of this embodiment.

[0020] FIG. 4 is a circuit diagram of an example of a part of the circuit of the battery monitoring IC according to the second embodiment.

[0021] FIG. 5 is a flowchart of an example of a flow of battery voltage equalization processing in the battery monitoring IC of the second embodiment.

DESCRIPTION OF EMBODIMENTS

[0022] Hereinafter, a battery monitoring system and a semiconductor device for battery monitoring (hereinafter referred to as “battery monitoring IC”) of this embodiment will be described in detail with reference to the drawings. The battery monitoring system (battery monitoring IC) of this embodiment may be applied to a product using a battery LSI (assembled battery or the like), and products such as a personal computer, a car, a motorcycle, a power tool, and the like.

First Embodiment

[0023] The detailed configuration of the battery monitoring IC 20 of this embodiment will be described. FIG. 1 shows a circuit diagram of an example of an assembled battery 14, a battery monitoring IC 20, and a diagnosis part 18 of this embodiment.

[0024] The assembled battery 14 includes five battery cells Vc1 to Vc5 (collectively referred to as the “battery cells Vc”) connected in series. The battery cells Vc1 to Vc5 are connected in series with the battery cell Vc1 at the bottom and the battery cell Vc5 at the top. Specific examples of the battery cells Vc include a nickel-metal hydride battery, a lithium-ion battery, and the like. In FIG. 1, the case where n=5, which is the number of battery cells Vc of the assembled battery 14, is shown as a specific example, but the number n of the battery cells Vc included in the assembled battery 14 is not particularly limited.

[0025] Each of the battery cells Vc1 to Vc5 is connected to the battery monitoring IC 20. For example, the voltage V0 on the low potential side of the battery cell Vc1 is input to an input terminal 21.sub.0 of the battery monitoring IC 20. Further, the voltage V1 on the high potential side of the battery cell Vc1, which is synonymous with the voltage on the low potential side of the battery cell Vc2, is input to an input terminal 21.sub.1.

[0026] Further, the high potential side of the battery cell Vc5 is connected to a power supply terminal 23 of the battery monitoring IC 20.

[0027] The battery monitoring IC 20 includes a control part 22, a booster part 50, a cell selection SW 26, a comparison part 28, a first buffer amplifier 30, and a second buffer amplifier 32. The control part 22 is an example of a switching part.

[0028] The booster part 50 has a function of outputting a boosted voltage VCCUP that boosts the power supply voltage VCC input to one terminal from the power supply terminal 23 from the other terminal. The booster part 50 includes a booster circuit 24. The power supply voltage VCC corresponding to the maximum potential of the assembled battery 14 is input to one terminal of the booster part 50 via the power supply terminal 23. The booster circuit 24 boosts the power supply voltage VCC to the boost voltage VCCUP (VCC<VCCUP). The booster part 50 has a function of supplying the boost voltage VCCUP boosted by the booster circuit 24 to the first buffer amplifier 30 and the second buffer amplifier 32 from the other terminal. As a specific example, the booster part 50 of this embodiment outputs the boost voltage VCCUP (VCC+5=VCCUP) obtained by boosting by about 5V the power supply voltage VCC input to one terminal from the other terminal. Further, the power supply voltage VCC is also supplied to the first buffer amplifier 30 and the second buffer amplifier 32.

[0029] The cell selection SW 26 includes switching elements SW0, SW1_1, SW1_2, SW2_1, SW2_2, SW3_1, SW3_2, SW4_1, SW4_2, and SW5. Hereinafter, when these switching elements included in the cell selection SW 26 are collectively referred to, they are referred to as the “switching elements SW of the cell selection SW 26.”

[0030] The switching elements SW of the cell selection SW 26 are turned on or off by a control signal output from the control part 22. Each of the switching elements SW1_2, SW2_2, SW3_2, SW4_2, and SW5 connects the input terminals 21.sub.1 to 21.sub.5 and the non-inverting input terminal of the first buffer amplifier 30 when they are in the on state. Further, each of the switching elements SW0, SW1_1, SW2_1, SW3_1, and SW4_1 connects the input terminals 21.sub.0 to 21.sub.4 and the non-inverting input terminal of the second buffer amplifier 32 when they are in the on state.

[0031] The cell selection SW 26 is connected to the non-inverting input terminal of the first buffer amplifier 30. Further, the cell selection SW 26 is connected to the non-inverting input terminal of the second buffer amplifier 32.

[0032] The comparison part 28 includes resistance elements R1, R2, R3 and R4, an amplifier 40, input parts 60 and 62, and an output part 64.

[0033] The output terminal of the first buffer amplifier 30 is connected to the non-inverting input terminal of the amplifier 40, and the voltage output from the first buffer amplifier 30 is input via the resistance element R1. One terminal of the resistance element R2 is connected between the non-inverting input terminal of the amplifier 40 and the resistance element R1, and the other terminal is connected to GND (reference potential VSS). Further, the output terminal of the second buffer amplifier 32 is connected to the inverting input terminal of the amplifier 40, and the voltage output from the second buffer amplifier 32 is input via the resistance element R3. Further, the output terminal and the inverting input terminal of the amplifier 40 are connected via the resistance element R4.

[0034] From the comparison part 28, an output Vout corresponding to the difference between the voltage output from the output terminal of the first buffer amplifier 30 and the voltage output from the second buffer amplifier 32 is output to the diagnosis part 18 via the output terminal 41.

[0035] FIG. 2 shows an internal circuit on the output terminal side of the first buffer amplifier 30 and the second buffer amplifier 32. The internal circuits on the output terminal side of the first buffer amplifier 30 and the second buffer amplifier 32 have the same configuration. As shown in FIG. 2, drains of an NMOS transistor MO, a PMOS transistor M1 powered by the power supply voltage VCC, and a PMOS transistor M2 powered by the boost voltage VCCUP are connected to the output terminals 300 of the first buffer amplifier 30 and the second buffer amplifier 32. The PMOS transistor M1 is an example of a first transistor, and the PMOS transistor M2 is an example of a second transistor.

[0036] Only one of the PMOS transistors M1 and M2 operates. Which of the PMOS transistors M1 and M2 is operated is switched by the control signal output from the control part 22.

[0037] When the PMOS transistor M2 is operated, the PMOS transistor M1 is powered down. In addition, when the PMOS transistor M1 is operated, the PMOS transistor M2 is powered down.

[0038] Next, the operation of the battery monitoring IC 20 of this embodiment will be described.

[0039] First, the diagnosis of the battery voltage of the battery cells Vc1 to Vc5 by the battery monitoring IC 20 of this embodiment will be described. The timing of performing the diagnosis is not particularly limited, but may be performed periodically, for example, at every predetermined timing.

[0040] In the diagnosis part 18 of the battery monitoring system of this embodiment, the battery voltage is measured for each of the battery cells Vc1 to Vc5 as a measurement target.

[0041] FIG. 3 shows an example of a flow of battery voltage diagnosis processing in the diagnosis part 18. The battery voltage diagnosis processing is repeatedly performed for each of the battery cells Vc1 to Vc5 as a measurement target.

[0042] In step S100, the on/off of the switching elements SW of the cell selection SW 26 is controlled according to a battery cell as a measurement target among the battery cells Vc1 to Vc5 as measurement targets by the control signal output from the control part 22. For example, when the voltage value (V2−V1=Vc2) of the battery cell Vc2 is to be measured, the switching elements SW1_1 and SW2_2 of the cell selection SW 26 are turned on, and the other switching elements SW are turned off. Further, when the voltage value (V5−V4=Vc5) of the battery cell Vc5 is to be measured, the switching elements SW4_1 and SW5 of the cell selection SW 26 are turned on, and the other switching elements SW are turned off.

[0043] Next, in step S102, the drive voltage of the first buffer amplifier 30 is switched by the control signal output from the control part 22. For example, when the voltage value of an upper battery cell (for example, the battery cell Vc4 or the battery cell Vc5) is to be measured, the drive voltage of the first buffer amplifier 30 is switched to the boost voltage VCCUP by operating the PMOS transistor M2. When the voltage value of a battery cell (for example, the battery cell Vc1 to the battery cell Vc3) other than the upper battery cell is to be measured, the drive voltage of the first buffer amplifier 30 is switched to the power supply voltage VCC by operating the PMOS transistor M1.

[0044] Next, in step S104, the drive voltage of the second buffer amplifier 32 is switched by the control signal output from the control part 22. For example, when the voltage value of an upper battery cell (for example, the battery cell Vc4 or the battery cell Vc5) is to be measured, the drive voltage of the second buffer amplifier 32 is switched to the boost voltage VCCUP by operating the PMOS transistor M2. When the voltage value of a battery cell (for example, the battery cell Vc1 to the battery cell Vc3) other than the upper battery cell is to be measured, the drive voltage of the second buffer amplifier 32 is switched to the power supply voltage VCC by operating the PMOS transistor M2.

[0045] Next, in step S106, the output Vout is measured.

[0046] The voltage output from the first buffer amplifier 30 is input to the non-inverting input terminal of the amplifier 40 of the comparison part 28. In addition, the voltage output from the second buffer amplifier 32 is input to the inverting input terminal of the amplifier 40.

[0047] Therefore, a voltage corresponding to the difference between the voltage output from the first buffer amplifier 30 and the voltage output from the second buffer amplifier 32 is output from the amplifier 40 as the output Vout to the diagnosis part 18. For example, when the voltage value of the battery cell Vc5 is to be measured, a voltage corresponding to the difference between the voltage V5 output from the first buffer amplifier 30 and the voltage V4 output from the second buffer amplifier 32 is output as the output Vout to the diagnosis part 18. The diagnosis part 18 measures the output Vout.

[0048] Next, in step S108, it is determined whether the output Vout is within a predetermined range. For example, when the voltage of the battery cell as a measurement target is normal, the output Vout becomes a voltage predetermined for the battery cell as a measurement target. Therefore, when the output Vout is within a predetermined range from the voltage predetermined for the battery cell as the measurement target, with the allowable range obtained by experiments and the like taken into account, the diagnosis part 18 determines that the voltage of the battery cell as the measurement target is normal.

[0049] If the output Vout is within the predetermined range, a positive determination is made and the process proceeds to step S110. After diagnosing that the voltage of the battery cell as the measurement target is normal in step S110, the diagnosis part 18 ends the battery voltage diagnosis processing.

[0050] In addition, if the output Vout is not within the predetermined range (outside the range), a negative determination is made and the process proceeds to step S112. After diagnosing that the voltage of the battery cell as the measurement target is abnormal in step S112, the diagnosis part 18 ends the battery voltage diagnosis processing.

[0051] As described above, according to the battery monitoring IC of this embodiment, the battery cells connected to the input terminals of the first buffer amplifier and the second buffer amplifier are selected from multiple battery cells; when an upper battery cell is selected, the voltage for driving the first buffer amplifier and the second buffer amplifier is switched to the boost voltage; and when a battery cell other than the upper battery cell is selected, the voltage for driving the first buffer amplifier and the second buffer amplifier is switched to the power supply voltage. As a result, it is possible to suppress an increase in the load of the booster circuit and improve the voltage measurement accuracy.

[0052] In addition, by switching the voltage for driving the buffer amplifier in a time division manner, the usage time of the boost voltage is limited, whereby the average load current to the booster circuit is reduced, and the required characteristics for the booster circuit are minimized. As a result, the required capacity of the booster circuit may be reduced, and the area may be reduced.

[0053] Further, the power supply voltage and the boost voltage are properly used as the drive voltage according to the battery cell selected as the measurement target. For the buffer amplifier, the power supply voltage corresponding to the highest potential of the assembled battery is used as the drive voltage, and the accuracy of the output voltage deteriorates only when the output potential and the input potential are close to the power supply voltage, and when the selected cell is the upper battery cell. When the selected cell is a lower battery cell, there is no problem even if the power supply voltage is used as the drive voltage. Therefore, by switching the drive voltage according to the selected cell, it is possible to limit the cells that supply the boost voltage and reduce the average load current of the booster circuit when all the battery cells are continuously measured.

Second Embodiment

[0054] Next, the battery monitoring IC according to the second embodiment will be described. The parts having the same configuration as that of the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

[0055] The second embodiment is different from the first embodiment in that the used cells among the assembled battery may be selected and that the voltage equalization processing of the used cells is performed.

[0056] FIG. 4 shows a circuit diagram a part of an assembled battery 214 and the battery monitoring IC 20 of this embodiment.

[0057] An equalization NMOS 224 is provided between the cell selection SW 26 of the battery monitoring IC 20 and the assembled battery 214.

[0058] Though not shown, the battery monitoring IC 20 further includes a control part 22, a booster part 50, a comparison part 28, a first buffer amplifier 30, and a second buffer amplifier 32, as in the first embodiment. The control part 22 is an example of a selection part.

[0059] The assembled battery 214 includes ten battery cells Vc1 to Vc14 (collectively referred to as the “battery cells Vc”) connected in series. The battery cells Vc1 to Vc14 are connected in series with the battery cell Vc1 at the bottom and the battery cell Vc14 at the top. In FIG. 4, the case the number of battery cells Vc of the assembled battery 214 is 14 shown as a specific example, but the number of the battery cells Vc included in the assembled battery 214 is not particularly limited.

[0060] Each of the battery cells Vc1 to Vc14 is connected to the battery monitoring IC 20. For example, the voltage V0 on the low potential side of the battery cell Vc1 is input to an input terminal 21.sub.0 of the battery monitoring IC 20. Further, the voltage V1 on the high potential side of the battery cell Vc1, which is synonymous with the voltage on the low potential side of the battery cell Vc2, is input to an input terminal 21.sub.1.

[0061] The cell selection SW 226 includes switching elements SW0, SW1_1, SW1_2, SW2_1, SW2_2, . . . , SW13_1, SW13_2, and SW14. Hereinafter, when these switching elements included in the cell selection SW 226 are collectively referred to, they are referred to as the “switching elements SW of the cell selection SW 226.”

[0062] The switching elements SW of the cell selection SW 226 are turned on or off by a control signal output from the control part 22. Each of the switching elements SW1_1, SW2_1, . . . , SW13_1, and SW14 connects the input terminals 21.sub.1 to 21.sub.14 and the non-inverting input terminal of the first buffer amplifier 30 when they are in the on state. Further, each of the switching elements SW0, SW1_2, SW2_2, . . . , SW13_2 connects the input terminals 21.sub.0 to 21.sub.13 and the non-inverting input terminal of the second buffer amplifier 32 when they are in the on state.

[0063] The equalization NMOS 224 includes NMOS transistors N1 to N14 (collectively referred to as the “NMOS transistors N”) for making a battery cell driven by a power supply voltage or a boost voltage and not selected as a used cell into an unused cell. The NMOS transistors N1 to N14 are provided corresponding to the battery cells Vc1 to Vc14. The NMOS transistors N1 to N14 are examples of switching elements for making a battery cell an unused cell.

[0064] In this embodiment, for the upper battery cells (for example, the battery cells Vc13 to Vc14), the NMOS transistors N are driven by the boost voltage VCCUP; and for the battery cells (for example, the battery cells Vc1 to Vc12) other than the upper battery cells, the NMOS transistors N are driven by the power supply voltage VCC. Further, by driving the NMOS transistors N corresponding to the unused battery cells Vc, two terminals of the unused battery cells Vc are short-circuited. For example, when the battery cells Vcn to Vcm are unused cells, the NMOS transistors Nn to Nm are driven and short-circuited to connect the battery cells Vcn−1 and Vcm+1. Since the potentials have become the same outside the battery monitoring IC 20, it is not necessary to short-circuit between two terminals of the unused battery cells Vc by the corresponding NMOS transistors N.

[0065] The control part 22 selects the upper battery cell Vc as the used cell with priority.

[0066] Here, the reason why the upper battery cell is selected as the used cell with priority by the control part 22 will be described.

[0067] When the cell voltage of the battery cells Vc is equalized, in a case where two terminals of the uppermost battery cell Vc14 are short-circuited by the NMOS transistor N14, the source side becomes close to the power supply voltage, and the power supply voltage is insufficient as the gate voltage for turning on the NMOS transistor N14; therefore, the boost voltage is required. When short-circuiting between two terminals of the lower battery cell with the NMOS transistor N, the power supply voltage is sufficient; therefore, the boost voltage is required for the uppermost battery cell and the nearby battery cell.

[0068] Further, when the number of used cells is variable and the number of used cells is small, if a short circuit is made between two terminals as an unused cell from the upper side, the number of the driven NMOS transistors N increases according to the number of selections; therefore, the load current of the boost power supply becomes large.

[0069] For example, when the boost voltage is required when short-circuiting two terminals of the upper two battery cells and the number of used cells is variable between 7 and 14, if the upper two battery cells are regarded as unused cells and the two terminals are short-circuited, the load current of the boost power supply becomes large.

[0070] Therefore, in this embodiment, the control part 22 selects the upper battery cell as used cells with priority. For example, when the number of used cells is variable and the number of used cells is small, the two terminals of an intermediate battery cell (for example, battery cells Vcm to Vcn) using the power supply voltage VCC as the drive power source of the NMOS transistor are short-circuited.

[0071] Further, when the battery voltage of the used cell is to be equalized, the battery voltage of the used cell is adjusted to be within a predetermined range by turning on or off the corresponding NMOS transistor N.

[0072] Next, the operation of the battery monitoring IC 20 of this embodiment will be described.

[0073] First, the equalization of the battery voltage of the battery cells Vc1 to Vc14 by the battery monitoring IC 20 of this embodiment will be described. The timing of performing the equalization is not particularly limited, but may be performed periodically, for example, at every predetermined timing.

[0074] FIG. 5 shows an example of the flow of the battery voltage equalization process in the diagnosis part 18 of the battery monitoring system of this embodiment. Here, it is assumed that the number of used cells is set. Further, the same processing as in the first embodiment is designated by the same reference numerals, and detailed description thereof will be omitted.

[0075] In step S200, according to the control signal output from the control part 22, the upper battery cell Vc is prioritized and selected as the used cell according to the number of used cells, and the NMOS transistor N corresponding to the unused cell is turned on. At this time, when a battery cell Vc other than the upper battery cell Vc becomes the unused cell, the corresponding NMOS transistor N is driven by the power supply voltage VCC. When the upper battery cell Vc is also an unused cell, the boost voltage VCCUP drives the corresponding NMOS transistor N.

[0076] In step S100, the on/off of the switching elements SW of the cell selection SW 226 is controlled according to a battery cell Vc as a measurement target among the used cells by the control signal output from the control part 22.

[0077] Next, in step S102, the drive voltage of the first buffer amplifier 30 is switched by the control signal output from the control part 22.

[0078] Next, in step S104, the drive voltage of the second buffer amplifier 32 is switched by the control signal output from the control part 22.

[0079] Next, in step S106, the output Vout is measured.

[0080] Next, in step S108, it is determined whether the output Vout is within a predetermined range. If the output Vout is within the predetermined range, a positive determination is made and the process proceeds to step S204. In addition, if the output Vout is not within the predetermined range (outside the range), a negative determination is made and the process proceeds to step S202.

[0081] In step S202, the diagnosis part 18 outputs a control signal from the control part 22 according to the voltage of the battery cell Vc as the measurement target, and adjusts the battery voltage of the battery cell Vc as the measurement target to be within a predetermined range by turning on or off the NMOS transistor N corresponding to the battery cell Vc as the measurement target.

[0082] In step S204, the diagnosis part 18 determines whether the processes of steps S100 to S202 have been performed on all the used cells as the measurement targets. If there is a used cell on which the processes of steps S100 to S202 have not been performed, the process returns to step S100 with the used cell as the measurement target.

[0083] In addition, when the processes of steps S100 to S202 have been performed on all the used cells as the measurement targets, the battery voltage equalization processing ends.

[0084] As described above, according to the battery monitoring IC of this embodiment, the upper battery cell is selected as the used cell from the assembled battery with priority, and the switching element provided for the upper battery cell to make it an unused cell is driven by a boost voltage, and the switching element provided for a battery cell other than the upper battery cell to make it an unused cell is driven by the power supply voltage. As a result, it is possible to suppress an increase in the load of the booster circuit and improve the voltage measurement accuracy.

[0085] Further, in the battery voltage equalization processing, a normal cell voltage measurement operation and a normal cell equalization operation are performed. Here, among the NMOS transistors for making the number of cells variable and making unused cells and for battery voltage equalization, only the NMOS transistor for the upper battery cell is driven by the boost voltage, and the upper battery cell is selected as the used cell with priority. In this configuration, when the number of used cells is set to be small, by not using the intermediate battery cell corresponding to the NMOS transistor driven by the power supply voltage, among the battery cells near the uppermost cell corresponding to the NMOS transistor driven by the boost voltage, the unused battery cells are limited to the minimum necessary cells. In this way, the usage time of the boost voltage is limited, whereby the average load current to the booster circuit is reduced, and the required characteristics for the booster circuit are minimized.