Audio amplifier using multi-level pulse width modulation

Abstract

The present invention relates in one aspect to a class D audio amplifier with improved output driver topology supporting multi-level output signals such as 3-level, 4-level or 5-level pulse width or pulse density modulated output signals for application to a loudspeaker load. The present class D audio amplifiers are particularly well-suited for high-volume consumer audio applications and solutions.

Claims

1. A class D audio amplifier comprising: a first output driver and a second output driver comprising first and second output nodes configured to be connected to respective inputs of a loudspeaker load to supply a load signal thereto, said first output driver comprising first one or more semiconductor switches coupled between a first supply voltage and the first output node, second one or more semiconductor switches coupled between the first output node and a second supply voltage, third one or more semiconductor switches coupled between the first output node and a third supply voltage; said second output driver comprising fourth one or more semiconductor switches coupled between the first supply voltage (VS) and the second output node, fifth one or more semiconductor switches coupled between the second output node and the second supply voltage, sixth one or more semiconductor switches coupled between the second output node and the third supply voltage; wherein each of the first, second, third, fourth, fifth, and sixth one or more semiconductor switches comprises a switch control terminal adapted to control a state of the first, second, third, fourth, fifth, and sixth one or more semiconductor switches to selectively place each of the first, second, third, fourth, fifth, and sixth one or more semiconductor switches in its on-state or off-state; a controller adapted to receive an audio input signal and derive a first set of modulated control signals therefrom and apply the first set of modulated control signals to respective switch control terminals of the first driver, the controller being further adapted to derive a second set of modulated control signals, having a predetermined phase relationship to the first set of modulated control signals, and apply the second set of modulated control signals to respective switch control terminals of the second driver, wherein the controller is configured to: in a first operation mode, set a first predetermined phase relationship between the first and second sets of modulated control signals to generate a first multi-level load signal across the loudspeaker load, in a second operation mode, set a second predetermined phase relationship between the first and second sets of modulated control signals to generate a second multi-level load signal across the loudspeaker load.

2. The class D audio amplifier according to claim 1, wherein the controller is configured to: in the first operation mode, providing each control signal of the second set of modulated control signals with opposite phase relative to a corresponding control signal of the first set of modulated control signals to generate a three-level load signal, in the second operation mode, providing each control signal of the second set of modulated control signals with opposite phase and an additional +/90 degrees phase shift relative to a corresponding control signal of the first set of modulated control signals to generate a five-level load signal.

3. The class D audio amplifier according to claim 1, wherein the controller comprises an audio signal level detector, the controller being adapted to switch between first operation mode and the second operation mode in dependence of a detected level of the audio input signal.

4. The class D audio amplifier according to claim 3, wherein the controller is further adapted to: comparing the detected level of the audio signal with a predetermined level threshold, selecting the first operation mode when the detected audio signal level exceeds the predetermined level threshold, selecting the second operation mode when the detected audio signal level is smaller than the predetermined level threshold.

5. The class D audio amplifier according to claim 1, wherein the first output driver comprises: the first one or more semiconductor switches including a first and a second semiconductor switch coupled in series between the first supply voltage and the first output node, the second one or more semiconductor switches including a third and a fourth semiconductor switch coupled in series between the second supply voltage and the first output node; and the second output driver comprises: the fourth one or more semiconductor switches including a fifth and a sixth semiconductor switch coupled in series between the first supply voltage and the second output node, the fifth one or more semiconductor switches including a seventh and an eight semiconductor switch coupled in series between the second supply voltage and the second output node; a third supply voltage source configured to generate the third supply voltage and comprising: a first DC voltage source configured to set a first predetermined DC voltage difference between a first node, located between the first and second semiconductor switches, and a second node, located between the third and fourth semiconductor switches, a second DC voltage source configured to set a second predetermined DC voltage difference between a third node, situated between the fifth and sixth semiconductor switches, and a fourth node, situated between the seventh and eight semiconductor switches.

6. The class D audio amplifier according to claim 5, wherein the first set of and the second set of modulated control signals are configured to, in a first state, connecting a first terminal of the first DC voltage source to the first output node through the first and third semiconductor switches; and in a second state connecting a second terminal of the first DC voltage source to the first output node through the fourth and second semiconductor switches.

7. The class D audio amplifier according to claim 5, wherein at least one of the first DC voltage source or the second DC voltage source comprises a charged capacitor; each capacitor having a capacitance between 100 nF and 10 F.

8. The class D audio amplifier according to claim 1, wherein the first output driver comprises: a first and a second semiconductor switch coupled in series between the first supply voltage and the first output node, a third and a fourth semiconductor switch coupled in series between the second supply voltage and the first output node; and the second output driver comprises: a fifth and a sixth semiconductor switch coupled in series between the first supply voltage and the second output node, a seventh and an eight semiconductor switch coupled in series between the second supply voltage and the second output node; a third supply voltage source configured to generate the third supply voltage and comprising: a pair of supply capacitors coupled in series between the first supply voltage and the second supply voltage to provide a mid-point voltage, a first diode coupled between the mid-point voltage and a node between the first and second semiconductor switches, a second diode coupled between the mid-point voltage and a node between the third and fourth semiconductor switches, a third diode coupled between the mid-point voltage and a node between the fifth and sixth semiconductor switches, a fourth diode coupled between the mid-point voltage and a node between the seventh and eight semiconductor switches.

9. The class D audio amplifier according to claim 1, comprising: a third supply voltage source configured to generate the third supply voltage and comprising: a pair of supply capacitors coupled in series between the first supply voltage and the second supply voltage to provide a mid-point voltage; wherein the first output driver comprises: the first one or more semiconductor switches including a first semiconductor switch coupled in series between the first supply voltage and the first output node, the second one or more semiconductor switches including a second semiconductor switch coupled in series between the second supply voltage and the first output node, a third second semiconductor switch coupled between the mid-point voltage and the first output node; wherein the second output driver comprises: the fourth one or more semiconductor switches including a fourth semiconductor switch coupled in series between the first supply voltage and the second output node, the fifth one or more semiconductor switches including a fifth semiconductor switch coupled in series between the second supply voltage and the second output node, a sixth semiconductor switch coupled between the mid-point voltage and the first output node.

10. The class D audio amplifier according to claim 1, wherein: each modulated control signal of the first and second sets of modulated control signals comprises a pulse width modulated control signal, or each modulated control signal of the first and second sets of modulated control signals comprises a pulse density modulated control signal.

11. The class D audio amplifier according to claim 1, wherein each of the first one or more semiconductor switches comprises a transistor switch selected from a group of {Field Effect Transistors (FETs), Bipolar Transistors (BJTs), Insulated Gate Bipolar Transistors (IGBTs)}.

12. The class D audio amplifier according to claim 1, wherein: the first predetermined DC voltage difference is set to substantially one-half of a DC voltage difference between the first and second DC supply voltages, or the third supply voltage is set to substantially one-half of a voltage difference between the first and second supply voltages.

13. The class D audio amplifier according to claim 1, wherein a switching frequency or modulation frequency of each of the first set of modulated control signals lies between 250 kHz and 5 MHz.

14. The driver circuit according to claim 1, wherein the controller comprises a programmable Digital Signal Processor.

15. The sound reproducing assembly, comprising: the class D audio amplifier according to claim 1; and a loudspeaker load operatively coupled to the first output node of the first driver and one of the first and second DC supply voltages, or a loudspeaker load operatively coupled in-between the first and second output nodes of the first and second output drivers, respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) A preferred embodiment of the invention will be described in more detail in connection with the appended drawings, in which:

(2) FIG. 1a) illustrates an H-bridge driver coupled to a loudspeaker load and pulse width modulated output signal waveforms (FIG. 1b)) of the H-bridge driver according to a first type of prior art class D amplifier utilizing AD modulation,

(3) FIG. 2a) illustrates an H-bridge driver for class D audio amplifiers coupled to a loudspeaker load and pulse width modulated output signal waveforms (FIG. 2b) of the H-bridge driver according to a second type of prior art class D amplifier utilizing BD modulation,

(4) FIG. 3 illustrates load inductor ripple current waveforms and load capacitor ripple voltage waveforms for the prior art Class D amplifiers depicted on FIGS. 1a) and 2a),

(5) FIGS. 4a) and 4b) are schematic diagrams of a single-ended output driver and an H-bridge output driver, respectively, for class D audio amplifiers coupled to loudspeaker loads in accordance with a first embodiment of the invention,

(6) FIG. 5 illustrates three-level and five-level pulse width modulated output signal waveforms of the H-bridge output driver depicted on FIG. 4b),

(7) FIG. 6 is schematic diagram of a CMOS based single-ended multi-level output driver for class D audio amplifiers coupled to a loudspeaker load in accordance with a second embodiment of the invention,

(8) FIG. 7 is a schematic diagram of a class D audio amplifier with an H-bridge output driver coupled to a loudspeaker load in accordance with a third embodiment of the invention,

(9) FIG. 8 is a schematic diagram of a class D audio amplifier with an H-bridge output driver coupled to a loudspeaker load in accordance with a fourth embodiment of the invention,

(10) FIGS. 9a) and 9b) illustrate the generation of pulse width modulated control signals for each of the semiconductor switches of the H-bridge output driver depicted on FIG. 4b) in a three-level operational mode and a five-level operational mode,

(11) FIGS. 10a) and 10b) show load capacitor ripple voltage and load inductor ripple current, respectively, versus modulation duty cycle for the prior art H-bridge driver illustrated on FIG. 1a) in comparison with the H-bridge driver depicted on FIG. 4b) operating in three-level output mode,

(12) FIG. 11 illustrates schematically a class D audio amplifier comprising the H-bridge driver depicted on FIG. 4b) and an accompanying controller,

(13) FIG. 12 illustrates a mode-switching scheme for operating the present class D amplifier embodiments in different operation modes dependent on a detected level of the audio input signal in accordance with a fifth embodiment of the invention; and

(14) FIG. 13 illustrates experimentally recorded power loss data for a prior art H-bridge driver and the H-bridge output driver in accordance with the second embodiment of the invention depicted on FIG. 4b).

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(15) FIG. 1a) illustrates schematically an H-bridge output driver 100 coupled to a loudspeaker load 140. Pulse width modulated output signal waveforms 120, 121 shown in FIG. 1b) are provided at respective output nodes VA, VB of the H-bridge output driver. The illustrated prior art class-D amplifier utilizes so-called AD modulation where the loudspeaker load is alternatingly connected between a positive DC supply voltage V.sub.S and a negative DC supply voltage, such as GND, and vice versa in accordance with respective switch control signals applied to control terminals (not shown) of semiconductor switches SW1, SW2, SW3 and SW4. The alternating switching of the loudspeaker load between V.sub.S and GND as illustrated by output signal waveform 122 is obtained by in a first phase setting SW1 and SW4 to respective ON or conductive states and SW2 and SW3 to respective OFF states or off-states. In a second phase, SW1 and SW4 are set to respective OFF or non-conducting states and SW2 and SW3 to respective on-states. The audio input signal waveform that corresponds to the pulse width modulated output signal waveforms is illustrated by waveform 119.

(16) Load inductors 138, 137 are coupled between respective output nodes VA, VB of the H-bridge output driver 100 and each side of the loudspeaker load 140. Likewise, load capacitors 136, 135 are coupled from each terminal or side of the loudspeaker load to GND. The combined operation of the load capacitors and load inductors is to provide lowpass filtering of the pulse width modulated output signal waveforms 120, 121 at output nodes VA and VB to suppress carrier or switching frequency components in the loudspeaker drive or load signal.

(17) FIG. 2a) illustrates another prior art H-bridge output driver with similar topology to the H-bridge driver illustrated in FIG. 1a) and coupled to the loudspeaker load 240. However, the present prior art class D amplifier utilizes so-called BD modulation. In class BD modulation, zero states exist which involve setting the output nodes VA and VB to the same state or voltage simultaneously, i.e. V.sub.S or GND, during certain time intervals. In the zero state both ends or terminals of the loudspeaker load 240 are simultaneously coupled or connected to either V.sub.S or to GND so as to set the driving voltage across the loudspeaker load 240 to zero. Consequently, when the level of the audio input signal is close to zero, switching of the pulse width modulated output waveforms 120, 121 at respective output nodes V.sub.A, V.sub.B is discarded. This is illustrated in the pulse width modulated output waveform 222 shown in FIG. 2b) at time instance marked by reference numeral 224 where the amplitude of the audio input signal 219 crosses zero. However, despite the presence of states with zero-differential voltage across the loudspeaker load it is important to notice that there only exists two different states or levels at each of the output nodes V.sub.A, V.sub.B of the output driver, i.e. V.sub.S or GND.

(18) FIG. 3 illustrates inter alia load inductor ripple current waveforms and load capacitor ripple voltage waveform for the prior art Class D amplifiers depicted on FIGS. 1a) and 2a). The waveforms illustrated in FIG. 3 correspond to a situation with zero level or amplitude of the audio input signal such that modulation of the pulse width modulated output waveforms at the first and second output nodes V.sub.A, V.sub.B is zero. The waveforms on the left hand side of the drawing correspond to AD modulation as outlined above in connection with FIG. 1b) while the right hand side waveforms depict the same voltage or current variables for class BD modulation as outlined above in connection with FIG. 2b). The respective load inductor ripple current waveforms on waveform plots 303 reflect the integrating function of the load inductors 237, 238 and 137, 138 on the rectangular carrier waveform. The approximate sine-shaped load capacitor ripple voltage waveforms V.sub.P and V.sub.N on waveform plots 305 measured at the respective input terminals of the loudspeaker load reflect the lowpass filtering effect of the load capacitors 235, 236 and 135, 136 on the rectangular carrier waveforms. It is interesting to notice, that while the load capacitor ripple voltage waveforms V.sub.P and V.sub.N are of substantially identical amplitudes for class AD and class BD modulation, a differential ripple voltage, i.e. V.sub.P minus V.sub.N, across the loudspeaker load as illustrated by waveforms 307 differs. For class AD modulation, the differential ripple voltage is twice the individual capacitor ripple voltages while the differential ripple voltage is about zero for class BD modulation. The lower level of ripple voltage for class BD modulation indicates a lower power loss in connection with the application of the pulse width modulated carrier waveforms to the loudspeaker load. However, despite the approximately zero differential ripple voltage across the loudspeaker load for class BD modulation, there still exist a significant common mode differential voltage as illustrated on common mode waveform plots 309 which leads to a power loss for this type of modulation. This is caused by load currents which are cycled back and forth through the load inductors causing power loss in a practical class D amplifier because real inductors possess inherent resistive and hysteresis losses.

(19) FIGS. 4a) and 4b) illustrate a single-ended output driver and an H-bridge output driver, respectively, coupled to a loudspeaker load 440 in accordance with first preferred embodiments of the invention. The operation of the H-bridge output driver 401 where the loudspeaker load is operatively interconnected between a pair of output nodes V.sub.A and V.sub.B is explained in detail below while pulse width modulated load waveforms or signals at the first and second output nodes V.sub.A and V.sub.B are illustrated on FIG. 5 according to two different operating modes of a controller (not shown) adapted to generate the pulse width modulated switch control signals. In the first operation mode, a load signal with 3-level modulation is generated while a load signal with 5-level modulation is generated in the second operating mode.

(20) In FIG. 4b), the H-bridge output driver 401 is operatively coupled to the loudspeaker load 440. The H-bridge output driver 401 comprises first and second substantially identical output drivers 425, 426, respectively. Each of the output drivers comprises four cascaded CMOS transistor switches, for example NMOS transistor, coupled between an upper DC supply voltage or rail V.sub.S and a lower DC supply voltage or rail in form of ground or GND rail. Furthermore, each output driver 425, 426 comprises a charged so-called flying capacitor C.sub.fly1, C.sub.fly2 418, 419 that enable the generation of a third output level or mid-point voltage situated approximately midway between V.sub.S and GND at the output nodes V.sub.A and V.sub.B as explained in further detail below.

(21) In the present embodiment, the upper leg A of a first output driver 425 of the H-bridge driver 401 comprises a pair of series or cascade coupled semiconductor switches such as CMOS transistors, preferably NMOS transistors. The series coupled semiconductor switches SW1 and SW2 are coupled to V.sub.S at a first end and the output node V.sub.A at an opposite end. The lower leg B of the first output driver 425 comprises another pair of series or cascade coupled CMOS semiconductor switches SW3 and SW4 coupled from the output node V.sub.A to GND. The upper leg C of the second output driver 426 of the H-bridge driver 401 comprises a pair of series or cascade coupled CMOS semiconductor switches SW5 and SW6 that preferably are identical in electrical characteristics to respective ones of the CMOS semiconductor switches SW1 and SW2 of leg A. The lower leg D comprises yet another pair of cascaded CMOS semiconductor switches SW7 and SW8 that preferably are identical in electrical characteristics to respective ones of the CMOS semiconductor switches SW3 and SW4 of leg B. The above-mentioned CMOS semiconductor switches are schematically illustrated on FIG. 4a) and FIG. 4b) as ideal switch elements. Each of the semiconductor switches may be composed of a single semiconductor switch as schematically illustrated or may in other embodiments comprise a plurality of parallelly coupled individual semiconductor switches with common control terminals.

(22) During operation of the H-bridge driver 401, the controller is configured to apply the first, second, third and fourth pulse width modulated control signals of appropriate amplitude to first, second, third and fourth gate terminals (not shown) of the CMOS semiconductor switches SW1, SW2, SW3 and SW4, respectively, so as to controlling respective states of these CMOS semiconductor switches. Thereby, the state of each of the CMOS semiconductor switches toggles or switches between an on-state or ON and an off-state or OFF in accordance with transitions of the pulse width modulated control signals. The same applies for CMOS semiconductor switches SW5, SW6, SW7 and SW8 of the second output driver 426 which are supplied with the 5.sup.th 6.sup.th, 7.sup.th and 8.sup.th pulse width modulated control signals, respectively, at their gate terminals.

(23) The on-resistance of each of the CMOS semiconductor switches SW1, SW2 in the on-state or conducting state or closed state may vary significantly according to requirements of a particular application, in particular an audio frequency impedance of the loudspeaker load 440. The on-resistance of semiconductor switches varies depending on switch dimensions, drive voltage at the control terminal, i.e. gate terminal in the present embodiment, and semiconductor process outcome. The semiconductor switches SW1, SW2 are preferably configured or designed to possess an on-resistance that is much smaller than an ohmic resistance of the loudspeaker load 440 such that power delivered through the output nodes V.sub.A, V.sub.B predominantly is dissipated in the loudspeaker load 440 and to a smaller extent in the individual on-resistances of the semiconductor switches as switch power loss.

(24) The on-resistance of each of the CMOS semiconductor switches SW1, SW2, SW3, SW4, SW5, SW6, SW7 and SW8 is preferably set to a value between 0.05 and 5 ohm such as between 0.1 and 0.5 ohm in the present embodiment of the invention.

(25) A loudspeaker load 440 which may comprise a moving coil, moving armature or other type of audio speaker is operatively coupled in-between the first and second output nodes V.sub.A and V.sub.B of the H-bridge driver 400. The loudspeaker load 440 typically includes a resistive component in series with significant inductive component. A first load inductor 438 and a first load capacitor 422 is coupled between the first output node V.sub.A and a first terminal of the loudspeaker load 440 so as to form a lowpass filter. The first load inductor 438 and a first load capacitor 422 may be provided as external components to an integrated circuit implementation of the first and second output drivers 425, 426 of the H-bridge driver. The lowpass filtering suppresses modulation or switching frequency components of the output waveform present at the output nodes V.sub.A, V.sub.B in the load signal applied across the loudspeaker load 440. In the present embodiment, the first load capacitor 422 may have a capacitance between 100 and 500 nF such as about 220 nF. The first load inductor 414 may have an inductance between 1 H and 5 H such as about 2.20 H. The respective values of a second load inductor 437 and a second load capacitor 423 coupled to the second output node V.sub.B are preferably identical.

(26) The first flying capacitor 418 has one terminal coupled to a first connection node 418a between the pair of cascade coupled CMOS semiconductor switches SW1, SW2 of the upper leg A of the first output driver 425 to provide electrical connection between SW1, SW2 and the flying capacitor terminal. An opposite terminal of the first flying capacitor 418 is coupled to a second connection node 418b situated between the pair of cascade coupled CMOS semiconductor switches SW3, SW4 of the lower leg B of the first output driver 425. The first flying capacitor 418 is precharged to a predetermined DC voltage which equals about one-half of a DC voltage difference between V.sub.S and GND, i.e. simply one-half of V.sub.S because of the GND connection of the lower DC supply voltage, before operation of the present H-bridge driver 400 is commenced. The first flying capacitor 418 therefore acts as a DC voltage source which maintains or sets a DC voltage difference of one-half V.sub.S between the first and second connection nodes 418a, 418b.

(27) The controller (illustrated as item 1103 of FIG. 11) is configured to provide the first and fourth pulse width modulated control signals in opposite phase and non-overlapping such that CMOS semiconductor switches SW1 and SW2 are never simultaneously in on-states with zero modulation of the pulse width modulated control signals, i.e. the audio signal input is zero. Likewise, the second and third pulse width modulated control signals preferably have opposite phase and are non-overlapping at zero modulation of the pulse width modulated control signals such that CMOS semiconductor switches SW2 and SW3 are never in on-states or ON simultaneously at zero modulation. This means that the first flying capacitor 418 in a first state is coupled between V.sub.S and output node V.sub.A when SW1 and SW3 are simultaneously in on-states or ON while SW4 and SW2 are both OFF or in off-states leading to an output level of V.sub.S minus one-half of V.sub.S, i.e. an output level of one-half of V.sub.S. In a second state of the first output driver 425 the first flying capacitor 418 is coupled between GND and the output node V.sub.A through SW2 and SW4 when these are simultaneously ON while SW1 and SW3 are both OFF leading to an output level of GND plus one-half of the DC supply voltage, i.e. one-half V.sub.S as was the case in the first state. Accordingly, the first flying capacitor is operative to generate a third supply voltage level at the output node V.sub.A equaling one-half of the DC supply voltage V.sub.S in the present embodiment. This third supply voltage level is generated in both the first and the second output driver state as outlined above because of the chosen adaptation of the DC voltage of the first flying capacitor 418 to one-half V.sub.S. Accordingly, the output levels at the output node V.sub.A of the first driver 425 therefore toggles between three discrete levels: V.sub.S, one-half V.sub.S and GND. Naturally, the GND voltage may in other embodiments be a negative or positive DC supply voltage for example a negative DC voltage substantially equal in magnitude to the first DC supply voltage.

(28) The illustrated H-bridge output driver 401 comprises a second output driver 426 coupled to another side or terminal of the loudspeaker load 403 through the second output node V.sub.B. The circuit topology and electrical characteristics of the individual components such as CMOS semiconductor switches SW5, SW6, SW7, SW8 and the flying capacitor 419 of the second output driver 426 are preferably substantially identical to those of the corresponding components of the first output driver 425. Likewise, the external second load inductor 437 and the external second load capacitor 423 are preferably identical to the corresponding external components associated with the first output driver 425.

(29) In a first embodiment of the invention, the various pulse width modulated control signals are configured such that the first and fifth fourth pulse width modulated control signals are in opposite phase at zero modulation. The same applies for the second and 6.sup.th pulse width modulated control signals, the third and 7.sup.th pulse width modulated control signals and the fourth and 8.sup.th pulse width modulated control signals. This configuration of the pulse width modulated control signals ensures, in combination with the respective settings of the predetermined DC voltages of the flying capacitors C.sub.fly1, C.sub.fly2 (418, 419) to about one-half of the first DC supply voltage V.sub.S, that a 3-level pulse width modulated output signal is generated between the first and second output nodes V.sub.A and V.sub.B and therefore applied as a load signal to the loudspeaker load 440. This 3-level pulse width modulated output signal is illustrated on FIG. 5 as waveform 507. As illustrated the present 3-level pulse width modulated output signal, which is applied to the loudspeaker 440 as a corresponding load signal, shares an advantageous property with the previously outlined prior art class BD modulation in that state switching rates at the first and second output nodes V.sub.A and V.sub.B are reduced when the audio signal input is close to zero.

(30) In a second embodiment of the invention, the various pulse width modulated control signals are configured such that the first and fifth fourth pulse width modulated control signals are inverted and additionally phase shifted with +/90 degrees relative to each other. The same applies for a corresponding phase relationship between the second and 6.sup.th pulse width modulated control signals, the third and 7.sup.th pulse width modulated control signals and the fourth and 8.sup.th pulse width modulated control signals. This adaptation of the pulse width modulated control signals ensures, in combination with the setting of both of the predetermined DC voltages of the flying capacitors C.sub.fly1, C.sub.fly2 (418, 419) to about one-half of the first DC supply voltage V.sub.S, that a 5-level pulse width modulated output signal is generated between the first and second output nodes V.sub.A and V.sub.B and therefore applied as a load signal to the loudspeaker load 440. This 5-level pulse width modulated output signal is illustrated on FIG. 5 as output waveform 513 depicting 2 discrete levels of pulse width modulated waveforms above zero, a zero level and 2 discrete levels of pulse width modulated waveforms below zero. As illustrated the present 5-level pulse width modulated output signal shares an advantageous property with the previously outlined class BD modulation and 3-level modulation in that state switching rates at the first and second output nodes V.sub.A and V.sub.B are reduced when the audio signal input is close to zero.

(31) FIG. 6 illustrates a CMOS based single-ended multi-level output driver 601 coupled to a loudspeaker load 640 through a lowpass filter comprising load inductor 637 and load capacitor 635 in accordance with a third embodiment of the invention. The single-ended multi-level output driver 601 comprises, in addition to semiconductor switches SW1, SW2, SW3, SW4 of the single-ended output driver depicted on FIG. 4a), a 5.sup.th CMOS semiconductor switch SW5 and a sixth semiconductor switch SW6 to bring the total number of series coupled or connected CMOS semiconductor switches up to six. The 5.sup.th CMOS semiconductor switch SW5 is coupled in series with the upper or first DC supply voltage V.sub.S and in series to the first and second semiconductor switches SW1 and SW2 which are coupled to an output node V.sub.A. The 6.sup.th CMOS semiconductor switch SW6 is coupled in series between GND and series coupled third and fourth semiconductor switches SW3 and SW4 which are coupled to the output node V.sub.A. Consequently, both an upper leg A and a lower leg B of the present single-ended multi-level output driver 601 comprises three cascaded CMOS semiconductor switches instead of two switches as used in the output driver of FIG. 4a). Furthermore, the CMOS single-ended multi-level output driver 601 comprises a second flying capacitor C.sub.fly2 619 in addition to a first flying capacitor C.sub.fly1 capacitor 618. The latter corresponds to the first flying capacitor 418 of the single-ended output driver depicted on FIG. 4b). The second flying capacitor 619 has one terminal coupled to a first connection node 630a situated between the pair of cascade coupled CMOS semiconductor switches SW5 and SW1 of the upper leg A. An opposite terminal of the second flying capacitor 619 is electrically coupled to a second connection node 630b situated between the pair of cascade coupled CMOS semiconductor switches SW4 and SW6 of the lower leg B. The second flying capacitor 619 is preferably pre-charged to a first predetermined DC voltage which may equal a DC voltage of between 60% and 75% of the DC supply voltage V.sub.S such as approximately two-thirds of the DC supply voltage. The first flying capacitor C.sub.fly1 618 is electrically coupled in-between third and fourth connection or coupling nodes situated between SW1 and SW2 and SW3 and SW4, respectively. The first flying capacitor 619 is preferably pre-charged to a second predetermined DC voltage which is different from the first predetermined DC voltage. The second predetermined DC voltage may lie between 25% and 40% of the DC supply voltage V.sub.S such as about one-third of the DC supply voltage V.sub.S.

(32) Consequently, the CMOS single-ended multi-level output driver 601 is capable of providing additional output levels at the output node V.sub.A compared to the 3-level or 4-level single-ended output driver topology depicted on FIG. 4a) depending on the chosen settings of the first and second predetermined DC voltages of the flying capacitors 618, 619.

(33) The CMOS semiconductor switches SW1, SW2, SW3, SW4, SW5 and SW6 comprises respective switch control terminals or inputs in form of gate terminals 650a-f that are driven by appropriate pulse width modulated control signals supplied by an appropriately configured controller (not shown) of a class D audio amplifier.

(34) The skilled person will understand that the single-ended multi-level output driver 601 could be modified to provide an H-bridge output driver topology based on a combination of two essentially identical output drivers 601 in a layout or circuit arrangement similar to that of the H-bridge output driver 401 depicted on FIG. 4b). This latter output driver topology is capable of providing a seven-level load signal across the loudspeaker load by generation of a first set of appropriately modulated control signals for the CMOS semiconductor switches SW1, SW2, SW3, SW4, SW5 and SW6 and generation of a second set of appropriately modulated control signals for corresponding CMOS semiconductor switches of the second output driver.

(35) Finally, the skilled person will understand that the CMOS single-ended multi-level output driver 601 could be further expanded by coupling one or more pair(s) of additional CMOS semiconductor switches in series with SW5 and SW6 and add additional flying capacitors between new interconnection nodes to create additional output levels at the output node V.sub.A.

(36) FIG. 7 is a schematic diagram of a class D audio amplifier with an H-bridge output driver comprising first and second output drivers 725, 726, respectively, coupled to a loudspeaker load 740 in accordance with a third embodiment of the invention. The topology is of each of the output drivers 725, 726 is often referred to as neutral-point clamped three-level half-bridge. A first load inductor 738 and a first load capacitor 722 is coupled between a first output node V.sub.A of the first driver 725 and a first terminal of the loudspeaker load 740 to form a lowpass filter. Another lowpass filter is formed by a second load inductor 737 and a second load capacitor 723 which are coupled between a second output node V.sub.B of the second driver 726 and a second terminal of the loudspeaker load 740. The purpose and characteristics of each of these lowpass filters are the same as those previously discussed in connection with the first embodiment of output driver 401.

(37) The first output driver 725 comprises a first semiconductor switch SW2 coupled in series between a first supply voltage V.sub.S and a first output node V.sub.A of the first output driver. A second semiconductor switch SW3 is coupled in series between GND, i.e. a second supply voltage, and V.sub.A. A third and fourth semiconductor switch SW1 and SW4, respectively, are coupled in series between a mid-point voltage V.sub.S and V.sub.A. The mid-point voltage V.sub.S is generated by third supply voltage source as a third supply voltage for the first and, optionally second, output driver 725, 726. The third supply voltage source comprises a pair of supply capacitors, C1 and C2, coupled in series between the first supply voltage V.sub.S and GND voltage to provide the mid-point voltage. The supply capacitors, C1 and C2 preferably have substantially equal capacitance such that the mid-point voltage is set to approximately one-half of the first supply voltage V.sub.S. Each of the semiconductor switches, SW1, SW2, SW3 and SW4 comprises a gate terminal Gc1, Gc2, Gc3 and Gc4 to control the state of the semiconductor switch in question. The semiconductor switches, SW1, SW2, SW3 and SW4 may comprise respective CMOS transistors such as NMOS transistors. The second output driver 726 comprises the second output node V.sub.B which is coupled to an opposite side or terminal of the loudspeaker load 740. The second output driver 726 comprises semiconductor switches SW5, SW6, SW7 and SW8 coupled in a circuit topology similar to that of the first output driver 725. The second output driver 726 may comprise a separate third supply voltage source, preferably similar to the third supply voltage source of the first output driver, to generate a mid-point voltage. Alternatively, the mid-point voltage generated for the first output driver 725 may be utilized by the second output driver as well. The circuit topology of the second output driver 726 and electrical characteristics of its individual components are preferably substantially identical to those of the first output driver 725.

(38) A controller 703 is configured to receive an audio input signal, Audio, and derive a first set of pulse width modulated control signals and a second set of pulse width modulated control signals therefrom. The first set of pulse width modulated control signals are illustrated by Vc1, Vc2, Vc3 and Vc4 which are applied to the gate terminals of CMOS semiconductor switches SW1, SW2, SW3 and SW4, respectively. The second set of pulse width modulated control signals are illustrated by Vc5, Vc6, Vc7 and Vc8 which are applied to CMOS semiconductor switches SW5, SW6, SW7 and SW8, respectively, arranged inside the second output driver 726. The controller is configured to control a predetermined phase relationship between the first set of pulse width modulated control signals and the second set of pulse width modulated control signals such that a three-level load signal is generated across the loudspeaker load 740 in a first operation mode and a five-level load signal generated across the loudspeaker load 740 in a second operation mode. An exemplary illustration of the process for the generation of the first and second sets of pulse width modulated control signals is explained in additional detail below in connection with FIG. 9a) and FIG. 9b).

(39) FIG. 8 is a schematic diagram of a class D audio amplifier with an H-bridge output driver comprising first and second output drivers 825, 826, respectively, coupled to a loudspeaker load 840 in accordance with a fourth embodiment of the invention. A first load inductor 838 and a first load capacitor 822 is coupled between a first output node V.sub.A of the first driver 825 and a first terminal of the loudspeaker load 840 to form a lowpass filter. Another lowpass filter is formed by a second load inductor 837 and a second load capacitor 823 which are coupled between a second output node V.sub.B of the second driver 826 and a second terminal of the loudspeaker load 840. The purpose and characteristics of each of these lowpass filters are the same as those previously discussed in connection with the first embodiment of output driver 401. The first output driver 825 comprises a first and second series coupled semiconductor switches SW1, SW2 coupled in-between a first supply voltage V.sub.S and the first output node V.sub.A. Third and fourth semiconductor switches SW3, SW4 are coupled in series between GND, i.e. a second supply voltage, and V.sub.A. A first semiconductor diode D1 is coupled from a mid-point voltage V.sub.S to a first node 818a, located between SW1 and SW2. A second semiconductor diode D2 is coupled from the mid-point voltage V.sub.S to a second node 818b, located between SW3 and SW4. The mid-point voltage V.sub.S is generated by third supply voltage source for the first and, optionally second, output driver 825, 826. The third supply voltage source comprises a pair of supply capacitors, C1 and C2, coupled in series between the first supply voltage V.sub.S and GND voltage to provide the mid-point voltage. The supply capacitors, C1 and C2 preferably have substantially equal capacitance such that the mid-point voltage is set to approximately one-half of the first supply voltage V.sub.S. Each of the semiconductor switches, SW1, SW2, SW3 and SW4 comprises a gate terminal Gc1, Gc2, Gc3 and Gc4, respectively, to control the setting of the state (i.e. on-state or off-state) of the semiconductor switch in question. The second output driver 826 comprises the second output node V.sub.B which is coupled to an opposite side or terminal of the loudspeaker load 840. The second output driver 826 comprises CMOS semiconductor switches SW5, SW6, SW7 and SW8 coupled in a circuit topology similar to that of the first output driver 825. The second output driver 826 may comprise a separate third supply voltage source, preferably similar to the third supply voltage source of the first output driver, to generate a separate mid-point voltage. Alternatively, the mid-point voltage generated for the first output driver 825 may be utilized by the second output driver as well. The circuit topology of the second output driver 826 and electrical characteristics of its individual components are preferably substantially identical to those of the first output driver 825.

(40) A controller 803 is configured to receive an audio input signal, Audio, and derive a first set of pulse width modulated control signals and a second set of pulse width modulated control signals therefrom. The first set of pulse width modulated control signals are illustrated by Vc1, Vc2, Vc3 and Vc4 which are applied to gate terminals of the CMOS semiconductor switches SW1, SW2, SW3 and SW4, respectively. The second set of pulse width modulated control signals are illustrated by Vc5, Vc6, Vc7 and Vc8 which are applied to the CMOS semiconductor switches SW5, SW6, SW7 and SW8 (not shown), respectively, arranged inside the second output driver 826. The output voltage at the first output node V.sub.A can be set to approximately the mid-point voltage V.sub.S when SW2 and SW3 are set to their respective on-states. When SW2 and SW3 simultaneously are in their on-states, a bi-directional current path is formed between the mid-point voltage and V.sub.A since D1 will conduct current in one direction and D2 conduct current in the opposite direction. Consequently, the voltage at the first output node V.sub.A can be set to three different levels to provide the desired three-level load signal. The skilled person will understand the output voltage at the second output node V.sub.B can be set to three different levels in a corresponding manner.

(41) The controller 803 is configured to control a predetermined phase relationship between the first set of pulse width modulated control signals and the second set of pulse width modulated control signals such that a three-level load signal is generated across the loudspeaker load 840 in a first operation mode and a five-level load signal generated across the loudspeaker load 840 in a second operation mode. An exemplary illustration of the process for the generation of the first and second sets of pulse width modulated control signals is explained in additional detail below in connection with FIGS. 9a) and 9b).

(42) FIGS. 9a) and 9b) illustrate the generation of pulse width modulated control signals for each of the semiconductor switches of the H-bridge output driver 401 depicted on FIG. 4b). The pulse width modulated control signals SW.sub.1-SW.sub.8 are derived by a switching pattern mapping circuit (1119 of FIG. 11) of the controller 1103 depicted on FIG. 11 from an audio input signal. The illustrated waveform shapes of the pulse width modulated control signals SW.sub.1-SW.sub.8 of FIGS. 9a) and 9b) are mapped for predetermined non-zero instantaneous level of the audio input signal, i.e. with modulation. FIG. 9a) illustrates the generation of pulse width modulated control signals in the three-level operation mode of the class D audio amplifier 1100 of FIG. 11 while FIG. 9b) illustrates the generation of pulse width modulated control signals in the five-level operation mode. In both operation modes, the analog PWM 1115 depicted on FIG. 11 is configured to derive four pulse width modulated signals .sub.0, .sub.90, .sub.180 and .sub.270 successively phase-shifted 90 degrees from each other and convey these to the switching pattern mapping circuit.

(43) In the three-level operation mode depicted on FIG. 9a), the switching pattern mapping circuit performs a phase selection by selecting pulse width modulated signals .sub.0 and .sub.180 as the pulse width modulated control signals SW.sub.1 and SW.sub.2 for semiconductor switches SW1 and SW2 of the first output driver (item 425 of FIG. 4b). The switching pattern mapping circuit furthermore generates a pair of pulse width modulated control signals SW.sub.3 and SW.sub.4 that are in opposite phase, or inverted, relative to SW.sub.2 and SW.sub.1, respectively, as the pulse width modulated control signals for semiconductor switches SW3 and SW4 of the first output driver. From the selected pulse width modulated signals .sub.0 and .sub.180 the switching pattern mapping circuit furthermore generates pulse width modulated control signals SW.sub.8 and SW.sub.7 for semiconductor switches SW8 and SW7 of the second output driver (item 426 of FIG. 4b). The switching pattern mapping circuit furthermore generates a pair of pulse width modulated control signals SW.sub.5 and SW.sub.6 that are in opposite phase to SW.sub.8 and SW.sub.7, respectively, as the pulse width modulated control signals for the semiconductor switches SW8 and SW7 of the second output driver. Consequently, in the three-level operation mode the switching pattern mapping circuit is configured to generate a first set of modulated control signals in form of the pulse width modulated control signals SW.sub.1, SW.sub.2, SW.sub.3 and SW.sub.4 for the first output driver that are in opposite phase, or inverted, relative to corresponding pulse width modulated control signals of a second set of pulse width modulated control signals SW.sub.8, SW.sub.6, SW.sub.7 and SW.sub.8 for the second output driver. In this manner the pulse width modulated control signals SW.sub.1 for the first output driver is rendered in opposite phase to the corresponding pulse width modulated control signal SW.sub.5 for the second output driver, SW.sub.2 for the first output driver rendered in opposite phase to the corresponding pulse width modulated control signal SW.sub.6 for the second output driver and so on.

(44) In the five-level operation mode depicted on FIG. 9b), the switching pattern mapping circuit performs a phase selection by selecting and re-arranging all pulse width modulated signals .sub.0, .sub.90, .sub.180 and .sub.270 as illustrated before generating the first set of modulated control signals in form of the pulse width modulated control signals SW.sub.1, SW.sub.2, SW.sub.3 and SW.sub.4 for the first output driver. By comparison with FIG. 9a), it is evident that the respective waveforms of the pulse width modulated control signals SW.sub.1, SW.sub.2, SW.sub.3 and SW.sub.4 of the first output driver are identical in the three-level and five-level operation modes. However, the waveforms of the second set of control signals in form of the pulse width modulated control signals SW.sub.5, SW.sub.6, SW.sub.7 and SW.sub.8 of the second output driver differ between the three-level and five-level operation modes as illustrated. The switching pattern mapping circuit is configured to generate pulse width modulated control signals in the second set of pulse width modulated control signals SW.sub.5, SW.sub.6, SW.sub.7 and SW.sub.8 for the second output driver that are inverted and additionally phase shifted with minus 90 degrees relative to the corresponding pulse width modulated control signals of the first set of pulse width modulated control signals SW.sub.1, SW.sub.2, SW.sub.3 and SW.sub.4 for the first output driver. In this manner the pulse width modulated control signal SW.sub.5 for the second output driver is rendered inverted and with an additional minus 90 degrees phase shift relative to the corresponding pulse width modulated control signal SW.sub.1 for the first output driver, SW.sub.6 for the second output driver rendered inverted and additionally phase shifted minus 90 degrees relative to the corresponding pulse width modulated control signal SW.sub.2 for the first output driver and so on.

(45) FIGS. 10a) and 10b) are respective graphs of load capacitor ripple voltage and load inductor ripple current, respectively, plotted versus modulation duty cycle of the pulse width modulated switch control signals. A modulation duty cycle of 0.5 corresponds to zero modulation of the pulse width modulated audio signal which in turn corresponds to zero level of the audio input signal as indicated on the graph 1001 by the marking Idle operation. The depicted graphs have been plotted for a load inductor value of 10 H (refer to FIG. 4b) item 438) and a load capacitor value of 1 F (refer to FIG. 4b) item 422). The first or upper DC supply voltage V.sub.S or P.sub.VDD of the H-bridge output driver 401 was set to 40 Volt. The switching or modulation frequency of each of the pulse width modulated switch controls signals was set to 400 kHz.

(46) The graph 1001 of FIG. 10a) displays the load capacitor ripple voltage measured in Volts peak-to-peak on the load capacitor (item 422 of FIG. 4b)) for two different types of class D audio amplifiers. Curve 1003 shows capacitor ripple voltage for the prior art output drivers utilizing 2-level class AD or BD modulation as displayed on FIGS. 1, 2 and 3. The curve 1005 shows capacitor ripple voltage for the 3-level operation mode of the H-bridge output driver 401 of FIG. 4b) in accordance with the first aspect of the present invention. A large reduction of the peak-to-peak capacitor ripple voltage, in particular around zero modulation, is evident. This decrease of capacitor ripple voltage leads to a very advantageous suppression or attenuation of EMI emissions from class D amplifier based on the present H-bridge output driver 401 even when identical capacitance values of the load capacitors are used.

(47) Graph 1011 of FIG. 10b) displays the load inductor ripple current in the load inductor (item 438 of FIG. 4b)) measured in Amperes peak-to-peak for two different types of class D audio amplifiers. The curve 1013 shows load inductor ripple current for the prior art 2-level class AD or BD modulation output drivers displayed on FIGS. 1, 2 and 3 measured with a load inductor value of 10 H and load capacitor value of 1 F. The curve 1015 shows load inductor ripple current for the 3-level operation mode of the H-bridge output driver 401 of FIG. 4b). However, in the latter case, the load inductor value is only 2.2 H (compared to 10 H for the 2-level class AD or BD modulation output drivers) and the load capacitor value is 0.47 F. A very large reduction of amplitude of the inductor ripple current is achieved around zero modulation, i.e. for small audio input signals that tend to dominate everyday listening situations, despite the significantly smaller values of load inductance and load capacitance for the present H-bridge output driver.

(48) FIG. 11 illustrates schematically a class D audio amplifier 1100 comprising an H-bridge driver 1101 similar to the H-bridge output driver 401 depicted on FIG. 4b) coupled to a controller 1103 in accordance with a preferred embodiment of the invention. The present class D audio amplifier 1100 utilizes a sophisticated audio input signal level dependent switching between two different operational modes as explained in detail below.

(49) The schematically illustrated H-bridge driver 1101 comprises a gate drive circuit 1109 that increases amplitudes of respective pulse width modulated control signals for the eight semiconductor switches of the power stage 1107 to a level that allows the individual semiconductor switches to be appropriately placed in ON and OFF states. The gate drive circuit 1109 may comprises various types of level converters. The amplitude of each of the pulse width modulated switch control signals may be around 1.8 Volt, 3.3 Volt or 5 Volt when supplied from a normal CMOS integrated circuit comprising the controller 1103. If the DC supply voltage of the H-bridge driver for example is set to about 40 Volts, the amplitudes of the pulse width modulated switch control signals are raised to about 40 Volts, or more, by the gate drive circuit 1109 as well. The power stage 1107 has a circuit topology largely identical to the H-bridge output driver 401 depicted on FIG. 4b) as mentioned before. The characteristics of the output filter circuit 1105 are preferably also similar to the output filter coupled to the H-bridge output driver 401. The output filter circuit 1105 accordingly comprises a load inductor and load capacitor coupled to each of a first and a second output node of the H-bridge output driver 1101.

(50) The controller 1103 preferably comprises a software programmable Digital Signal Processor (DSP) configured to provide the below described functions or operations in accordance with a set of executable program instructions. The controller 1103 comprises a subtraction circuit 1131 for receipt of analog audio input signals. A feedback signal derived from the first or second output node of the H-bridge output driver prior to the output filter circuit 1105 is subtracted from the analog audio input signal by the subtraction circuit 1131 to form a resulting audio signal. The resulting audio signal is transmitted into the loop filter 1117. The loop filter 1117 comprises one or more integrators, schematically illustrated by integrator symbols and integrator coefficients K.sub.1-K.sub.n, that lowpass filters the resulting audio input signal before transmission to an analog pulse width modulator circuit 1115 or analog PWM. The carrier frequency of the analog PWM 1115 is controlled by a PWM clock circuit 1121 that generates synchronization pulses to the analog PWM 1115. The analog PWM 1115 produces a naturally sampled pulse width modulated audio signal with a carrier frequency set by the PWM clock circuit 1121. The naturally sampled pulse width modulated audio signal is conveyed to a switching pattern mapping circuit 1119. The switching pattern mapping circuit 1119 is configured to generate an appropriately phased and timed pulse width modulated control signal for each of the eight semiconductor switches of the power stage 1107 as previously explained in connection with FIGS. 9a) and 9b). In the present embodiment of the invention, the output of the switching pattern mapping circuit 1119 is therefore eight pulse width modulated control signals which are conveyed to an optional timing controller 1133. The timing controller 1133 may be adapted to perform certain time base adjustments to one or more of the eight pulse width modulated control signal for example dead-time control between certain pairs of control signals to ensure non-overlap of the same control signals. The eight time-base adjusted pulse width modulated control signals are thereafter transmitted to the gate drive 1109 as described above.

(51) In one embodiment, the switching pattern mapping circuit 1119 comprises a sampling circuit embodied as a digital register that is operated by a clock signal, Clock, of the class D amplifier. The digital register regularly samples or latches a signal value of the naturally sampled pulse width modulated audio signal synchronously to the clock signal to provide a uniformly sampled pulse width modulated audio signal representative of the naturally sampled pulse width modulated audio signal. The sampling frequency at which the register is operated may be set to value between 10 MHz and 400 MHz such as between 50 MHz and 200 MHz for carrier frequencies of the naturally sampled pulse width modulated audio signal between 100 kHz and 1.2 MHz.

(52) In other embodiments, the switching pattern mapping circuit 1119 operates entirely in the analog domain such that each of the respective pulse width modulated control signals for the eight semiconductor switches of the power stage 1107 is a naturally sampled pulse width modulated audio signal.

(53) However, in both embodiments, the switching pattern mapping circuit 1119 is configured to generate pulse width modulated switch control signals with appropriate timing and polarity to the eight individual semiconductor switches of the H-bridge output driver 1107 as described above in connection with FIG. 4b) and FIGS. 9a) and 9b). The carrier frequency of each of the pulse width modulated control signals is set by the PWM clock generator 1121 operating in accordance with a clock frequency control signal set by the clock management circuit 1123. The clock management circuit 1123 is thereby adapted to control the carrier frequency of the PWM clock generator 1121. A power management circuit 1125 comprises a modulation sensing input port 1127 allowing the power management circuit 1125 to detect a modulation duty cycle of the pulse width modulated audio signal supplied to the input of the switching pattern mapping circuit 1119. Since the detected modulation duty cycle indicates an instantaneous level of the resulting audio input signal, the power management module exploits this audio level information to control the carrier frequency setting of the pulse width modulated control signals or switch control signals. Furthermore, the power management circuit or module 1125 is further adapted to exploit the audio level information to select between a 3-level modulation mode and 5-level modulation mode at the output nodes of the H-bridge output driver 1107. In the present embodiment, the power management circuit 1125 is configured to switch between three distinct operational modes depending on the detected modulation duty cycle. Lower and upper modulation thresholds determine both the appropriate settings of the carrier frequency and the appropriate setting of the operation mode (3-level mode or 5-level mode in the present embodiment) such that a first or super-idle mode is entered when the detected modulation duty cycle is below the lower modulation threshold. This first modulation threshold may for example be set to a modulation index between 0.01 and 0.05 such as about 0.02. In the super-idle mode, the carrier frequency f.sub.sw may be set to about 150 KHz and the switch control signals are preferably configured to provide 5-level modulation by the switching pattern mapping circuit 1119. This operational mode is graphically depicted as super-idle mode 1203 in FIG. 12 where the horizontal arrow indicates increasing direction of the level of the audio input signal and thus increasing modulation duty cycle.

(54) The power management circuit 1125 is configured to switch to a second or low-power mode 1205 once the detected modulation duty cycle exceeds the lower modulation threshold but still lies below the upper modulation threshold. This second modulation threshold may for example be set to a modulation index between 0.05 and 0.2 such as about 0.1. In the low-power mode, the carrier frequency f.sub.sw is preferably increased relative to the super-idle mode because it allows a higher loop bandwidth of the feedback path so as to improve suppression of non-linarites in the H-bridge output driver of the power stage 1107. The carrier frequency f.sub.sw may be set to about twice the latter carrier frequency. The switch control signals are preferably configured to maintain the existing 5-level modulation to maximize the loop bandwidth of the feedback path for a given setting of the carrier frequency f.sub.sw of the naturally sampled pulse width modulated audio signal.

(55) Finally, the power management circuit 1125 is configured to switch to a third or normal mode 1207 once the detected modulation duty cycle exceeds the upper modulation threshold. In the normal mode, the carrier frequency f.sub.sw is preferably increased by a predetermined amount relative to the carrier frequency of the low-power mode because of the change of operational mode in normal mode. This change would tend to reduce the loop bandwidth if the carrier frequency remained constant. However, the 3-level modulation of output signal across the loudspeaker load suppresses the common mode component of the load capacitor ripple voltage in an advantageous manner to improve EMI performance at large audio signal levels.

(56) In certain embodiments, the power management circuit 1125 may be adapted to alter frequency response characteristics of the loop filter 1117 in an adaptive manner depending on the detected modulation duty cycle through a filter control signal 1129. This is particularly useful to maintain or change an existing loop filter bandwidth in response to a switch between the above-described super-idle mode, low-power mode and normal mode.

(57) FIG. 13 illustrates experimentally recorded power dissipation data for the prior art H-bridge output driver depicted on FIG. 2 using AD modulation in comparison to the H-bridge output driver in accordance with present invention depicted on FIG. 4b) applying the modulation duty cycle dependent mode switching scheme disclosed above in connection with FIGS. 11 and 12. The audio input signal is a 1 kHz sine wave and the loudspeaker load is 8 ohm in both illustrated cases. The prior art H-bridge driver uses a load inductor value of 9.4 H and a modulation frequency of 400 kHz. The H-bridge output driver in accordance with present invention uses a load inductor value of 2.2 H and a modulation frequency of 600 kHz.

(58) Curve 1301 represents the measured power loss in Watts versus supplied load power or output power for the prior art H-bridge output driver while curve 1303 represents the same figure of merit for the H-bridge output driver in accordance with present invention. As illustrated, a considerable reduction of power loss is offered by the present invention throughout the majority of the linear operation range of the H-bridge output drivers. The marked reduction in power loss for small values of the delivered output power such as output powers less than 1 Watt, are particularly noticeable because this power range is used in many everyday listing situations. The measured power dissipation savings amount to a factor of about 9 (nine) for small values of the output or load power. It is also noticeable that this markedly improved energy efficiency is obtained without using larger load inductor or load capacitors values for the present H-bridge driveron the contrary under the conditions for the experimentally recorded power loss data of FIG. 13 the load inductor is significantly smaller.