VOLTAGE REFERENCE BUFFER CIRCUIT

Abstract

The present invention discloses a voltage reference buffer circuit. An embodiment of the voltage reference buffer circuit includes: a first bias generator configured to generate a first bias voltage; a second bias generator configured to generate a second bias voltage different from the first bias voltage; a first driving component coupled to a high voltage terminal, the first bias generator and a reference voltage output terminal, and configured to control a reference voltage at the reference voltage output terminal according to the first bias voltage; and a second driving component coupled to the reference voltage output terminal, the second bias generator and a low voltage terminal, and configured to control a current between the reference voltage output terminal and the second driving component according to the second bias voltage.

Claims

1. A voltage reference buffer circuit, comprising: a first bias generator configured to generate a first bias voltage; a second bias generator configured to generate a second bias voltage different from the first bias voltage; a first driving component coupled to a high voltage terminal, the first bias generator and a reference voltage output terminal, and configured to control a reference voltage at the reference voltage output terminal according to the first bias voltage; and a second driving component coupled to the reference voltage output terminal, the second bias generator and a low voltage terminal, and configured to control a current between the reference voltage output terminal and the second driving component according to the second bias voltage, wherein the first driving component and the second driving component are different types of transistors.

2. The voltage reference buffer circuit of claim 1, wherein a circuit composed of the first bias generator and the first driving component includes a first current mirror, and a circuit composed of the second bias generator and the second driving component includes a second current mirror.

3. The voltage reference buffer circuit of claim 1, wherein the first bias generator includes: a negative feedback circuit including a voltage input terminal, a negative feedback circuit output terminal and a negative feedback terminal; and a third driving component coupled to the high voltage terminal, the negative feedback circuit output terminal and the negative feedback terminal, and configured to control a voltage at the negative feedback terminal according to a voltage at the negative feedback circuit output terminal, in which a terminal, that is coupled to the negative feedback circuit output terminal, of the third driving component is coupled to the first driving component to form a first current mirror, and the voltage at the negative feedback circuit output terminal is the first bias voltage.

4. The voltage reference buffer circuit of claim 3, wherein the first bias generator further includes: a voltage generator configured to provide a voltage at the voltage input terminal or configured to adjust and provide the voltage at the voltage input terminal.

5. The voltage reference buffer circuit of claim 3, wherein the second bias generator includes: a current source; a current mirror circuit including a current source terminal and a mirrored current terminal, in which the current source terminal is coupled to the current source and a voltage at the mirrored current terminal is the second bias voltage; and a fourth driving component coupled to the negative feedback terminal, the second driving component and the mirrored current terminal, while the fourth driving component is coupled to the second driving component to form a second current mirror.

6. The voltage reference buffer circuit of claim 1, wherein the first driving component is set between the high voltage terminal and the reference voltage output terminal, the second driving component is set between the low voltage terminal and the reference voltage output terminal, one end of the first driving component is coupled with the reference voltage output terminal, one end of the second driving component is coupled with the reference voltage output terminal, and both the voltage of the end of the first driving component and the voltage of the end of the second driving component are equal to the reference voltage.

7. The voltage reference buffer circuit of claim 6, wherein the first driving component includes an NMOS transistor, the second driving component includes a PMOS transistor, the end of the first driving component is a source of the NMOS transistor, and the end of the second driving component is a source of the PMOS transistor.

8. The voltage reference buffer circuit of claim 3, further comprising: a resistance circuit coupled between the negative feedback terminal and the low voltage terminal, and configured to control the voltage at the negative feedback terminal.

9. The voltage reference buffer circuit of claim 1, wherein the second bias generator includes: a current source; a current mirror circuit including a current source terminal and a mirrored current terminal, in which the current source terminal is coupled to the current source and a voltage at the mirrored current terminal is the second bias voltage; and a fourth driving component coupled to the first bias generator, the second driving component and the mirrored current terminal, while the fourth driving component is coupled to the second driving component to form a second current mirror.

10. The voltage reference buffer circuit of claim 9, wherein the current source is an adjustable current source.

11. The voltage reference buffer circuit of claim 1, wherein the second bias generator includes: a negative feedback circuit including a voltage input terminal, a negative feedback circuit output terminal and a negative feedback terminal, in which the negative feedback terminal is coupled to the first bias generator; and a fourth driving component coupled to the negative feedback terminal, the negative feedback circuit output terminal and the low voltage terminal, and configured to control a voltage at the negative feedback terminal according to a voltage at the negative feedback circuit output terminal, in which a terminal, that is coupled to the negative feedback circuit output terminal, of the fourth driving component is coupled to the second driving component to form a second current mirror, and the voltage at the negative feedback circuit output terminal is the second bias voltage.

12. The voltage reference buffer circuit of claim 11, further comprising a resistance circuit coupled between the first bias generator and the negative feedback terminal.

13. The voltage reference buffer circuit of claim 1, wherein the first driving component is a first transistor, the second driving component is a second transistor, a ratio of a channel width of the second transistor to a channel length of the second transistor is N times a ratio of a channel width of the first transistor to a channel length of the first transistor, in which the N is not less than two and not greater than four.

14. The voltage reference buffer circuit of claim 13, wherein the N is three.

15. The voltage reference buffer circuit of claim 1, wherein the first driving component is an NMOS transistor, and the second driving component is a PMOS transistor.

16. The voltage reference buffer circuit of claim 1, further comprising: a resistance load coupled between the reference voltage output terminal and the low voltage terminal for controlling the reference voltage, wherein the current between the reference voltage output terminal and the second driving component is greater than a current between the reference voltage output terminal and the resistance load.

17. The voltage reference buffer circuit of claim 16, wherein the current between the reference voltage output terminal and the second driving component is not less than two times the current between the reference voltage output terminal and the resistance load.

18. The voltage reference buffer circuit of claim 16, wherein the resistance load includes a plurality of resistors connected in series and thereby provides the reference voltage and at least one voltage division less than the reference voltage.

19. A voltage reference buffer circuit, comprising: a first bias generator for generating a first bias voltage; a second bias generator for generating a second bias voltage different from the first bias voltage; a first driving component coupled to a high voltage terminal, the first bias generator and a reference voltage output terminal, and configured to control a reference voltage at the reference voltage output terminal according to the first bias voltage; a second driving component coupled to the reference voltage output terminal, the second bias generator and a resistance load, and configured to control a current between the reference voltage output terminal and the second driving component according to the second bias voltage, in which the first driving component and the second driving component are different types of transistors; a third bias generator for generating a third bias voltage; a fourth bias generator for generating a fourth bias voltage different from the third bias voltage; a third driving component coupled to the resistance load, the third bias generator and another reference voltage output terminal, and configured to control another reference voltage at the another reference voltage output terminal according to the third bias voltage; and a fourth driving component coupled to the another reference voltage output terminal, the fourth bias generator and a low voltage terminal, and configured to control a current between the another reference voltage output terminal and the fourth driving component according to the fourth bias voltage, in which the third driving component and the fourth driving component are different types of transistors.

20. The voltage reference buffer circuit of claim 19, wherein the first driving component is set between the high voltage terminal and the reference voltage output terminal, the second driving component is set between the low voltage terminal and the reference voltage output terminal, a transistor source of the first driving component is coupled with the reference voltage output terminal, a transistor source of the second driving component is coupled with the reference voltage output terminal, and both the voltage of the transistor source of the first driving component and the voltage of the transistor source of the second driving component are equal to the reference voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 illustrates an embodiment of the voltage reference buffer circuit of the present invention.

[0011] FIG. 2 illustrates an embodiment of the first bias generator of FIG. 1.

[0012] FIG. 3 illustrates another embodiment of the first bias generator of FIG. 1.

[0013] FIG. 4 illustrates an embodiment of the second bias generator of FIG. 1.

[0014] FIG. 5 illustrates another embodiment of the voltage reference buffer circuit of the present invention.

[0015] FIG. 6 illustrates a further embodiment of the voltage reference buffer circuit of the present invention.

[0016] FIG. 7 illustrates another embodiment of the second bias generator of FIG. 1.

[0017] FIG. 8 illustrates a further embodiment of the voltage reference buffer circuit of the present invention.

[0018] FIG. 9 illustrates the comparison of current sink capability between the present invention and a prior art.

[0019] FIG. 10 illustrates the comparison of current source capability between the present invention and a prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The following description is written by referring to terms acknowledged in this industrial filed. If any term is defined in the description, such term should be explained accordingly. Besides, the connection between objects in the disclosed embodiments of this specification can be direct or indirect provided that these embodiments are still practicable under such connection. Said indirect indicates that an intermediate object or a physical space is existed between the objects. In addition, the shape, size, and ratio of any element in the disclosed drawings are just exemplary for understanding rather than restrictive for the present invention.

[0021] The present invention discloses a voltage reference buffer circuit using a plurality of driving components for enhancing the capability of souring and sinking current, and achieving the efficacy of prompt operation and low power consumption.

[0022] Please refer to FIG. 1 showing an embodiment of the voltage reference buffer circuit of the present invention. The voltage reference buffer circuit 100 of FIG. 1 includes a first bias generator 110, a second bias generator 120, a first driving component 130 and a second driving component 140. In this embodiment, the first driving component 130 and the second driving component 140 provide driving assistance concurrently under a normal state when a reference voltage is outputted; in other words, when the voltage reference buffer circuit 100 normally operates, the first driving component 130 and the second driving component 140 keep providing driving assistance. An embodiment of the first driving component 130 is a first transistor (e.g., an NMOS transistor or another type of transistor), and an embodiment of the second driving component 140 is a second transistor (e.g., a PMOS transistor or another type of transistor).

[0023] In detail, the first bias generator 110 is configured to generate a first bias voltage V.sub.b1, and the second bias generator 120 is configured to generate a second bias voltage V.sub.b2 that is different from the first bias voltage V.sub.b1. The first driving component 130 includes three first electrodes (e.g., the drain, gate and source of an NMOS) that are connected to a high voltage terminal V.sub.DD, the first bias generator 110 and a reference voltage output terminal V.sub.R respectively, and the first driving component 130 is configured to control a reference voltage at the reference voltage output terminal V.sub.R according to the first bias voltage V.sub.b1. The second driving component 140 includes three second electrodes (e.g., the source, gate and drain of an PMOS) that are connected to the reference voltage output terminal V.sub.R, the second bias generator 120 and a low voltage terminal V.sub.SS respectively, and the second driving component 140 is configured to control a current between the reference voltage output terminal V.sub.R and the second driving component 140 according to the second bias voltage V.sub.b2. In an exemplary implementation of this embodiment, the first driving component 130 and the second driving component 140 are different types of transistors. In an exemplary implementation of this embodiment, a circuit composed of the first bias generator 110 and the first driving component 130 includes a first current mirror as shown in FIG. 2, and a circuit composed of the second bias generator 120 and the second driving component 140 includes a second current mirror as shown in FIG. 4 or FIG. 7.

[0024] Please refer to FIG. 2 showing an embodiment of the first bias generator 110 of FIG. 1. As shown in FIG. 2, the first bias generator 110 includes a negative feedback circuit (e.g., an operational amplifier) 210 and a third driving component 220. The negative feedback circuit 210 includes a voltage input terminal V.sub.+, a negative feedback circuit output terminal V.sub.OP and a negative feedback terminal V.sub.. The third driving component 220 is configured to control a voltage at the negative feedback terminal V.sub. according to a voltage at the negative feedback circuit output terminal V.sub.OP. In this embodiment, a terminal of the third driving component 220 is coupled to the negative feedback circuit output terminal V.sub.OP, and this terminal is coupled to the first driving component 130 to form a first current mirror, furthermore, the voltage at the negative feedback circuit output terminal V.sub.OP is the first bias voltage V.sub.b1, so that the first driving component 130 controls the reference voltage at the reference voltage output terminal V.sub.R according to the first bias voltage V.sub.b1; in other words, by controlling the voltage (i.e., the first bias voltage V.sub.b1) at the negative feedback circuit output terminal V.sub.OP and a conduction setting of the first driving component 130 (e.g., the voltage difference V.sub.GS between the gate and the source), the reference voltage at the reference voltage output terminal V.sub.R can be controlled.

[0025] Please refer to FIG. 3 showing another embodiment of the first bias generator 110 of FIG. 1. In comparison with FIG. 2, the first bias generator 110 of FIG. 3 further includes a voltage generator 310 configured to provide a voltage at the voltage input terminal V+(while the circuit 310 is a constant voltage generator or an adjustable voltage generator) or configured to adjust and provide the voltage at the voltage input terminal V+(while the circuit 310 is an adjustable voltage generator). Since the voltage (i.e., the first bias voltage V.sub.b1) at the negative feedback circuit output terminal V.sub.OP will approach the voltage at the voltage input terminal V.sub.+ through a negative feedback mechanism, the voltage at the negative feedback circuit output terminal V.sub.OP can be controlled through the control over the voltage at the voltage input terminal V+. People of ordinary skill in the art can appreciate that the voltage generator 310 can be realized with the existing arts such as a combination of a current source and a resistor, and thus the detail of the voltage generator 310 is omitted here.

[0026] Please refer to FIG. 4 showing an embodiment of the second bias generator 120 of FIG. 1. The second bias generator 120 of FIG. 4 includes a current source 410, a current mirror circuit 420 and a fourth driving component 430. The current mirror circuit 420 includes a current source terminal 422 and a mirrored current terminal 424. The current source terminal 422 is coupled to the current source 410, and a voltage at the mirrored current terminal 424 is the second bias voltage V.sub.b2. The fourth driving element 430 includes three fourth electrodes (e.g., the source, gate and drain of a PMOS) that are connected to the first bias generator 110 (e.g., the negative feedback terminal V.sub. of the first bias generator 110 in FIG. 3), the second bias component 140 and the mirrored current terminal 424 respectively. In this embodiment, the fourth driving component 430 is coupled to the second driving component 140 to form a second current mirror, so that the second driving component 140 controls the current between the reference voltage output terminal V.sub.R and the second driving component 140 according to the second bias voltage V.sub.b2; in other words, since the current of the current source 410 is proportional to the current of the mirrored current terminal 424 and the current of the mirrored current terminal 424 is proportional to the current flowing through the second driving component 140, the current between the reference voltage output terminal V.sub.R and the second driving component 140 can be controlled by controlling the current of the current source 410. This current source 410 is a constant current source or an adjustable current source.

[0027] Please refer to FIG. 5. In an embodiment, in order to further control the first bias voltage V.sub.b1 (e.g., the voltage at the negative feedback circuit output terminal V.sub.OP in FIG. 2), a resistance circuit 510 is set between the first bias generator 110 and the aforementioned low voltage terminal V.sub.SS (e.g., between the negative feedback terminal V.sub. and the low voltage terminal V.sub.SS in FIG. 2); however, this resistance circuit 510 is not a must for the present invention.

[0028] Please refer to FIG. 6. In an embodiment, in order to further control the voltage at the reference voltage output terminal V.sub.R, a resistance load 610 is set between the reference voltage output terminal V.sub.R and the low voltage terminal V.sub.SS; however, this resistance load 610 is not a must for the present invention. In this embodiment, the resistance load 610 includes at least one resistor; when the resistance load 610 includes a plurality of resistors connected in series, the resistance load 610 provides the reference voltage at the reference voltage output terminal V.sub.R and at least one voltage division less than the reference voltage. If this embodiment is applied to a specific circuit such as a successive approximation register analog-to-digital converter (SAR ADC), a plurality of resistors with proper resistance values can be selected as the above-mentioned serially connected resistors, so as to make the reference voltage be 2.sup.M times each of the at least one voltage division; however, this is an option rather than a limitation to the embodiment.

[0029] In an embodiment, in order to ensure the efficacy of the voltage reference buffer circuit 100, a current (I1) flowing through the first driving component 130 should be close to a current (I2) flowing through the second driving component 140. For instance, please refer to FIG. 6, the current (i.e., I2) between the reference voltage output terminal V.sub.R and the second driving component 140 should be greater than the current (I3) between the reference voltage output terminal V.sub.R and the resistance load 610, so as to have the current I1 be close to the current I2. In this instance, a resistance circuit with a higher resistance value is selected as the resistance load 610, so as to have the current I2 be equal to or greater than two times the current I3, or have the current I2 be equal to or greater than six times the current I3. The higher the ratio of the current I2 to the current I3 (i.e., I2/I3), the better the current driving capability (including current sinking capability) of the voltage reference buffer circuit 100. For another instance, as shown in FIG. 1 and FIG. 6, the ratio of the first driving component 130 (e.g., an NMOS transistor) to the second driving component 140 (e.g., a PMOS transistor) can be well controlled to have the current I1 be close to the current I2; more specifically, with proper design and/or fabrication, the ratio of the channel width of the second driving component 140 to the channel length of the second driving component 140 is N times the ratio of the channel width of the first driving component 130 to the channel length of the first driving component 130, in which the N is a positive number (e.g., a number between two and four, or a number equal or close to three).

[0030] FIG. 7 shows another embodiment of the second bias generator 120 of FIG. 1. The second bias generator 120 of FIG. 7 includes a negative feedback circuit 710 and a fourth driving component 720. The negative feedback circuit 710 includes a voltage input terminal V.sub.+, a negative feedback circuit output terminal V.sub.OP and a negative feedback terminal V.sub., in which the negative feedback terminal V.sub. is coupled to the first bias generator 110 (e.g., coupled to the negative feedback terminal V.sub. of the first bias generator 110 in FIG. 2). The fourth driving component 720 is coupled to the negative feedback terminal V.sub., the negative feedback circuit output terminal V.sub.OP and a low voltage terminal V.sub.SS, and configured to control a voltage at the negative feedback terminal V.sub. according to a voltage at the negative feedback circuit output terminal V.sub.OP (i.e., the second bias voltage V.sub.b2). In this embodiment, a terminal of the fourth driving component 720 is coupled to the negative feedback circuit output terminal V.sub.OP, and this terminal is also coupled to the second driving component 140 to form a second current mirror, so that the current flowing through the fourth driving component 720 is proportional to the current flowing through the second driving component 140. Accordingly, the second driving component 140 can control a current between the reference voltage output terminal V.sub.R and the second driving component 140 according to the voltage at the negative feedback circuit output terminal V.sub.OP (i.e., the second bias voltage V.sub.b2) that is determined by the voltage at the voltage input terminal V.sub.+.

[0031] FIG. 7 further includes a resistance circuit 730 that is coupled between the first bias generator 110 and the negative feedback terminal V.sub.. The resistance circuit 730 is configured to further control the voltage at the negative feedback terminal V.sub. and the current flowing through the fourth driving component 720. It should be noted that the resistance circuit 730 is an option instead of a must.

[0032] Please refer to FIG. 8 showing another embodiment of the voltage reference buffer circuit of the present invention. As shown in FIG. 8, in order to provide two reference voltages for a specific circuit (e.g., SAR ADC), the voltage reference buffer circuit 800 includes the aforementioned first bias generator 110, second bias generator 120, first driving component 130 and second driving component 140 for providing a reference voltage V.sub.R+, and the voltage reference buffer circuit 800 further includes a third bias generator 810, a fourth bias generator 820, a third driving component 830 and a fourth driving component 840 for providing another reference voltage V.sub.R, in which the third bias generator 810 provides a third bias voltage V.sub.b3, the fourth bias generator 820 provides a fourth bias voltage V.sub.b4 different from the third bias voltage V.sub.b3, and the third driving component 830 and the fourth driving component 840 are different types of transistors. In addition, the voltage reference buffer circuit 800 includes a resistance load 850 coupled between the second driving component 140 and the third driving component 830 for defining the two different reference voltages V.sub.R+, V.sub.R.

[0033] Since those of ordinary skill in the art can apply a feature of any of the aforementioned embodiments to the other embodiments in a reasonable way, repeated and redundant description is therefore omitted.

[0034] To sum up, the present invention uses a plurality of driving components for enhancing the capability of sourcing and sinking current, and thereby establishes or recover a reference voltage instantly. For instance, as shown in FIG. 9, in comparison with a known voltage reference buffer, after drawing current the present invention recovers a reference voltage (, that is to say making the reference voltage rise first and fall afterwards,) at a faster speed; this is because after connecting to a voltage reference reception circuit (e.g., SAR ADC), the present invention (with the setting of the aforementioned second driving component) can draw more current from the voltage reference reception circuit to recover the reference voltage quickly as shown by the solid line in FIG. 9. On the other hand, the known voltage reference buffer, especially the resistance load therein for establishing the reference voltage, draws less current from the voltage reference reception circuit and thus the reference voltage will be recovered at a slower speed as shown by the dash line in FIG. 9. For another instance, as shown in FIG. 10, after outputting current the present invention recovers a reference voltage (, that is to say making the reference voltage fall first and rise afterwards,) at a faster speed; this is because after connecting to a voltage reference reception circuit (e.g., SAR ADC), the present invention (with the setting of the aforementioned second driving component) can output more current to the voltage reference reception circuit to recover the reference voltage quickly as shown by the solid line in FIG. 10. On the other hand, the known voltage reference buffer, especially the resistance load therein for establishing the reference voltage, outputs less current to the voltage reference reception circuit and thus the reference voltage will be recovered at a slower speed as shown by the dash line in FIG. 10. Since those of ordinary skill in the art can appreciate the characteristics and advantages of the present invention in accordance with the configuration of the present invention, unnecessary explanation is omitted.

[0035] The aforementioned descriptions represent merely the exemplary embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of the present invention are all consequently viewed as being embraced by the scope of the present invention.