Circuitry and methods for use in mixed-signal circuitry

Abstract

Switching circuitry for use in a digital-to-analog converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.

Claims

1. Switching circuitry for use in a digital-to-analogue converter, the circuitry being operable based on an input data signal which alternates between having a logic high value and having a logic low value, and the circuitry comprising: first and second common nodes at which first and second currents are respectively received; first and second output nodes; first and second intermediate nodes; first and second clock-controlled switches; first and second controllable resistances; an amplifier; and a plurality of switches each connected to receive said input data signal or a data signal derived therefrom as an individual control signal of that switch, so that a signal level of the individual control signal received at a second switch of the plurality of switches is caused to change whenever a signal level of the individual control signal received at a first switch of the plurality of switches is caused to change, and a signal level of the individual control signal received at a fourth switch of the plurality of switches is caused to change whenever a signal level of the individual control signal received at a third switch of the plurality of switches is caused to change, the plurality of switches being connected and operable in each clock cycle of a series of clock cycles based on their respective control signals to direct the first current through the first common node, the first switch, the first intermediate node, the first clock-controlled switch and the first output node and the second current through the second common node, the fourth switch, the second controllable resistance, the second intermediate node, the second clock-controlled switch and the second output node when the input data signal in the clock cycle for the first and second switches has the logic high value, and to direct the second current through the second common node, the second switch, the first controllable resistance, the first intermediate node, the first clock-controlled switch and the first output node and the first current through the first common node, the third switch, the second intermediate node, the second clock-controlled switch and the second output node when the input data signal in the clock cycle for the first and second switches has the logic low value, wherein the first and second currents have non-zero values which are different from one another, and wherein the amplifier is configured to measure voltages at the first and second common nodes and to control resistance values of the first and second controllable resistances so as to equalize the voltages at the first and second common nodes.

2. Switching circuitry as claimed in claim 1, wherein the clock cycles are defined by a clock signal or a plurality of time-interleaved clock signals, which are substantially sinusoidal clock signals.

3. Switching circuitry as claimed in claim 1, wherein either the first and second currents both have a positive magnitude or the first and second currents both have a negative magnitude.

4. Switching circuitry as claimed in claim 1, wherein: the plurality of switches is connected between the first and second common nodes and the first and second output nodes and operable in each clock cycle of the series of clock cycles to conductively connect along respective paths the first common node to the first output node and the second common node to the second output node when the input data signal has the logic high value, and the first common node to the second output node and the second common node to the first output node when the input data signal has the logic low value.

5. Switching circuitry as claimed in claim 4, wherein a data-controlled and a clock-controlled switch are provided in series along each said path from the first or second common node to the first or second output node.

6. Switching circuitry as claimed in claim 5, wherein the clock cycles are defined by a clock signal or a plurality of time-interleaved clock signals, which are substantially sinusoidal clock signals, and wherein the switching circuitry comprises a clock generator operable to generate the or each clock signal, and clock-signal distribution circuitry configured to supply each clock-controlled switch with a said clock signal without that clock signal passing via a data-controlled switch.

7. Switching circuitry as claimed in claim 5, wherein pairs of said paths pass through the same clock-controlled switch, in each such pair one of the paths connecting to the first common node and the other connecting to the second common node.

8. Switching circuitry as claimed in claim 7, wherein, for each said pair of paths, the data-controlled switches of the two paths are controlled by respective mutually-complementary data signals.

9. Switching circuitry as claimed in claim 7, wherein, for each said pair of paths, the data-controlled switch of each path is connected between a said intermediate node common to both of those paths and the respective one of the first and second common nodes.

10. Switching circuitry as claimed in claim 9, further comprising, for each said pair of paths, said controllable resistance is connected in series between the intermediate node and the data-controlled switch in the one of those paths connected to the second common node.

11. Switching circuitry as claimed in claim 5, wherein the clock-controlled switches are controlled directly by a clock signal without that clock signal passing via a data-controlled switch.

12. Switching circuitry as claimed in claim 4, configured such that when one of the output nodes is conductively connected to the first common node the first current flows through those nodes, and when one of the output nodes is conductively connected to the second common node the second current flows through those nodes.

13. A digital-to-analogue converter, comprising switching circuitry for use in the digital-to-analogue converter, the switching circuitry being operable based on an input data signal which alternates between having a logic high value and having a logic low value, and the switching circuitry comprising: first and second common nodes at which first and second currents are respectively received; first and second output nodes; first and second intermediate nodes; first and second clock-controlled switches; first and second controllable resistances; an amplifier; and a plurality of switches each connected to receive said input data signal or a data signal derived therefrom as an individual control signal of that switch, so that a signal level of the individual control signal received at a second switch of the plurality of switches is caused to change whenever a signal level of the individual control signal received at a first switch of the plurality of switches is caused to change, and a signal level of the individual control signal received at a fourth switch of the plurality of switches is caused to change whenever a signal level of the individual control signal received at a third switch of the plurality of switches is caused to change, the plurality of switches being connected and operable in each clock cycle of a series of clock cycles based on their respective control signals to direct the first current through the first common node, the first switch, the first intermediate node, the first clock-controlled switch and the first output node and the second current through the second common node, the fourth switch, the second controllable resistance, the second intermediate node, the second clock-controlled switch and the second output node when the input data signal in the clock cycle for the first and second switches has the logic high value, and to direct the second current through the second common node, the second switch, the first controllable resistance, the first intermediate node, the first clock-controlled switch and the first output node and the first current through the first common node, the third switch, the second intermediate node, the second clock-controlled switch and the second output node when the input data signal in the clock cycle for the first and second switches has the logic low value, wherein the first and second currents have non-zero values which are different from one another, and wherein the amplifier is configured to measure voltages at the first and second common nodes and to control resistance values of the first and second controllable resistances so as to equalize the voltages at the first and second common nodes.

14. A digital-to-analogue converter as claimed in claim 13, wherein the clock cycles are defined by a clock signal or a plurality of time-interleaved clock signals, which are substantially sinusoidal clock signals.

15. A digital-to-analogue converter as claimed in claim 13, wherein either the first and second currents both have a positive magnitude or the first and second currents both have a negative magnitude.

16. An integrated circuit or an IC chip, comprising switching circuitry for use in a digital-to-analogue converter, the switching circuitry being operable based on an input data signal which alternates between having a logic high value and having a logic low value, and the switching circuitry comprising: first and second common nodes at which first and second currents are respectively received; first and second output nodes; first and second intermediate nodes; first and second clock-controlled switches; first and second controllable resistances; an amplifier; and a plurality of switches each connected to receive said input data signal or a data signal derived therefrom as an individual control signal of that switch, so that a signal level of the individual control signal received at a second switch of the plurality of switches is caused to change whenever a signal level of the individual control signal received at a first switch of the plurality of switches is caused to change, and a signal level of the individual control signal received at a fourth switch of the plurality of switches is caused to change whenever a signal level of the individual control signal received at a third switch of the plurality of switches is caused to change, the plurality of switches being connected and operable in each clock cycle of a series of clock cycles based on their respective control signals to direct the first current through the first common node, the first switch, the first intermediate node, the first clock-controlled switch and the first output node and the second current through the second common node, the fourth switch, the second controllable resistance, the second intermediate node, the second clock-controlled switch and the second output node when the input data signal in the clock cycle for the first and second switches has the logic high value, and to direct the second current through the second common node, the second switch, the first controllable resistance, the first intermediate node, the first clock-controlled switch and the first output node and the first current through the first common node, the third switch, the second intermediate node, the second clock-controlled switch and the second output node when the input data signal in the clock cycle for the first and second switches has the logic low value, wherein the first and second currents have non-zero values which are different from one another, and wherein the amplifier is configured to measure voltages at the first and second common nodes and to control resistance values of the first and second controllable resistances so as to equalize the voltages at the first and second common nodes.

17. An integrated circuit or an IC chip as claimed in claim 16, wherein the clock cycles are defined by a clock signal or a plurality of time-interleaved clock signals, which are substantially sinusoidal clock signals.

18. An integrated circuit or an IC chip as claimed in claim 16, wherein either the first and second currents both have a positive magnitude or the first and second currents both have a negative magnitude.

Description

(1) Reference will now be made, by way of example, to the accompanying drawings, of which:

(2) FIG. 1, as mentioned hereinabove, presents an overview of a previously considered DAC;

(3) FIG. 2, as mentioned hereinabove, presents an exemplary differential switching circuit suitable for use with the DAC of FIG. 1;

(4) FIG. 3, as mentioned hereinabove, presents a modified differential switching circuit;

(5) FIG. 4, as mentioned hereinabove, presents modified switch driver circuitry for use with the differential switching circuit of FIG. 3;

(6) FIGS. 5A and 5B, as mentioned hereinabove, present timing diagrams useful for understanding the operation of the circuitry of FIGS. 3 and 4;

(7) FIG. 6, as mentioned hereinabove, reproduces the first driver portion of FIG. 4 in simplified form, to enable a better understanding of identified problems;

(8) FIG. 7, as mentioned hereinabove, indicates that the inventors have considered driving the gates of the output switches with NMOS data-controlled switches rather than CMOS switches;

(9) FIG. 8 is a schematic diagram presenting a differential switching circuit which embodies the present invention;

(10) FIG. 9 presents an example 16 GHz, 4-phase clock signal;

(11) FIG. 10 is a schematic diagram presenting parts of a DAC comprising the differential switching circuit of FIG. 8;

(12) FIG. 11 shows waveforms for the clock signals CLK .sub.1 to .sub.4 in its upper graph, and partial waveforms for currents received at output nodes A and B of the FIG. 8 circuit in its lower graph;

(13) FIG. 12 is a schematic diagram corresponding to the FIG. 8 circuitry, but provided in reduced form for simplicity, and useful for understanding better operation of the FIG. 8 circuitry;

(14) FIG. 13 is a schematic diagram corresponding to the FIG. 8 circuitry, but provided in reduced form for simplicity, and useful for understanding possible use of a DC or data-switched bleed current;

(15) FIG. 14 is a schematic diagram presenting (in reduced form) a differential switching circuit which embodies the present invention;

(16) FIG. 15A presents a simplified schematic version of the FIG. 8 switching circuit;

(17) FIG. 15B presents a simplified schematic version of the FIG. 14 switching circuit;

(18) FIG. 16 presents a table useful for understanding operation of the FIG. 14 circuitry;

(19) FIG. 17 presents a table detailing five example input data waveforms numbered 1 to 5;

(20) FIG. 18 presents a table detailing five example input data waveforms numbered 6 to 10;

(21) FIG. 19 is a schematic diagram indicating that it would be possible to provide dummy (duplicate) nodes A.sub.CAL and B.sub.CAL which are not true output nodes but instead internal nodes used for calibration;

(22) FIGS. 20(a) and 20(b) show waveforms for the clock signals CLK .sub.1 to .sub.4, to indicate that such clock signals in practice have amplitude/common-mode errors and that the inventors have considered aligning the upper portions of those signals;

(23) FIG. 21(a) presents the four switches SW1 to SW4, FIG. 21(b) presents clock signals CLK 1 to 4, and FIG. 21(c) indicates schematically how such clock signals may be controlled to control such switches;

(24) FIG. 22 is a schematic diagram based on FIG. 21(c), but adapted to indicate schematically that Amplitude Level Control (ALC) may be performed;

(25) FIG. 23 presents an expanded version of the FIG. 21(c) circuitry, to indicate schematically how such ALC might be carried out in practice and to indicate that two techniques may be employed together;

(26) FIG. 24 presents a refinement of the circuitry shown in FIG. 21(c);

(27) FIG. 25 is a schematic diagram presenting example sampling circuitry 200 for use in an analogue-to-digital converter (ADC);

(28) FIG. 24 presents a refinement of the circuitry shown in FIG. 21(c);

(29) FIG. 25 is a schematic diagram presenting example sampling circuitry 200 for use in an analogue-to-digital converter (ADC);

(30) FIG. 26 is a schematic diagram of analogue-to-digital circuitry which comprises a sampler corresponding to the sampling circuitry shown in FIG. 25;

(31) FIG. 27 is a schematic diagram presenting parts of combined DAC and ADC circuitry;

(32) FIGS. 28(a)-28(d) contain a schematic diagram indicating that the same clock generation and distribution circuitry may be employed for different combinations of DAC and ADC circuitry;

(33) FIG. 29 presents four example driver configurations, labelled A to D, for use in understanding FIGS. 27 and 28(a)-28(d); and

(34) FIG. 30 presents a table, detailing possible combinations for Drivers A to D.

(35) FIG. 8 shows a differential switching circuit 50, which embodies the present invention.

(36) As for differential switching circuit 10 shown in FIG. 3, the circuitry comprises a common node CN (or tail node) to which a current source (or, once and for all, sink) is connected. Four transistors SW1 to SW4 are shown connected in parallel between the common node CN and a first output node A. Similarly, four transistors SW5 to SW8 are shown connected in parallel between the common node CN and a second output node B. These transistors SW1 to SW8 will be referred to as output switches hereafter, and correspond respectively to output switches S1 to S8 in FIG. 3. However, as will become apparent, there are significant differences between the differential switching circuit 50 and the differential switching circuit 10.

(37) In FIG. 8, the gates of the output switches SW1 to SW8 are driven directly by way of clock signals (which do not pass via data-controlled switches), although a buffer or decoupling capacitor may be provided along the clock paths to the gates (not shown). Importantly, the gates of those output switches are not driven by data-dependent signals in the way that output switches S1 to S8 in FIGS. 3 and 4 are.

(38) In FIG. 8, data-controlled switches D1 to D8 are provided in series connection with the output switches SW1 to SW8, respectively, enabling the clock signals to drive the transistor gates directly.

(39) This presents a significant advantage, as it moves the data-controlled switches away from the voltage-mode portion of the circuitry (i.e. controlling the gates of the output switches) to the current-mode portion, where they simply carry currents. It is advantageous to drive the gates of the output switches directly with clock signals as better control can be had of the signals which arrive at those gates, with fewer distortion sources (such as switched transistors) in the clock paths. It is to be recalled that the inventors identified the data-controlled switches in FIG. 4 as distortion contributors.

(40) Looking at FIG. 8, each output switch SW1 to SW8 effectively becomes one of a pair of series-connected switches (in this case, field-effect transistors). These switches may be implemented as NMOS field-effect transistors. The pairs including SW1 to SW4 are provided in parallel branches, and similarly the pairs including SW5 to SW8 are provided in parallel branches.

(41) Another significant difference between FIG. 8 and FIGS. 3 and 4 is that the clock signals CLK 1 to CLK 4 supplied to the output switches SW1 to SW8 are respective phases of a four-phase clock signal, as shown in FIG. 9. Clock signals CLK 1 to CLK 4 therefore correspond respectively to the first to fourth phases of a repeating series of four phases. Moreover, the clock signals are substantially sinusoidal. Effectively, four time-interleaved sinusoidal clock signals are provided.

(42) The overall operation of the FIG. 8 circuitry is somewhat similar to that in FIGS. 3 and 4, in that the output switches SW1 to SW8 and the data-controlled switches D1 to D8 are driven so as, in use, to steer current from the current source through the first output node A or the second output node B in dependence upon the value (digital 0 or 1) of the data signals DATA1 to DATA4.

(43) In order to achieve this, output switches SW1 and SW5 are provided with clock signal CLK 1, SW2 and SW6 are provided with clock signal CLK 2, SW3 and SW7 are provided with clock signal CLK 3, and SW4 and SW8 are provided with clock signal CLK 4. Moreover, data-controlled switches D1 and D5 are respectively provided with data signals DATA 1 and DATA 1, D2 and D6 are respectively provided with DATA 2 and DATA 2, D3 and D7 are respectively provided with DATA 3 and DATA 3, and D4 and D8 are respectively provided with DATA 4 and DATA 4.

(44) The effect of the 4-phase clock signal is that either output switch SW1 or SW5 is switched on in a first clock cycle or phase (1), dependent on the value of the data signal DATA 1. Similarly, dependent on data, SW2 or SW6 switches on in a second clock cycle or phase (2), SW3 or SW7 switches on in a third clock cycle or phase (3) and SW4 or SW8 switches on in a fourth clock cycle or phase (4). The output switches in FIG. 8 are NMOS transistors, and as such turn on in the +ve peak portions of the relevant clock signals.

(45) Accordingly, for each clock cycle, if the value of the data signal concerned is 1 the current I.sub.TAIL is steered through node A and if it is zero through node B. Moreover, as before, in each cycle one series-connected transistor pair turns on and one turns off, irrespective of the data. In each cycle, two output-switch transistors turn on and two turn off, irrespective of the data.

(46) Given the example 16 GHz, 4-phase clock signal depicted in FIG. 9, this operation leads to an overall sample rate of 64 Gs/s, which is significantly faster than the example sample rate of 12 Gs/s mentioned in connection with FIG. 3.

(47) Output nodes A and B are connected to the output switches via respective output cascodes as indicated in FIG. 8. A differential output signal of the switching circuitry may thus be measured between the two output terminals, as a current signal or as a voltage signal by way of terminating resistors (not shown in FIG. 8, but understood by reference to FIG. 1).

(48) Looking at each pair of series-connected switches in FIG. 8 as a single unit, in any particular cycle or state 1 is on and 7 are off. Looking at the upper switches (the output switches) of each pair, in any state 2 are on and 6 are off. Looking at the lower switches (the data-controlled switches) of each pair, in any state (ignoring transitional changes of the data values, which in an ideal case would be instantaneous) 4 are on and 4 are off.

(49) Moreover, looking at each pair as a single unit, from one cycle to the next 1 turns on and 1 turns off. Looking at the upper switches (the output switches) of each pair, from one cycle to the next 2 turn on and 2 turn off. Looking at the lower switches (the data-controlled switches) of each pair, from one cycle to the next either the same number turn on as turn off (if the data changes) or the switches retain their states (if the data stays the same).

(50) Looking further at FIG. 8, the circuitry portion comprising output switches SW1 to SW8 may be referred to as clock-controlled circuitry 52, and the circuitry portion comprising data-controlled switches D1 to D8 may be referred to as data-controlled circuitry 54. It will be appreciated that the switches in the clock-controlled circuitry 52 are controlled by clock signals and not by data signals, and as such they may be considered data-independent. Conversely, the switches in the data-controlled circuitry 54 are controlled by data signals and not by clock signals, and as such they may be considered clock-independent. For example, the clock signals CLK 1 to CLK 4 may be supplied continuously (i.e. during active operation) to the clock-controlled circuitry 52 and specifically to the gates of the output switches SW1 to SW8, which is not the case in FIGS. 3 and 4 (given the intervening data-controlled switches).

(51) Incidentally, another difference between the FIG. 8 circuitry and that of FIGS. 3 and 4 is that the data signals are supplied directly to the gates of the data-controlled switches D1 to D8, albeit perhaps via a buffer or decoupling capacitor (not shown). That is, the mask signals MASK1 to MASK4 employed in FIG. 4 are not required in connection with the FIG. 8 circuitry, given that the four-phase clock signal (comprising CLK 1 to CLK 4) is employed. This leads to an advantageous reduction in the required circuitry.

(52) To provide some context, FIG. 10 shows parts of a DAC 60 comprising the differential switching circuit 50. The differential switching circuitry 50 is shown schematically in the upper-right corner, comprising the clock-controlled circuitry 52 and the data-controlled circuitry 54. Also shown is a clock generator 62 configured to generate the clock signals CLK 1 to CLK 4 and supply them to the differential switching circuit 50.

(53) It is incidentally noted that FIG. 8 represents differential switching circuitry 50, in which differential input data signals are employed (i.e. employing four sampling switches SW1 to SW4, and a complementary set SW5 to SW8). For simplicity, FIG. 10 is presented with single-ended input data signals (or with only one half of corresponding differential signals shown). FIG. 10 may be interpreted to apply to differential switching circuitry 50, with the input data signals being differential signals, and with SW1 to SW8 being employed as in FIG. 8.

(54) As a running example, a desired DAC sample rate of 64 Gs/s is assumed, and the data signals DATA 1 to DATA 4 input to the differential switching circuit 50 are 16 GHz (i.e. time-interleaved) data signals.

(55) Three stages of multiplexing/retiming 72, 74 and 76 are also shown by way of example, in order to input at the first multiplexer/retiming circuit 72 a parallel set of 64 1 GHz data signals if retiming is carried out (or e.g. 128 500 MHz data signals if multiplexing is carried out), and output 64 1 GHz data signals to the second multiplexer 74, which in turn outputs 16 4 GHz signals to the third and last multiplexer 76, which in turn outputs the data signals DATA 1 to DATA 4 as 4 16 GHz signals as above. For simplicity, although unit 72 may carry out retiming or multiplexing, it will be referred to as a multiplexer below.

(56) Also shown are three stages of clock generation 80, 82, 84, in order to take the input clock signals CLK 1 to CLK 4 and generate in turn the clock signals required by the three stages of multiplexing 72, 74 and 76, as indicated in FIG. 10.

(57) It is to be remembered that the differential switching circuit 50 is representative of a single segment or slice in the overall DAC, for example by looking back to FIG. 1. Thus, any coding (e.g. thermometer-coding) of an ultimate input digital signal is assumed to have occurred upstream of the digital signals input in FIG. 10, such that those input digital signals input are only those intended for the segment or slice shown.

(58) The overall DAC would have further slices or segments, each with their own stages of multiplexing 72, 74 and 76. Of course, the clock generation circuitry 62, 80, 82 and 84 may be shared between the segments (or separately provided, at least in part).

(59) The analogue outputs of the various slices or segments may be combined to create a single analogue output of the overall DAC, for example in a similar manner as to in FIG. 1. In another example, seven segments could be provided to produce the outputs for the 3 MSBs of an 8-bit DAC (with thermometer-encoding), and five segments (in which their outputs are binary weighted) could be provided to produce the outputs for the 5 LSBs. Other variations would of course be possible. For example, an impedance ladder could be employed, as disclosed in EP-A1-2019490.

(60) FIG. 11 shows more waveforms for the clock signals CLK .sub.1 to .sub.4 in the upper graph, and partial waveforms for the currents received at output nodes A and B, labelled as IOUT.sub.A and IOUT.sub.B, in the lower graph, for use in better understanding the operation of differential switching circuit 50 of FIG. 8.

(61) As mentioned above, clock signals CLK .sub.1 to .sub.4 are time-interleaved raised (substantially) cosine waveforms and are 90 out of phase with one another. The clock signals shown are sinusoidal, but need not be strictly-perfect sinusoids. As will become apparent, in the present embodiment the shape of the waveforms is more important in the uppermost part than towards the bottom.

(62) As an aside, the number of clock signals shown in FIGS. 9 and 11 is related to the number of parallel paths to each of nodes A and B in FIG. 8. Since there are four parallel paths to each of nodes A and B in FIG. 8, four time-interleaved clock signals are provided, 90 out of phase with one another. It is envisaged that where X parallel paths to each of nodes A and B are provided, X time-interleaved clock signals may be provided, (360/X) out of phase with one another. In this case, X is an integer greater than or equal to 2, and preferably greater than or equal to 3, and more preferably equal to 4.

(63) Returning to FIG. 11, for the benefit of further explanation clock signal .sub.4 is highlighted in bold.

(64) Clock signals CLK .sub.1 to .sub.4 control the gates of output switches SW1 to SW8, as already described in connection with FIG. 2. Accordingly, the output-switch pairs (where the pairs are SW1/SW5, SW2/SW6, SW3/SW7, SW4/SW8) are turned on and then off in sequence, such that as one of them is turning off the next in sequence is turning on, and such that when one of them is turned fully on the others are substantially turned off. As mentioned before, which switch of such an output-switch pair carries a current pulse when the pair is turned on is dependent on the data signal (of DATA 1 to DATA 4) concerned.

(65) Because substantially all current passing through the common node via switches SW1 to SW8 must equal current I.sub.TAIL, then the sum of currents flowing through nodes A and B at any time must be substantially equal to I.sub.TAIL. The effect of the data-controlled switches D1 to D8 mentioned above is therefore that current I.sub.TAIL is steered to pass through one switch from each output-switch pair in the sequence in which those output-switch pairs are turned on and off, i.e. such that as one of the output-switch pairs is turning off and thus one of its output switches starts to carry less of I.sub.TAIL, the next output-switch pair in sequence is turning on and thus one of its output switches starts to carry more of I.sub.TAIL, and such that when one of the output-switch pairs is turned fully on, one of its output switches carries substantially all of I.sub.TAIL because the other output switch of that pair has its series-connected data-controlled switch substantially turned off and because the output switches of the other output-switch pairs are substantially turned off.

(66) This effect is shown in the lower graph of FIG. 11. Only three output currents for clocks CLK .sub.3, .sub.4 and .sub.1 are shown for simplicity, however the pattern of waveforms shown continues with the successive peaks being for IOUT.sub.A or IOUT.sub.B dependent on the data. In the present example, it is assumed that the data sequence is DATA 3=0 (such that the current passes to node B), DATA 4=1 (such that the current passes to node A), and DATA 1=0 (such that the current passes to node B). For comparison with the upper graph of clock signals, the waveform for the output current corresponding to clock signal .sub.4 is highlighted in bold.

(67) In order to gain a better understanding of the lower graph in FIG. 11, three points, 90, 92 and 94 are indicated on waveform .sub.4 and a corresponding three points 100, 102 and 104 are indicated on the corresponding current waveform.

(68) At point 90, waveform CLK .sub.4 is at its peak value, i.e. at V.sub.DD, and the other clock signals CLK .sub.1 to .sub.3 are significantly below their peak value. Accordingly, (given DATA 4=1) switches SW4 and SW8 are fully on with D4 on and D8 off, and at least the other output switches (SW1 to SW3 and SW5 to SW7) are substantially off. Therefore, at the corresponding point 100, current IOUT.sub.A is equal to I.sub.TAIL and current IOUT.sub.B is substantially equal to zero.

(69) At point 92, which precedes point 90, waveform .sub.4 is rising towards its peak value but has not yet reached its peak value. Also, at point 79, waveform .sub.3 is falling from its peak value. Importantly, at point 92 clock signals .sub.3 and .sub.4 have equal values. Therefore switches SW3 and SW4, and also SW7 and SW8, are on to the same extent as one another, because their source terminals are connected together. At point 92, clock signals .sub.1 and .sub.2 are also equal to one another and are sufficiently low to ensure that switches SW1 and SW2, and also SW5 and SW6, are off. Thus, at this point in time, half of current I.sub.TAIL flows through switches SW4 and D4 (given DATA 4=1) and half of it flows through switches SW7 and D7 (given DATA 3=0), as indicated by point 102, such that IOUT.sub.B=IOUT.sub.A=(I.sub.TAIL)/2.

(70) Point 94 is equivalent to point 92, except that at this point it is switches SW4 and SW1, and also SW8 and SW5, that are on. Therefore, at corresponding point 104, IOUT.sub.A=IOUT.sub.B=(I.sub.TAIL)/2.

(71) It will therefore be appreciated that the three points for each current waveform (e.g. points 100, 102 and 104 for current waveform IOUT.sub.A in FIG. 11) are fixed or defined in time relative to the clock waveforms and in magnitude relative to the current I.sub.TAIL. That is, taking current IOUT.sub.A as an example, at point 100 the current is equal to I.sub.TAIL and at points 102 and 104 the current is equal to half I.sub.TAIL. The location of points 100, 102 and 104 is fixed relative to the clock signals .sub.1 to .sub.4. The same is true for the subsequent current signal pulses or charge packets, which may be for IOUT.sub.A or IOUT.sub.B dependent on the data. The focus on points 90, 92 and 94 demonstrates that for the present embodiment the upper part of the clock signals is important, and that the lower parts are less important (such that, for example, the precise shape of the lower parts is not strictly critical). The significance of this point will become apparent later.

(72) Thus, the series of current pulses of waveforms (for IOUT.sub.A or IOUT.sub.B dependent on the data) are all of the same shape, and that shape is defined by the positive peak of the sinewave clock signals.

(73) This operation has considerable benefits.

(74) Because the pulses all have the same raised-cosine shape, defined by the sinewave clock waveforms, the frequency response/roll-off is thereby defined mathematically by the cosine curve and as a result the analogue bandwidth from the input I.sub.TAIL to the output node A or B is very high, typically greater than 300 GHz. Furthermore, the voltage level at the tail node or common node CN in the circuitry does not fluctuate much during operation. By way of explanation, in FIG. 8 the switches SW1 to SW8 and D1 to D8 are NMOS switches, operated in the saturated region, with the source terminals of D1 to D8 tied together to form the tail node concerned. Thus, those switches operate as cascodes with a low input impedance and a high output impedance.

(75) Because the voltage level at the tail nodes does not move much, those nodes may be considered to be virtual grounds, and have a reduced sensitivity to parasitic capacitances at those tail nodes. The circuitry of FIG. 8 is a fast analogue circuit carrying current pulses of a defined shape. The circuitry thus has a high bandwidth that is known, repeatable, accurate and constant. This known bandwidth may thus be compensated for with a filter, for example digitally (e.g. with an FIR filter on the input data).

(76) Moreover, it is the actual current I.sub.TAIL that is steered or routed through the circuitry (without copying, for example by a current mirror). All of the current I.sub.TAIL passes via the output nodes. The direction of flow of conventional current may be from output to input, but the principles are the same for current flowing from input to output, and indeed the graphs of currents IOUT.sub.A/B are shown as positive values (with the direction of those currents shown, e.g. in FIG. 11, as from output to input) to aid conceptual understanding of the operation of the circuitry. In summary, if both of the output currents are summed together, the result would be the same as I.sub.TAIL.

(77) Assuming that the clock signals .sub.1 to .sub.4 are perfect, i.e. free of amplitude noise and phase noise (jitter), then any errors are mainly (i.e. ignoring insignificant signal-dependent errors) due to mismatches between the switching transistors (and such mismatches are dealt with later).

(78) Because four time-interleaved sinusoidal clock signals (in this case, raised cosines) are employed in the present embodiment, the 25% duty-cycle pulses required to drive the corresponding four switches for each node (e.g. switches SW1 to SW4 for node A, and SW5 to SW8 for node B, in FIG. 8) are formed even though the clock signals themselves (being sinusoids) naturally have a 50% duty cycle. That is, for an X-way split of the input current signal (X=4, above), it is possible to use 50% duty-cycle sinusoidal clock signals to produce 100/X % duty-cycle pulses. In contrast, if switched logic-level (hard-switched) clock signals were employed, as in FIGS. 5A, 5B and 6, it would be necessary to use clock signals themselves having a 100/X % (25%, for X=4) duty cycle to produce 100/X % (25%, for X=4) duty-cycle pulses. Therefore, the present embodiment is advantageous, particularly when considering high-frequency operation, as 50% duty-cycle clock signals may be employed (even when X=3 or more).

(79) Yet a further advantage of the differential switching circuit 50 is that the gates of the switches SW1 to SW8 may be driven directly with clock signals, even without requiring an intermediate buffer. This is because the present circuitry is configured to accept sinusoidal clock signals. Such direct driving may include intermediate AC coupling, e.g. via a capacitor. With such direct driving, the gate capacitances of the switches SW1 to SW8 of the differential switching circuit 50 can be included in VCO design (where the VCO creates the clock signals CLK .sub.1 to .sub.4) as being part of necessary capacitance within the VCO. Thus, the gate capacitances are effectively absorbed within the VCO, such that the differential switching circuit 50 operates as if there were zero gate capacitance. Thus, switching delays due to gate capacitances are effectively removed. Furthermore, the ability to not employ buffers to generate square (i.e. pulsed or switched-logic) waves allows associated noise and delay mismatch to be avoided. It is envisaged, however, that buffers may be employed in some embodiments, because the added loading capacitance of all the switches in all the segments of an overall DAC may be too large for a VCO (clock generator) to drive.

(80) Returning to FIG. 11, it will be appreciated that in order to determine whether any particular current pulse in the lower half of the Figure is of IOUT.sub.A or IOUT.sub.B the data value concerned should be stable in time to create the pulse concerned. For example, in the case of the bold current signal of FIG. 11, which corresponds to clock signal CLK .sub.4, the relevant data signal DATA 4 should be stable at least over the period of time spanning the five vertical dashed lines. For example, data signal DATA 4 could be arranged to change state at or approximately at the troughs (negative peaks) of clock signal CLK .sub.4. Similarly, each of data signals DATA 1 to DATA 3 could be arranged to change state at or approximately at the troughs of their respective clock signals CLK .sub.1 to .sub.3. Thus, in the running example of 16 GHz clock signals as in FIGS. 9 and 10, the data signals DATA 1 to DATA 4 may also be 16 GHz signals as in FIG. 10 configured to change state at or approximately at the troughs of their respective clock signals.

(81) The inventors have further considered the operation of the series-connected switch pairs (e.g. SW1 and D1) in the FIG. 8 circuitry, and identified the potential for improvement. FIG. 12 is a schematic diagram corresponding to the FIG. 8 circuitry, but provided in reduced form for simplicity. Thus, only D1 of the data-controlled switches D1 to D8 is shown explicitly (although it is assumed that they are all present).

(82) To help with the explanation, a parasitic capacitance 110 is indicated as present at the intermediate node IN between the switches of each series-connected pair. Effectively, each intermediate node IN floats (in terms of its voltage potential) when the data-controlled switch D concerned is off (the clock signals continuing to be supplied to the output switch SW concerned irrespective of data). As such, the voltages at the intermediate nodes IN have a memory, i.e. they depend on what the data was in the previous series of cycles. This leads to some data-dependent distortion in the DAC output signal.

(83) The inventors have considered how to provide to an extent a memory-less voltage at the intermediate nodes IN, for example with the voltage level having only two possible states (e.g. x if the data-controlled switch was previously on and y if it was previously off).

(84) As indicated in FIG. 13 (in a reduced version for simplicity), one possible solution the inventors have considered is to provide a DC or data-switched bleed current at the intermediate nodes IN. This is only indicated in respect of switch SW5 in FIG. 13, as the output switch assigned to the same phase as switch SW1. For example, when DATA1=1, it may be that data-controlled switch D1 is ON and D5 is OFF. When D5 is OFF, its intermediate node IN would float in the absence of the bleed current, however with the bleed current this floating problem may be avoided. A problem with DC bleed is however power wastage, i.e. wasted current. There is also the need to provide bigger switches to carry the larger currents needed. A problem with a data-switched bleed current is a sensitivity to the data signal (i.e. data-dependent distortion in the DAC output).

(85) Posed with the above issues, the inventors have devised an improved differential switching circuit 120 as indicated in FIG. 14 in reduced form. The circuitry of FIG. 14 is essentially the same as that in FIG. 8 except that for each output switch (SW1 to SW8) two data-controlled switches are provided in parallel, leading from the intermediate node to different tail nodes. One of the tail nodes is connected to a big current source I.sub.BIG and the other to a small current source I.sub.SMALL. Big and small in this context are relative to one another. For example, I.sub.BIG may be equal to 1.5 l and I.sub.SMALL equal to 0.5 l. Other ratios of big:small are of course possible.

(86) The pair of data-controlled switches per output switch is only shown in FIG. 14 in respect of output switches SW1 and SW5 for simplicity, those switches both being associated to phase 1 (CLK .sub.1) however it will be understood that for each of the output switches SW1 to SW8, one of its data-controlled switches is connected to the tail or common node for I.sub.BIG and the other to the tail or common node for I.sub.SMALL. Thus, although output switches SW2 to SW4 and SW6 to SW8 are not shown explicitly in FIG. 14, it is understood that they are present, each connected to two data-controlled switches in a similar fashion to SW1 and SW8.

(87) Therefore, for output switch SW1 there is a series-connected data-controlled switch D1B connected to the common node CNB for I.sub.BIG and a series-connected data-controlled switch D1S connected to the common node CNS for I.sub.SMALL. The pair of data-controlled switches connected to the same output switches are effectively in parallel with one another. Here, the suffix B relates to BIG and the suffix S relates to SMALL. This is shown in FIG. 14 explicitly.

(88) Similarly, and for completeness, for output switch SW2 (not shown) there is a series-connected data-controlled switch D2B connected to the common node CNB for I.sub.BIG and a series-connected data-controlled switch D2S connected to the common node CNS for I.sub.SMALL, for output switch SW3 (not shown) there is a series-connected data-controlled switch D3B connected to the common node CNB for I.sub.BIG and a series-connected data-controlled switch D3S connected to the common node CNS for I.sub.SMALL, for output switch SW4 (not shown) there is a series-connected data-controlled switch D4B connected to the common node CNB for I.sub.BIG and a series-connected data-controlled switch D4S connected to the common node CNS for I.sub.SMALL, for output switch SW5 (as shown in FIG. 14) there is a series-connected data-controlled switch D5B connected to the common node CNB for I.sub.BIG and a series-connected data-controlled switch D5S connected to the common node CNS for I.sub.SMALL, for output switch SW6 (not shown) there is a series-connected data-controlled switch D6B connected to the common node CNB for I.sub.BIG and a series-connected data-controlled switch D6S connected to the common node CNS for I.sub.SMALL, for output switch SW7 (not shown) there is a series-connected data-controlled switch D7B connected to the common node CNB for I.sub.BIG and a series-connected data-controlled switch D7S connected to the common node CNS for I.sub.SMALL, and for output switch SW8 (not shown) there is a series-connected data-controlled switch D8B connected to the common node CNB for I.sub.BIG and a series-connected data-controlled switch D8S connected to the common node CNS for I.sub.SMALL.

(89) In each pair of data-controlled switches connected to the same output switch (e.g. D1B and D1S), one is controlled by the data signal concerned and the other by the complementary data signal. For example, D1B is controlled by DATA 1 and D1S is controlled by DATA 1. Thus, one of the two is always on (irrespective of the data) and as such the intermediate node IN never (except transiently, when the data changes) floats. In particular, the IN is always connected to one of the two tail nodes before and after the output switch concerned is turned from off to on to off again. If the two tail voltages are the same and the data switches change when the clock-controlled switch is off this has no effect on the output and does not introduce any memory effect.

(90) For completeness, the other connections for FIG. 14 are indicated in table 2 below.

(91) Each row in the table corresponds to a different one of the output switches, as indicated in the second column. In each of the second to fourth columns, each entry specifies the switch concerned (e.g. SW1) and then in square brackets the signal applied to that switch (e.g. CLK .sub.1).

(92) In each row, the three switches comprise an output switch (e.g. SW1), and two data-controlled switches (e.g. D1B and D1S) each of which is series-connected with that output switch.

(93) The first column indicates the relevant phase for reach row, of phases 1 to 4.

(94) TABLE-US-00002 TABLE 2 Data-Controlled Data-Controlled Switch Switch Phase Output Switch (BIG) (SMALL) 1 SW1 [CLK .sub.1] D1B [DATA 1] D1S [DATA 1] 2 SW2 [CLK .sub.2] D2B [DATA 2] D2S [DATA2] 3 SW3 [CLK .sub.3] D3B [DATA 3] D3S [DATA 3] 4 SW4 [CLK .sub.4] D4B [DATA 4] D4S [DATA4] 1 SW5 [CLK .sub.1] D5B [DATA1] D5S [DATA 1] 2 SW6 [CLK .sub.2] D6B [DATA2] D6S [DATA 2] 3 SW7 [CLK .sub.3] D7B [DATA 3] D7S [DATA 3] 4 SW8 [CLK .sub.4] D8B [DATA 4] D8S [DATA 4]

(95) Returning to FIG. 14, additional switches R1 to R8 (transistors) in series with the data-controlled switches connected to the tail node for I.sub.SMALL are provided and controlled (effectively as voltage-controlled resistorsMOS operating in the linear region) so that the two tail node voltages V.sub.TAILS and V.sub.TAILB are kept substantially equal, at around 0V. Although only R1 and R5 are shown explicitly in FIG. 14 (connected in series with D1S and D5S, respectively), it will be understood that R2 to R4 and R6 to R8 are also provided, in series with D2S to D4S and D6S to D8S, respectively. An amplifier measuring the tail voltages V.sub.TAILS and V.sub.TAILB (as indicated at the right-hand side of FIG. 14) and controlling the additional transistors so as to tend to equalise the tail voltages is shown in FIG. 14.

(96) It is desirable for both tail node voltages to be the same, so that the intermediate nodes IN always goes back down to the same (tail node) voltage at the end of each cycle. For example, the data changes when the output switches SW concerned are off, so an intermediate node IN at the point when the data changes goes from one tail node to the other. During a current pulse for a particular output switch SW, i.e. when the output switch SW turns from off to on to off, the tail/common node CN and intermediate node IN voltages rise and fall again. The rise is higher for Ismall since less current is flowing in the output switch, so its gate-source voltage is smaller. The resistive switches R are added to push the small tail node voltage V.sub.TAILS down so that it has the same voltage as the big tail node voltage V.sub.TAIL B. The IN voltage at the end of a current pulse is the same as at the beginning, so no net current can flow into the parasitic capacitance; with Ibig the node goes from V.sub.TAILB to a (lower) voltage and back to V.sub.TAILB, with Ismall the node goes from V.sub.TAILS to a (higher) voltage and back to V.sub.TAILSin other words there is no sample-to-sample memory or net charge gain/loss into the capacitance.

(97) It will therefore be appreciated that the circuitry of FIG. 14 functions somewhat similarly to that in FIG. 8, where, in any one cycle or phase, a current pulse flows through one of output nodes A and B and no pulse flows through the other. The important difference is that in FIG. 14, in any one cycle or phase, a big current pulse flows through one of output nodes A and B (dependent on the data) and a small pulse flows through the other. Thus, as indicated at the upper middle of FIG. 14, the output between differential terminals A and B would be the difference (shown as shaded) between the big and small pulses. It is this difference which would be considered the true output of the DAC (in this case, of the segment/slice shown).

(98) With this in mind, it may be appreciated that the circuitry portion comprising output switches SW1 to SW8 may be referred to as clock-controlled circuitry 52, as in FIG. 8. The circuitry portion comprising data-controlled switches D1B to D8B and D1S to D8S, as well as additional switches R1 to R8, may be referred to as data-controlled circuitry 154 (which is different from data-controlled circuitry 54 in FIG. 8). Of course, it is to be remembered that FIG. 14 like FIG. 8 represents a single DAC slice, and as such the overall DAC would comprise many such slices.

(99) The FIG. 14 circuitry has several advantages (some of which also apply to FIG. 8, as will be apparent), as follows.

(100) Use of first and second differently-sized current sources, here labelled I.sub.BIG and I.sub.SMALL, advantageously reduces or removes voltage memory at the intermediate nodes IN without requiring DC bleed current (per output switch). The FIG. 14 circuitry ensures that there is never any undefined, floating, node. Although I.sub.SMALL acts as a data-switched bleed current in one sense, it has the same switching accuracy as the main tail current I.sub.BIG and thus does not add significant noise into the overall circuitry.

(101) The data-controlled switches D1B to D8B and D1S to D8S are on the quiet tail or common nodes. Those nodes are at approximately 0V, allowing the data-controlled switches to become strong on under control of the data. The tail nodes may be equalised as shown in FIG. 14, using an amplifier which measures the two tail nodes and in turn controls the additional switches R1 to R8. The additional switches R1 to R8 may be controlled in parallel by the same amplifier, as in FIG. 14, or may be individually controlled. In one embodiment, R1 to R8 within one segment/slice will be controlled together, because it may be difficult/impossible to separate out their individual effect on Vtails. Each segment (of an overall DAC) could have its own control voltage (controlling R1 to R8) or there could be a common voltage for all segments, depending on factors such as the accuracy of the measurement circuit (mismatch between segments), and relative ease of layout or routing (space for one loop per segment vs. ease of routing a common control voltage).

(102) The output switches SW1 to SW8 can be controlled directly by sinewave or sinusoidal (e.g. not shaped switched logic) clock signals. This is advantageous for very-high-frequency operationother shapes of clock signal would be harder to produce accurately.

(103) The clock voltages applied to the output switches SW1 to SW8 can be big as there are no intermediate switches. That is, the clock paths to the output switches SW1 to SW8 are cleared of potential discrete distortion sources (e.g. other switches). As such, the impact of V.sub.TH variations in the data-controlled switches D1 to D8, D1B to D8B and D1S to D8S is removed or lessened.

(104) The data-controlled switches D1 to D8, D1B to D8B and D1S to D8S can be implemented in the same way as the output switches SW1 to SW8, e.g. as 0.9V transistors. This is advantageous as it renders the data-controlled switches as the same high-speed transistors (low resistance, low capacitance) as the output switches, so that there are no longer any speed limitations to the circuit operation (beyond those of the high-speed transistors themselves). The NMOS data-controlled switches in FIG. 7, for example, are slower (higher resistance, higher capacitance) high-voltage transistors (thicker oxide, longer gate length) which slow the circuit down, add distortion to clocks (non-constant Ron), and increase capacitive load on clocks (difficult to drive).

(105) As mentioned above, even if clock signals .sub.1 to .sub.4 were perfect, i.e. free of amplitude noise and phase noise (jitter), errors may occur due to mismatches between the switching transistors, i.e. the output switches. Such mismatches will now be considered further. In particular, a calibration technique for use in a DAC corresponding to FIG. 8 or 14 will now be considered.

(106) In order to appreciate the calibration technique better, a simplified version of switching circuit 50 is presented in FIG. 15A, in which the data-controlled circuitry 54 is shown in reduced form as connected to current source (or sink) I.sub.TAIL. Similarly, a simplified version of switching circuit 120 is presented in FIG. 15B, in which the data-controlled circuitry 154 is shown in reduced form as connected to current sources (or sinks) I.sub.BIG and I.sub.SMALL.

(107) It is recalled that the effect of the four-phase clock signal is that output switches (transistors) SW1 and SW5 are on in a first clock cycle or phase (when 1 is around its peak), SW2 and SW6 are on in a second clock cycle (when 2 is around its peak), SW3 and SW7 are on in a third clock cycle (when 3 is around its peak) and SW4 and SW8 are on in a fourth clock cycle (when 4 is around its peak). In any such clock cycle or phase, and in the case of FIGS. 14 and 15B, which of the two transistors that are on (e.g. SW1 and SW5) carries the big current pulse due to I.sub.BIG and which carries the small current pulse due to I.sub.SMALL, is dependent upon the data. This is indicated in FIG. 16. FIG. 16 may also be understood to apply to FIGS. 8 and 15A, where I.sub.BIG is replaced with I.sub.TAIL, and where I.sub.SMALL is replaced with Zero Current.

(108) The present calibration technique is particularly advantageous in the case of the circuitry of FIGS. 15A and 15B, where the clock signals are directly connected to the gates of transistors SW1 to SW8, as it is undesirable to disconnect or stop those clock signals to perform calibration (for example because the circuits to do this would consume power and add delay and mismatch). However, it should be understood that the present calibration technique is also advantageous in a case where it may be more acceptable to disconnect and/or stop the clock signals, for example in the case of FIGS. 3 and 4 where data-controlled switches are provided at the gates of switches S1 to S8 (corresponding to SW1 to SW8).

(109) The general principle of the present technique may be appreciated with reference to FIGS. 17 and 18, which are provided in connection with the circuitry of FIGS. 14 and 15B by way of example. The technique involves applying specific data waveforms, in this example to the data-controlled circuitry 154, and examining output waveforms at one or both of nodes A and B.

(110) FIG. 17 considers five example input data waveforms numbered 1 to 5. Waveform 1 is a repeating data pattern 0000. This corresponds to a repeating pattern of DATA 1=0, DATA 2=0, DATA 3=0 and DATA 4=0. As such, the pulses experienced successively at switches SW1 to SW4 would be S, S, S, S (where S means small), as will be apparent from FIG. 16. Not shown in FIG. 17 is that the corresponding pulses experienced successively at switches SW5 to SW8 would be B, B, B, B (where B means big), although this will also be apparent from FIG. 16.

(111) A waveform experienced at output node A is indicated schematically for waveform 1, for two cycles of the repeating data pattern concerned. That is, a series of 8 small current pulses is shown. Also shown by way of a dashed horizontal line is a DC average voltage level which might be obtained at node A for example by low-pass filtering (LPF). A slow ADC could for example be used to perform such low-pass filtering. This DC average voltage level is given the label REFA, and is taken as a reference voltage for node A (i.e. switches SW1 to SW4).

(112) Waveform 2 is a repeating data pattern 1000 and produces pulses at transistors (switches) SW1 to SW4 as indicated in FIG. 17, namely a repeating pattern B, S, S, S. A DC average voltage level may also be obtained at output node A as indicated in FIG. 17, and a voltage difference V between this level and REFA may be taken as an indication of the gain of the switch SW1.

(113) In a similar manner, waveforms 3 to 5 may be employed to obtain voltage differences indicative of the gains of switches SW2 to SW4, respectively, as indicated in FIG. 17.

(114) FIG. 18 shows waveforms 6 to 10, which may be employed to obtain voltage level REFB and voltage differences indicative of the gains of switches SW5 to SW8, by examining waveforms experienced at output node B. Since the use of waveforms 6 to 10 is similar to the use of waveforms 1 to 5, duplicate description is omitted. Suffice to say that waveform 6 provides a voltage level given the label REFB, and is taken as a reference voltage for node B (i.e. switches SW5 to SW8). Waveforms 7 to 10 may be employed to obtain voltage differences indicative of the gains of switches SW5 to SW8, respectively, as indicated in FIG. 18.

(115) As will be appreciated, the above-described technique enables voltage differences indicative of the gains of each of the transistors SW1 to SW8 to be obtained. Such voltages could therefore be used to, for example, adjust the bulk voltages (e.g. bulk-source voltages) of the individual transistors SW1 to SW8 to equalise their gains and thus calibrate the circuitry (e.g. to take account of V.sub.TH differences between the switches (field-effect transistors)). For example, a DAC may be provided per switch SW1 to SW8, to provide its bulk voltage depending on a controlled digital input.

(116) Given that this technique uses particular input data waveforms as exemplified in FIGS. 17 and 18, it could be run at startup for the overall DAC but not readily during runtime when real data is supplied. Moreover, the FIG. 15B circuitry represents a single DAC slice and as such the technique should be performed per DAC slice on startup.

(117) Importantly, the present technique can be used to provide an input data signal to an overall DAC which has several such DAC slices, which signal targets the slices one by one so that they can be calibrated one by one. For example, such a signal may cycle through the slices one by one, and when one slice is under calibration it receives its set of different input data waveforms while the other slices receive in parallel a set of dummy waveforms (for which each waveform is the same). In this way, the output nodes of the overall DAC can be used to take the voltage measurements, since when one slice is under calibration and gives different voltages for its different input data waveforms, the other slices will contribute to the output voltages in the same way for each waveform of the dummy set (such that their contributions will cancel out). Thus, advantageously, it may be possible to calibrate such an overall DAC at startup by supplying the input data waveform and taking measurements at the output nodes, without needing to switch in or out particular slices.

(118) Incidentally, although it has been discussed above that the waveforms experienced at output nodes A and B may be examined during operation of the present technique, it would be possible to provide dummy (duplicate) nodes A.sub.CAL and B.sub.CAL which are not true output nodes but instead internal nodes used for calibration. See for example FIG. 19, where a dummy-node arrangement 160 comprising a dummy node A.sub.CAL is shown. Such dummy nodes could be switched in (e.g. using cascodes 162) for the purpose of performing the present technique, as also indicated in dummy-node arrangement 160. Moreover, this could enable the calibration to be carried out in parallel, i.e. with each slice having its own dummy output on each side to enable the slices to be calibrated in parallel. This however has the disadvantage of having to add circuits to switch the output current between the main outputs and the dummy outputs, which adds delay and reduces bandwidth. As such, for particular embodiments it may be better not to employ such dummy-node arrangements per slice and instead to employ the main DAC output nodes A and B to take measurements.

(119) It would also be possible in theory to measure voltages at the tail nodes rather than at the output nodes, again enabling the calibration to be carried out in parallel, i.e. with each slice having its voltage-measurement circuitry to enable the slices to be calibrated in parallel. In each phase or cycle, the tail node voltages rise and then fall again (as the output switch goes off to on to off). When the output switches are correctly calibrated (e.g. by bulk-voltage control), the rise and fall of the tail node voltages should be the same in each phase.

(120) As mentioned above, although the above technique has been described mainly using the I.sub.BIG/I.sub.SMALL pulses of FIGS. 14 and 15B, the technique may also be employed where only one current source is provided (see e.g. FIGS. 8 and 15A) in which case there would be pulse P and no-pulse NP rather than big pulse B and small pulse S in FIGS. 17 and 18. Similarly, the technique could be applied with the circuitry of FIGS. 3 and 4, in which case again there would be pulse P and no-pulse NP rather than big pulse B and small pulse S in FIGS. 17 and 18.

(121) Further, the above explanation of the present technique in connection with FIGS. 17 and 18 may be considered a low-complexity approach, and considers single-ended measurements (i.e. at output node A or B). However, it is to be noted that a measurement e.g. focussing on SW1 and waveform 2 in FIG. 17 actually takes into account adjacent switches in sequence, since for SW1 turning on with waveform 2 the sequence would be (considering the output switches carrying the big pulses B) SW8 on.fwdarw.off, SW1 off.fwdarw.on.fwdarw.off, SW6 off.fwdarw.on. Therefore, in fact the contribution of adjacent switches could be taken into account.

(122) The following is an example.

(123) Considering the effect on current pulse area of an error in switch V.sub.TH, if the switch SW1 V.sub.TH contributes +100% error, the preceding opposite-side switch SW8 and following opposite-side switch SW6 contribute 50% error each (given waveform 2). This can be taken account of when calculating how much to adjust each switch V.sub.TH based on the current error measurements, for example:
Adjust(SW1)=k*[error(SW1)0.5*error(SW8)0.5*error(SW6)]

(124) To help separate out the errors for a given switch, waveforms which use switching to same-side switches can be used as well as those which use switching to the opposite-side switches mentioned above. For example, if currents are measured for (SW4+SW1) both on and (SW1+SW2) both on and the errors added together, the result has twice as much contribution from SW1 as from SW4 and SW2. If this is added to the opposite-side-switch result from above, the result now has 4 contributions from SW1 and 1 each from SW6, SW8, SW2 and SW4, which gives a more accurate estimation of the switch error for SW1.

(125) Depending on the exact effect of errors in a switch V.sub.TH (for example, this may be influenced by the parasitic capacitance on the common tail node), when making measurements to calculate the error for a given switch it may be preferable to use only voltage measurements on the output to which the switch is connected, or the differential output, or some combination of both. This choice may also be affected by whether only opposite-side switching waveforms are used, or also same-side switching as described above.

(126) With this in mind, waveforms could be adopted to allow double-ended measurements to be made (between output nodes A and B) and to allow the influence of switches SW1 to SW8 to be isolated by comparing the various voltage readings obtained. One possible approach is, for a pair of switches such as SW1 and SW5, to turn them SW1 on.fwdarw.off, SW5 off.fwdarw.on, and then do the opposite.

(127) For example, for each switch, the error measurement is the differential output voltage when the switch is on minus the baseline measurement as shown in FIG. 17. All 8 switches in a segment may be measured, then the errors may be calculated. The switch adjustments (bulk voltage change) may just be equal to these errors (multiplied by a constant which controls how fast the calibration converges). Or using the fact mentioned above that the preceding and following switches steal current, the adjustment for a given switch can also use the errors from these adjacent switches.

(128) Returning to FIG. 11, it is explained above that in the context of the circuitry of FIGS. 8 and 14 the upper part of the clock signals is important, the lower parts being less important. This is because the three points for each current waveform (e.g. points 100, 102 and 100 for current waveform IOUT.sub.A in FIG. 11) are fixed relative to the clock signals CLK .sub.1 to .sub.4, with particular focus on example points 90, 92 and 94.

(129) The inventors have considered this feature of the operation of the circuitry of FIGS. 8 and 14, in connection with the generation of the clock signals CLK .sub.1 to .sub.4. In particular, it is difficult at high frequency (e.g. at 16 GHz) to ensure that stable, reliable such clock signals are supplied to the output switches (as in the clock-controlled circuitry 52).

(130) It is desirable to provide the DAC circuitry with a four-phase sinewave clock signal: (1) with a defined common-mode voltage; (2) with a defined amplitude (Vpp); and (3) with the circuitry capable of rejecting amplitude differences between the different phases.

(131) However, as indicated in FIG. 20(a), such clock signals in practice have amplitude common-mode errors {circumflex over (1)} and amplitude errors {circumflex over (2)} and {circumflex over (3)}, which may be dynamic (i.e. vary over time).

(132) The inventors have recognised that it may be advantageous to focus on controlling the upper parts of those signals (which are important, as above) and to pay less attention to or sacrifice the lower parts (which are less important, as above). Moreover, the inventors have recognised that the shape and level of the clock signals 1 to 4 is most critical as supplied to the gates of the output switches SW1 to SW8, since this is where those signals control the operation of the circuitry.

(133) Accordingly, the inventors have considered aligning the upper portions of the clock signals 1 to 4 by shifting them up or down, as indicated in FIG. 20(b). As shown, the positive peaks are aligned relative to a reference voltage V.sub.ON. The inventors have considered carrying out this shifting locally, i.e. substantially at the point where the clock signals are supplied to the gates of the output switches.

(134) This has the effect of controlling the parts of those signals which are important (the uppermost parts), and shifting the effects of amplitude errors (which may be present in the clock signals as originally generated) to the negative peaks or troughs where they have little if any effect on the operation of the output switches.

(135) FIG. 21(a) presents the four switches SW1 to SW4 again for ease of understanding, as an example four of the switches SW1 to SW8 which receive clock signals CLK 1 to 4. Similarly, FIG. 21(b) presents clock signals CLK 1 to 4.

(136) Focus is now placed on switch SW1 as an example, and this is reproduced in FIG. 21(c) which presents clock-level control circuitry 170 embodying the present invention.

(137) The following explanation of course equally applies to the other switches SW2 to SW4 mutatis mutandis (and indeed to SW5 to SW8).

(138) In order to be able to shift the level of the clock signal, the clock signal 1 is supplied to switch SW1 via a capacitor 172 to DC decouple the clock signal as supplied to the gate of switch SW1 from the clock signal as supplied from a clock generator upstream.

(139) Although it might then seem appropriate to connect the gate to a common-mode reference voltage via a resistor 174 (as indicated in dashed formto indicate that this is not actually done), this would have the effect of controlling the common mode of the clock signal 1dealing with only error {circumflex over (1)} as shown in FIG. 20(a) and not dealing with errors {circumflex over (2)} and {circumflex over (3)}. The inventors have in particular recognised that a more effective approach would be to try to control the positive peak of the clock signal as in FIG. 20(b), without necessarily controlling (i.e. focussing on) the overall common-mode voltage or the negative peak.

(140) In order to achieve this, the inventors have proposed connecting the gate of the output switch to a reference voltage V.sub.ON (see FIG. 20(b)) when the clock signal concerned (e.g. CLK 1 for output switch SW1) is around its peak, so as instead to control a particular or special common-mode voltage around which the uppermost part of that clock signal fluctuates.

(141) In order to achieve this, the gate terminal of the (main) switch SW1 in FIG. 21(c) is connected to reference voltage V.sub.ON via a PMOS (auxiliary) transistor 176, which itself is controlled by the clock signal 3 which is 180 out of phase with clock signal 1. Clock signals 1 and 3 may be referred to as CK and CK in the generic sense, given their opposite phases, and such nomenclature will be used going forwards.

(142) The advantage of using CK to control the PMOS transistor and CK to control (NMOS) switch SW1, is that the PMOS transistor turns on to connect the gate of the switch SW1 to V.sub.ON at effectively the same time as SW1 turns on. This is apparent from FIG. 21(b), where clock signals CLK 1 and 3 have been highlighted in bold and marked as CK and CK. It can be seen that that CK is at or around its positive peak (turning on NMOS switch SW1) at substantially the same time as CK is at or around its negative peak (turning on PMOS switch 176).

(143) The circuitry 170 depicted in FIG. 21(c) accordingly operates effectively as a track-and-hold circuit, based upon the RC time constant of the PMOS transistor 176 (with on-resistance R.sub.ON) and the AC coupling capacitor 172. Thus, when the PMOS transistor is turned on, the positive peak part of the clock signal CK as supplied to the switch SW1 is shifted towards the desired voltage V.sub.ON. The bandwidth BW of the bias loop might for example be designed to be approximately 1 GHz so as to reject amplitude errors not caught by other calibration circuitry. In effect, such errors are rejected by making them appear in the troughs (negative peaks) where they are not important.

(144) Even given other calibration circuitry as mentioned above, the present invention may be beneficial since it may reject errors up to e.g. 1 GHz as discussed above. Such other calibration might for example be carried out only 50 times per second (not rejecting errors above 50 Hz) or only once per second (not rejecting errors above 1 Hz).

(145) It is noted that it is not the actual positive peak itself which is shifted towards V.sub.ON, but instead the peak part since the PMOS transistor 176 is turned on and off gradually in the same way as the NMOS output switch (i.e. not ideally in the sense of a square wave). The point of the signal which is shifted towards V.sub.ON is higher than the middle point between: (a) the point on CK when the PMOS transistor turns on based on CK; and (b) the positive peak of CK itself. It is higher e.g. because the clock spends more time at the peak than transitioning through the PMOS switching threshold (shape of sinewave peak), and the on resistance of the switch is lower at the peak than near the threshold.

(146) As will be appreciated from a comparison of FIGS. 20(a) and 20(c), the present invention effectively transfers positive peak errors to the negative peak or trough, so that in the ideal case there is 0% error at the positive peak and 200% error at the negative peak (i.e. a doubling of error in the trough). In a practical embodiment there might be e.g. 10% error at the positive peak and 190% at the negative peak, with the change for the positive peak (which matters) representing a 10(20 dB) error reduction.

(147) It is reiterated that the clock-level control circuitry 170 comprising a capacitor 172 and PMOS transistor 176 as employed in FIG. 21(c) could also be employed for each of the switches SW2 to SW8, in each case providing the relevant clock phase (CK) to the NMOS output switch and the out-of-phase clock phase (CK) to the PMOS transistor.

(148) FIG. 22 is a schematic diagram based on FIG. 21(c), but adapted to indicate schematically that the clock signals CK and CK originate from a clock generator such as the clock generator 62 of FIG. 10, and to indicate that the amplitude of the two clock signals (as applied to SW1 and switch 176) could be detected, compared to a desired amplitude, and the result of the comparison used to control the clock generator, thereby performing Amplitude Level Control (ALC). The control could be common to all clocks or could be individual per clock.

(149) FIG. 23 presents an expanded version of the FIG. 21(c) circuitry, to indicate schematically how such ALC might be carried out in practice and to indicate that two techniques may be employed together, namely: (a) use a PMOS (auxiliary) transistor (176 in FIG. 23) to fix or align the clock positive-peak regions, and move the errors to the negative peaks or troughs as already explained; and (b) use an NMOS (auxiliary) transistor (178 in FIG. 23) to measure the errors in the negative peaks to control the amplitude (ALC) of the generated clock signals.

(150) Thus, in FIG. 23, the same PMOS transistor 176 is shown connected in the same manner to a reference voltage V.sub.ON and controlled by clock signal CK (albeit it is shown positioned in the upper rather than lower half of the drawing). The reference voltage V.sub.ON is shown as generated by an amplifier 180 from another reference voltage V.sub.REF1. An NMOS transistor 178 is also provided connected in a similar manner to the gate terminal of output switch SW1 but via a capacitor 182 (very small, e.g. <0.1 pF) to ground (another reference voltage). The NMOS transistor 178 is also controlled by clock signal CK.

(151) The effect is that the PMOS transistor 176 turns on when CK is around its positive peak (CK is around its negative peak) and acts to fix the peak regions around V.sub.ON as already described. V.sub.ON is also taken as a measure (+ve PEAK) representative of the positive peak voltage of CK as indicated. Additionally, the NMOS transistor 178 turns on when CK is around its negative peak (CK is around its positive peak) and provides (i.e. measures) a voltage equivalent to V.sub.ON but as a measure (ve PEAK) representative of the negative peak voltage of CK as indicated.

(152) These two measures (+ve PEAK and ve PEAK) may then be compared (e.g. by way of a subtractor 184) to give a measure of the peak-to-peak voltage Vpp of the clock signal CK, the result compared with a desired Vpp (e.g. by way of another subtractor 186), and the final result used to control the clock generator (which may be clock generator 62 of FIG. 10), e.g. via an amplifier 188.

(153) This technique may be carried out individually per clock phase 1 to 4, or in parallel for all clock phases as indicated in FIG. 23 (since the control loops have a track and hold property). Four transistors are shown in FIG. 23 above the clock generator, controlled by the output of amplifier 188, to represent control of the four phases in parallel. Separate amplitude control would mean that the circuit could also compensate for clock amplitude differences between the four phases, for example by adjusting the clock driver bias currents. This would equate to separate control of the four transistors above the clock generator in FIG. 23. For example, for each phase only the switches for that phase (e.g. SW1 and SW5 for phase 1) would contribute to +ve PEAK and ve PEAK and only the relevant one of the four transistors above the clock generator would being controlled by the output of amplifier 188.

(154) FIG. 24 presents a refinement 190 of the basic circuitry 170 shown in FIG. 21(c). A problem with the basic circuitry 170 is that the threshold voltage V.sub.TH of the PMOS transistor 176 varies with process, e.g. varying by up to 100 mV. The V.sub.TH variation for this particular transistor (from chip to chip) is important because it will affect the set (target) amplitude of the clock signal CK, which it is desired to keep constant (e.g. across the four phases 1 to 4).

(155) The solution provided in FIG. 24 is to DC decouple CK from the gate of the PMOS transistor 176 by way of a capacitor 192 (AC coupling means), and to provide a gate bias for PMOS transistor 176 using another PMOS transistor 194, a resistor 196 and a current source 198 connected as shown. The current source 198 is chosen to give the bias PMOS transistor 194 about the same Ron as the average value of Ron of the PMOS switch 176. The result is that if V.sub.TR is smaller, the gate bias is made higher to compensate, and vice versa. That is, since both PMOS transistors 176 and 194 are created in the same process (e.g. on the same chip), their threshold voltages V.sub.TH match (to a high degree) and the second 194 compensates for the first 176 by providing a V.sub.TH shift in the gate bias.

(156) Furthermore, the reference voltage V.sub.REF2 in FIG. 24 may be set according to Vpp of the clock signal CK so that the amplitude of the clock signal CK has no effect on the R.sub.ON of the switch 176, i.e. V.sub.GS (SW)=Vpp (CK). If the V.sub.TH or V.sub.GS of the switch varies then so does the point at which it turns on (i.e. how close to the CK waveform peak). The circuit can be designed so that the point where the switch turns on (how close to the peak of CK) is independent of V.sub.TH of switches 176 and 194 (they are both PMOS switches so their V.sub.TH varies together with process variation) and/or V.sub.peak (the peak voltage of CK).

(157) It will be appreciated that the refinement 190 presented in FIG. 24 could be applied in an analogous manner to the NMOS switch 178 of FIG. 23, so as to also compensate for V.sub.TH variation for the NMOS switch 178. In that case, however, an NMOS transistor would need to be provided in place of PMOS transistor 194.

(158) The contribution relevant to FIGS. 20 to 24 may be summarised as follows.

(159) Clocked switches (auxiliary switches) such as switches 176 and 178, driven by the opposite phase clock CK to the clock CK supplied to the (main) output switch (e.g. SW1 as in the Figures) may be used to: (1) sense the positive peak (PMOS switch 176) and control the peak region of CK; and (2) sense the negative peak (NMOS switch 178) of CK. The added (auxiliary) switches may be very small, e.g. relative to the size of the (main) output switches SW, giving small added capacitance, and be relatively insensitive to switch errors. For example, the V.sub.TH error of the switches 176 and 178 does not directly cause errors because when they start to turn on (at V.sub.GS=V.sub.TH) their resistance is high. Most of their effect is at the peak of the sinewave and here it is just equivalent to an on-resistance variation, which only causes a much smaller error in the measurement.

(160) Further, the refinement of FIG. 24 may be employed for improved accuracy. This involves providing further switches equivalent to switch 194 to: (1) adjust the gate voltage of the NMOS/PMOS gate voltage concerned to cancel V.sub.TH process variation; and (2) adjust the NMOS/PMOS gate voltage to cancel R.sub.ON change from clock amplitude variation (V.sub.GS (SW)=Vpp (CLK)). Both of these require AC coupling to the NMOS/PMOS gate equivalent to capacitor 192.

(161) These contributions may be applied to set V.sub.ON for driving the NMOS output switch in analogue, to reject clock amplitude variation, and to detect peaks for ALC of the clocks.

(162) It is incidentally noted that the techniques described above in connection with FIGS. 20 to 24 relate to the control of the clock signals CLK 1 to 4 as applied to the output switches SW1 to SW8 of the DAC circuitry of e.g. FIGS. 8 and 14. The techniques may therefore be applied to other circuits which employ clock signals CLK 1 to 4 and for which the uppermost part of those clock signals is more important than the lower part.

(163) One such other circuit is shown in FIG. 25, which corresponds to sampling circuitry 200 for use in an analogue-to-digital converter (ADC) as devised by the present inventors. FIG. 25 corresponds to FIG. 10 of EP-A1-2211468, to which reference may now be made. In FIG. 25, the point to note is that sampling switches SW1 to SW8 correspond to output switches SW1 to SW8 of FIGS. 8 and 14, and that clock signals CLK 1 to 4 also correspond to clock signals CLK 1 to 4 of FIGS. 8 and 14. Moreover, the relative importance of the uppermost parts of the clock signals CLK 1 to 4 explained in connection with FIG. 11 also applies to the sampling circuitry 200 of FIG. 25, as explained in connection with FIG. 12 of EP-A1-2211468. A detailed understanding of the sampling circuitry 200 can be found in EP-A1-2211468.

(164) Thus, the present invention also extends to sampling circuitry and ADC circuitry which employs the techniques of FIGS. 20 to 24.

(165) For a fuller understanding of the ADC circuitry disclosed in EP-A1-2211468, FIG. 26 is a schematic diagram of analogue-to-digital circuitry 210 which corresponds to the circuitry of FIG. 9 of EP-A1-2211468. Circuitry 210 comprises a sampler 200 (which corresponds to the sampling circuitry shown in FIG. 25), a voltage-controlled oscillator VCO 62 (which corresponds to the clock generator 62 of FIG. 10), demultiplexers 212, ADC banks 214, a digital unit 216 and a calibration unit 218.

(166) The sampler 200 is configured to perform four-way or four-phase time-interleaving so as to split the input current I.sub.IN into four time-interleaved sample streams A to D. It is incidentally noted that FIG. 25 represents differential sampling circuitry, in which a differential input signal is employed (i.e. employing four sampling switches SW1 to SW4, and a complementary set SW5 to SW8), for example to take advantage of common-mode interference rejection. For simplicity, FIG. 26 is presented with a single-ended input signal, current I.sub.IN, which is divided into the four sample streams A to D by way of switches SW1 to SW4. Of course, FIG. 26 could be interpreted to apply to differential sampling circuitry, in which case the input signal, current I.sub.IN, would be a differential input, with SW1 to SW8 being employed in sampler 200 as in FIG. 25, and with each of the streams A to D being differential streams. The disclosure will be interpreted accordingly.

(167) VCO 62 is a quadrature VCO operable to output four clock signals 90 out of phase with one another, for example as four raised cosine signals CLK 1 to 4. VCO 62 may for example be a shared 16 GHz quadrature VCO to enable circuitry 200 to have an overall sample rate of 64 GS/s.

(168) Each of streams A to D comprises a demultiplexer 212 and an ADC bank 214 connected together in series as shown in FIG. 26. The demultiplexers 212 and ADC banks 214 are identified individually per stream (with subscript suffixes) and collectively (with a dashed box) in FIG. 26. The sampler 200 operates in the current mode and, accordingly, streams A to D are effectively four time-interleaved streams of current pulses originating from (and together making up) input current I.sub.IN, each stream having a sample rate one quarter of the overall sample rate. Continuing the example overall sample rate of 64 GS/s, each of the streams A to D may have a 16 GS/s sample rate.

(169) Focusing on stream A by way of example, the stream of current pulses is first demultiplexed by an n-way demultiplexer 212.sub.A. Demultiplexer 212.sub.A is a current-steering demultiplexer and performs a similar function to sampler 200, splitting stream A into n time-interleaved streams each having a sample rate equal to n of the overall sample rate. Continuing the example overall sample rate of 64 GS/s, the n output streams from demultiplexer 212 may each have a 16/n GS/s sample rate. Demultiplexer 212.sub.A may perform the 1:n demultiplexing in a single stage, or in a series of stages. For example, in the case of n=16, demultiplexer 212.sub.A may perform the 1:n demultiplexing by means of a first 1:4 stage followed by a second 1:4 stage.

(170) The n streams output from demultiplexer 46 pass into ADC bank 214.sub.A, which contains n ADC sub-units each operable to convert its incoming pulse stream into digital signals, for example into 8-bit digital values. Accordingly, n digital streams pass from ADC bank 214.sub.A to digital unit 216. In the case of n=16, the conversion rate for the ADC sub-units may be 64 times slower than the overall sample rate.

(171) Streams B, C, and D operate analogously to stream A, and accordingly duplicate description is omitted. In the above case of n=16, circuitry 210 may be considered to comprise 64 ADC sub-units split between the four ADC banks 214.

(172) The four sets of n digital streams are thus input to the digital unit 216 which multiplexes/retimes those streams to produce a single digital output signal representative of the analogue input signal, current I.sub.IN. This notion of producing a single digital output may be true schematically, however in a practical implementation it may be preferable to output the digital output signals from the ADC banks in parallel.

(173) Calibration unit 218 is connected to receive a signal or signals from the digital unit 216 and, based on that signal, to determine control signals to be applied to one or more of the sampler 200, VCO 62, demultiplexers 212 and ADC banks 214. Further details regarding the operation, and related benefits, of circuitry 210 may be found in EP-A1-2211468.

(174) Against this backdrop, i.e. with the circuitry of FIGS. 8, 14 and 25 in mind, in particular considering FIGS. 10 and 26 together, clock generation and distribution circuitry for use with both the ADC and DAC circuitry will be considered further.

(175) In particular, it is noted that the same four-phase sinusoidal clock signal (clock signals CLK 1 to 4) is employed by the switches of both the DAC and ADC circuitry, i.e. by output switches SW1 to SW8 in FIGS. 8 and 14 and by sampler switches SW1 to SW8 in FIG. 25. Thus, substantially the same clock-signal generation and distribution circuitry may be employed for both.

(176) Indeed, as indicated in FIG. 27, the similarities (in terms of clock requirements between the ADC circuitry shown on the left-hand side) and the DAC circuitry (shown on the right-hand side) extend beyond the sampler and output switches (SW1 to SW8), e.g. to the demultiplexers 212 (and sub-ADC units 214) for the ADC circuitry and the multiplexers/retimers 72/74/76 for the DAC circuitry.

(177) In more detail, FIG. 27 shows parts of combined DAC and ADC circuitry 250, and has similarities with the DAC circuitry of FIG. 10. In particular, circuitry 250 comprises ADC circuitry 252 shown on the left-hand side, DAC circuitry 254 shown on the right-hand side, and clock generation and distribution circuitry 256 shown in the middle.

(178) In a similar manner to FIG. 10, the DAC circuitry 254 comprises the differential switching circuit 50 or 120, which may comprise the clock-controlled circuitry 52 and the data-controlled circuitry 54 or 154.

(179) It is incidentally noted (as before) that although FIGS. 8, 14 and 25 represent differential circuitry, for simplicity FIG. 27 is presented as if single-ended signals are used (or with only one half of corresponding differential signals shown). Of course, FIG. 27 could be interpreted to apply to differential circuitry, in which case the signals would be differential signals. The disclosure will be interpreted accordingly.

(180) The same running example is employed here as in FIG. 10, i.e. a desired DAC sample rate of 64 Gs/s, with data signals DATA 1 to DATA 4 input to the differential switching circuit 50/120 being 16 GHz (i.e. time-interleaved) data signals.

(181) Three stages of multiplexing/retiming 72, 74 and 76 are also shown as in FIG. 10, and as such duplicate description is omitted.

(182) Also shown in clock generation and distribution circuitry 256 is a clock generator 62 (having phase-locked loop PPL and polyphase filter PPF circuitry) configured to generate the clock signals CLK 1 to CLK 4 and supply them to the differential switching circuit 50 or 120. Further, shown are three stages of clock generation 80, 82, 84, in order to take the input clock signals CLK 1 to CLK 4 and generate in turn the clock signals required by the three stages of multiplexing/retiming 72, 74 and 76, as indicated in FIG. 10. Again, duplicate description is omitted.

(183) It is to be remembered that the differential switching circuit 50/120 is representative of a single segment or slice in the overall DAC, as in FIG. 10. The overall DAC circuitry 254 would have further slices or segments, each with their own stages of multiplexing/retiming 72, 74 and 76. The analogue outputs of the various slices or segments may be combined to create a single analogue output of the overall DAC, as explained before. Of course, the clock generation and distribution circuitry 256 may be shared between the segments (or separately provided, at least in part).

(184) In a similar manner to FIG. 26, the ADC circuitry 252 comprises the (differential) sampler 200. Again, either single-ended or differential signals could be used.

(185) The same running example is employed here as in FIG. 25, i.e. a desired ADC sample rate of 64 Gs/s, and with 2-stages of demultiplexing shown as 212A and 212B, each performing 1:4 demultiplexing, and with sub-ADC units 214. The overall 64 Gs/s sample rate accordingly outputs 4 streams from sampler 200 (single-ended or differential) each at 16 Gs/s (which may be expressed herein as 16 GHz), with the first demultiplexing stage 212A outputting 16 4 Gs/s signals, and with the second demultiplexing stage 212B outputting 64 1 Gs/s signals.

(186) An important point to note is that the same clock generation and distribution circuitry 256 provides its clock signals to the ADC circuitry 252, as well as to the DAC circuitry 254. The inventors have recognised advantageously that the same clock generation and distribution circuitry 256 may be used to support both the DAC and ADC circuitry, if the DAC and ADC are designed to require similar clock signals as they are in FIG. 27. In particular, looking at FIG. 27 and working downwards from the sampler 200 and switching circuit 50/120, in both the DAC and ADC circuitry the signals in successive stages are 4 16 GHz signals, then 16 4 GHz signals, and then 64 1 GHz signals.

(187) Incidentally, the clock-signal generation and distribution circuitry may contain circuitry such as phase interpolators or phase rotators to accurately retime or phase-shift clock signals (by tiny amounts) as applied to the DAC circuitry compared to those applied to the ADC circuitry, however effectively the two sets of circuitry may employ the same clock signals (i.e. having the same characteristicsshape/frequency/amplitude).

(188) This allows the same clock generation and distribution circuitry to be used in each of the four example scenarios indicated in FIGS. 28(a)-28(d). In FIG. 28(a), the same clock generation and distribution circuitry 256 is used to support both the ADC circuitry 252 on the left and DAC circuitry 254 on the right (as in FIG. 27). In FIG. 28(b), the same clock generation and distribution circuitry 256 is used to support both the DAC circuitry 254 on the left and ADC circuitry 252 on the right. In FIG. 28(c), the same clock generation and distribution circuitry 256 is used to support both the ADC circuitry 252 on the left and further ADC circuitry 252 on the right. In FIG. 28(d), the same clock generation and distribution circuitry 256 is used to support both the DAC circuitry 254 on the left and further DAC circuitry 254 on the right. Of course, the same clock generation and distribution circuitry 256 could be used to support more than two sets of DAC/ADC circuitry, and thus further combinations of ADC circuitry 252 and DAC circuitry 254 are envisaged beyond those in FIGS. 28(a)-28(d).

(189) The clock generation and distribution circuitry 256 could comprises means (e.g. phase rotators or phase interpolators) to arrange for some or all of the clock signals output to either the ADC circuitry or the DAC circuitry (depending on which are present) to be retimed, or phase shifted or phase rotated, for example to synchronise/align internal operations of the ADC/DAC circuitry or to synchronise/align channels (e.g. each being ADC or DAC circuitry) with one another or with a common synchronisation clock. In the context of FIGS. 28(a)-28(d), such means (e.g. phase rotators or phase interpolators) could be provided on both sides of the clock generation and distribution circuitry 256 so that both sides may be individually retimed, if necessary.

(190) This shared and flexible use of the clock generation and distribution circuitry 256 is advantageous. Generating the multiple high-frequency clock signals with careful control over relative timing and skew and distributing them to the switching circuits is a major design problem for such high-speed converters, and can constitute a large part of the overall development time and effort.

(191) Incidentally, two sets of driver circuitryDRV1 258 (for the ADC) and DRV2 260 (for the DAC)are indicated as being present in FIG. 27.

(192) FIG. 29 presents four example driver configurations, labelled A to D. In each case, it is assumed that the clock generation circuitry is on the left, and the output/sampler switches SW on the right.

(193) Driver A is termed Direct Drive, and is equivalent to there being no driver circuitry. That is, the clock signals are applied directly to the gates of the output/sampler switches. Driver B is termed Buffered, and assumes that the clock signals pass via buffers (which may each be considered to be two buffers in series). Driver C is termed AC Coupled, and assumes that the clock signals pass via AC-coupling (or DC-decoupling) capacitors as shown. Driver D is termed Buffered and AC-coupled, and assumes that the clock signals pass via buffers and AC-coupling capacitors as shown.

(194) FIG. 30 presents a table, detailing possible combinations for Drivers A to D which could be used as DRV1 and DRV2. Combination 1 is equivalent to there being no driver circuitry, i.e. with the clock signals applied directly to the gates of the output and sampler switches. Combinations 2 to 4 assume that only DRV2 is provided, with DRV1 effectively not being present. Combinations 5 to 7 assume that only DRV1 is provided, with DRV2 effectively not being present. Combinations 8 to 10 assume that both DRV1 and DRV2 are provided, and that they are the same as one another. Combinations 11 to 16 assume that both DRV1 and DRV2 are provided, and that they are different from one another.

(195) It will be appreciated that other driver designs beyond those in FIGS. 28(a)-28(d) could be employed. Moreover, FIG. 30 presents all combinations of Drivers A to D, and demonstrates that even where more than four possible driver designs are available, or there are more than two sets of DAC/ADC circuitry, all possible combinations of available drivers are envisaged. The above disclosure will be interpreted accordingly.

(196) The commonality of the clock requirements between the ADC and DAC circuitry has several advantages. Reduced time and effort is required in respect of design burden and layout complexity. There is also flexibility in system design, for example in view of the ADC/DAC mixtures shown in FIGS. 28(a)-28(d). There is also a benefit in terms of power/area, given that single clock generation and distribution circuitry may supply plural ADC/DAC circuits. There is also a benefit in terms of risk to a system designer, since tried and tested clock generation and distribution circuitry may be largely reused, limiting the expected number of redesigns. There is also the possibility of reduced complexity in version controlfor example different commercial markets may require different sample rates/frequencies, and reuse of tested clock generation and distribution circuitry per such market may thus be beneficial. These advantages stem from the case here where both the ADC and DAC circuitry have closely similar clock requirements/specifications, with similar multiplexing/demultiplexing stages, whereas typically high-speed ADCs and DACs have different clock requirements (especially at the highest-speed parts of the circuits) and different multiplexing/demultiplexing schemes.

(197) Circuitry of the present invention may from part of an analogue-to-digital converter or a digital-to-analogue converter. Circuitry of the present invention may be implemented as integrated circuitry, for example on an IC chip. The present invention extends to integrated circuitry and IC chips as mentioned above, circuit boards comprising such IC chips, and communication networks (for example, internet fiber-optic networks and wireless networks) and network equipment of such networks, comprising such circuit boards.

(198) The present invention may be embodied in many other different forms, within the spirit and scope of the appended claims.