Detection of an inter-turn winding fault in a motor
09973132 ยท 2018-05-15
Assignee
Inventors
- Stephen John Fedigan (Plano, TX, US)
- Sandun Shivantha Kuruppu (Dallas, TX, US)
- Paul LeRoy Brohlin (Parker, TX, US)
Cpc classification
International classification
G01R27/16
PHYSICS
H02P29/024
ELECTRICITY
Abstract
A motor control circuit includes a processor configured to calculate a plurality of motor impedances from measurements of an excitation voltage on a power bus to a motor and measurements of a plurality of currents through the motor resulting from the excitation voltage, and the processor configured to calculate individual winding inductances in the motor, based on the measured motor impedances, and configured to determine whether there is an inter-turn winding fault based on the calculated individual winding inductances.
Claims
1. A motor control circuit, comprising: a motor impedance measurement circuit for measuring an excitation voltage on a power bus to the motor and a plurality of currents through a motor resulting from the excitation voltage; a processor configured to calculate a plurality of motor impedances from the measurement by the motor impedance measurement circuit of the excitation voltage on the power bus to the motor and the measurement by the motor impedance measurement circuit of the plurality of currents through the motor resulting from the excitation voltage; the processor configured to calculate individual winding inductances in the motor based on the calculated motor impedances; and the processor configured to determine whether there is an inter-turn fault based on the calculated individual winding inductances.
2. The motor control circuit of claim 1, further comprising: an excitation circuit for sending the excitation voltage on the power bus to the motor.
3. The motor circuit of claim 2, further comprising: the excitation circuit comprising a resistor in series with the power bus and an electronic switch in parallel with the resistor; the excitation circuit comprising a signal source coupled to the power bus through an inductor in series with a capacitor.
4. The motor circuit of claim 2, further comprising: a plurality of switches configured to switch power to the motor; and where the frequency of the excitation voltage is at least ten times higher than the frequency of switching the plurality of switches.
5. The motor circuit of claim 1, further comprising a voltage divider, used by the motor impedance measurement circuit for measuring the excitation voltage on the power bus.
6. The motor circuit of claim 1, further comprising: a current sensor, used by the motor impedance measurement circuit for measuring current through the motor resulting from the excitation voltage.
7. The motor circuit of claim 6, further comprising: the processor computing motor impedance by dividing the excitation voltage on the power bus by current through the motor resulting from the excitation voltage.
8. The motor circuit of claim 6, the current sensor comprising a resistor.
9. The motor circuit of claim 1, the motor impedance measurement circuit further comprising an amplifier followed by two synchronous detectors.
10. The motor circuit of claim 9, each synchronous detector further comprising a multiplier that multiplies the output of the amplifier by a signal having the same frequency as the frequency of the excitation voltage.
11. The motor circuit of claim 1, further comprising: a bus capacitor; and the processor further configured to determine whether there is a failure of the bus capacitor based on the amplitude of the excitation voltage.
12. A method, comprising: measuring, by a motor impedance measurement circuit, an excitation voltage on a power bus to a motor and a plurality of currents through the motor resulting from the excitation voltage; computing, by a processor, a plurality of motor impedances using the measured excitation voltage from the measurement by the motor impedance measurement circuit and the measured plurality of currents from the measurement by the motor impedance measurement circuit; computing, by the processor, individual motor winding inductances based on the computed motor impedances; and determining, by the processor, whether the motor has an inter-turn winding fault, based on the computed motor winding inductances.
13. The method of claim 12, further comprising: generating, by an excitation circuit, the excitation voltage on the power bus.
14. The method of claim 13, further comprising: determining, by the processor, whether there is a failure of a capacitor on the power bus based on the amplitude of the excitation voltage.
15. The motor circuit of claim 1, wherein the individual winding inductances comprise individual stator winding inductances.
16. The motor circuit of claim 1, wherein the inter-turn winding fault indicates a short circuit between a first winding in the motor and a second winding in the motor.
17. The method of claim 16, wherein the first winding in the motor comprises a first stator winding in the motor and the second winding in the motor comprises a second stator winding in the motor.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1)
(2)
(3)
(4)
DETAILED DESCRIPTION
(5)
(6) The chopper circuit 112 causes a bus capacitor C.sub.B to linearly charge and discharge at the frequency of the chopper circuit 112. Preferably, the chopper circuit 112 generates an excitation voltage with a frequency that is substantially higher than human audio perception and at least ten times higher than the switching rate of the switches 106. Alternatively, if the switches are pulse width modulated (PWM), then the frequency of the excitation voltage is preferably at least ten times higher than the PWM carrier signal frequency, which may be on the order of 10 KHz. For example, the frequency of the excitation voltage may be on the order of 100 KHz.
(7) High frequency harmonics in a square wave excitation voltage may result in significant current in the bus capacitor C.sub.B.
(8) At the frequency of the excitation voltage, the motor impedance is effectively an inductance. As the motor rotates, the motor impedance varies, and the variation of motor impedance modulates both the amplitude and phase of the current resulting from the excitation voltage. In
(9)
(10)
(11) In the above equations, for example, a.sub.1 is the output of A/D 316 during the first switch state and represents the real part of a complex number, and b.sub.1 is the output of A/D 326 during the first switch state and represents the imaginary part of a complex number. I.sub.1 is the computed magnitude of the motor current resulting from the excitation voltage V.sub.E during the first switch state. .sub.1 is the computed phase of the motor current resulting from the excitation voltage V.sub.E during the first switch state.
(12) As discussed above, the motor impedance circuit 122 also measures the excitation voltage V.sub.E. In
(13)
(14) The processor 124 computes the motor impedance (Z.sub.1, Z.sub.2, Z.sub.3) for each switch state. The processor then generates three equations with three unknowns (L.sub.A, L.sub.B, L.sub.C) as follows:
(15)
(16) The processor 124 then solves for the three individual winding inductances (L.sub.A, L.sub.B, L.sub.C) and the computed winding inductances are analyzed for an inter-turn winding fault. If one of the individual winding inductances (L.sub.A, L.sub.B, or L.sub.C) is different than the others, or different than an expected value, then that motor winding may have an inter-turn fault.
(17) The processor 124 can also detect a failure of the bus capacitance C.sub.B. An increase in the amplitude of the excitation voltage V.sub.E may indicate a failed bus capacitance C.sub.B. That is, if the bus capacitor's equivalent resistance is increased, then the impedance of the bus capacitor C.sub.B is increased, and the attenuation of the excitation voltage V.sub.E is decreased, and the magnitude of the excitation voltage increases.
(18)
(19) While illustrative and presently preferred embodiments of the invention have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed and that the appended claims are intended to be construed to include such variations except insofar as limited by the prior art.