METHOD FOR POROSIFYING A MATERIAL AND SEMICONDUCTOR STRUCTURE

Abstract

A method for porosifying a III-nitride material in a semiconductor structure is provided, the semiconductor structure comprising a sub-surface structure of a first III-nitride material, having a charge carrier density greater than 5×10.sup.17 cm.sup.−3, beneath a surface layer of a second III-nitride material, having a charge carrier density of between 1×10.sup.14 cm.sup.−3 and 1×10.sup.17 cm.sup.−3. The method comprises the steps of exposing the surface layer to an electrolyte, and applying a potential difference between the first III-nitride material and the electrolyte, so that the sub-surface structure is porosified by electrochemical etching, while the surface layer is not porosified. A semiconductor structure and uses thereof are further provided.

Claims

1-42. (canceled)

43. A semiconductor structure comprising: a porous sub-surface structure of a first III-nitride material; and a non-porous surface layer of a second III-nitride material; the surface layer having a charge carrier density of between 1×10.sup.14 cm.sup.−3 and 1×10.sup.17 cm.sup.−3; in which the sub-surface structure has uniform porosity throughout the structure, and in which both the surface layer and the sub-surface structure have a minimum lateral dimension of more than 550 μm.

44. A structure according to claim 43, in which the surface layer completely covers the sub-surface structure.

45. A structure according to claim 43, in which the surface layer has a minimum lateral dimension of at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.

46. A structure according to claim 43, in which the surface layer and the sub-surface structure comprise III-nitride materials selected from the list consisting of: GaN, AlGaN, InGaN, and AlInGaN.

47. A structure according to claim 43, in which the threading dislocation density in both the surface layer and the sub-surface structure is at least 1×10.sup.4 cm.sup.−2, 1×10.sup.5 cm.sup.−2, 1×10.sup.6 cm.sup.−2, 1×10.sup.7 cm.sup.−2, or 1×10.sup.8 cm.sup.−2 and/or less than 1×10.sup.9 cm.sup.−2 or 1×10.sup.10 cm.sup.2.

48. A structure according to claim 43, in which the thickness of the surface layer is at least 1 nm, or 10 nm, or 100 nm, and/or less than 1 μm, or 5 μm, or 10 μm.

49. A structure according to claim 43, in which the porous sub-surface structure has an average pore size of greater than 1 nm, or 2 nm, or 10 nm, or 20 nm, and/or less than 50 nm, or 60 nm, or 70 nm.

50. A structure according to claim 43, comprising a plurality of sub-surface layers formed from III-nitride material in the form of a stack of layers; in which odd-numbered sub-surface layers (counting away from the surface layer) are porous, with uniform porosity throughout each layer, and even-numbered sub-surface layers are non-porous.

51. A structure according to claim 50, in which each odd sub-surface layer has the same porosity, and each even layer is non-porous, such that the structure acts as a distributed Bragg reflector (DBR).

52. A structure according to claim 50, in which at least two odd sub-surface layers have different porosities.

53. A structure according to claim 43, in which the semiconductor structure is not patterned with trenches.

54. A structure according to claim 43, in which the semiconductor structure is not pre-patterned with trenches separated by less than 1 cm, or 5 mm, or 1 mm, or 600 μm, or 400 μm, or 200 μm.

55. A structure according to claim 43, in which the outermost surface of the surface layer has a root mean square roughness of less than 10 nm, or less than 5 nm, or less than 2 nm, or less than 1 nm, or less than 0.5 nm, over an area of 1 micrometre squared.

56. A structure according to claim 43, in which the surface layer is not coated with an electrically insulating layer.

57. Use of a semiconductor structure as defined in claim 43 as a substrate for overgrowth of one or more semiconductor devices.

58. Use of a semiconductor structure as defined in claim 57, in which the semiconductor device is a laser or an LED.

59. Use of a semiconductor structure as defined in claim 43 as a mirror, or a distributed Bragg reflector (DBR).

60. A device incorporating or mounted on a semiconductor structure as defined in claim 43.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0149] Specific embodiments of the invention will now be described with reference to the figures, in which:

[0150] FIG. 1 shows a schematic illustration of the experimental setup for electrochemical etching;

[0151] FIG. 2A shows a schematic illustration of a multi-layer semiconductor structure forming a distributed Bragg-reflector (DBR) according to an aspect of the present invention;

[0152] FIG. 2B shows a cross-sectional scanning electron microscopy (SEM) image of the multi-layer semiconductor structure of FIG. 2A;

[0153] FIG. 3A shows a top view Nomarski optical image of the etched sample of FIG. 2B;

[0154] FIG. 3B shows an atomic force microscopy (AFM) image of the surface layer of a non-etched region of the sample shown in FIG. 2B;

[0155] FIG. 3C shows an atomic force microscopy (AFM) image of the surface layer of an etched region of the sample shown in FIG. 2B;

[0156] FIG. 4 shows the measured reflectance spectrum of a GaN DBR structure according to a preferred embodiment of the present invention;

[0157] FIG. 5A shows an AFM image of the top surface of an etched semiconductor wafer forming a DBR;

[0158] FIG. 5B shows an AFM image of the top surface of an un-etched GaN epitaxial layer;

[0159] FIG. 6 is a photograph of an etched 2-inch semiconductor wafer forming a DBR according to a preferred embodiment of the present invention;

[0160] FIG. 7A shows photographs of a range of GaN DBR structures according to a preferred embodiment of the present invention; and

[0161] FIG. 7B shows the measured reflectance spectra of the DBR structures of FIG. 7A;

[0162] FIG. 8A shows a schematic diagram of an overgrown GaN-based LED on a GaN DBR substrate, according to a preferred embodiment of the present invention;

[0163] FIG. 8B shows a cross-sectional SEM image of the overgrown LED structure of FIG. 8A;

[0164] FIG. 8C shows a photograph of a GaN LED structure without an underlying porous GaN DBR;

[0165] FIG. 8D shows a photograph of a GaN LED structure formed on top of a porous GaN DBR, according to a preferred embodiment of the present invention;

[0166] FIG. 8E shows the room temperature electroluminescence (EL) “internal quantum efficiency” (IQE) for LEDs with and without porous GaN DBRs as pseudo-substrates;

[0167] FIG. 9A shows a schematic diagram of a multi-layer semiconductor structure comprising several III-nitride materials, according to a preferred embodiment of the present invention;

[0168] FIG. 9B shows an SEM image of the multi-layer semiconductor structure of FIG. 9A; and

[0169] FIG. 9C shows a close-up SEM image of the multi-layer semiconductor structure of FIG. 9B.

DETAILED DESCRIPTION

[0170] FIG. 1 shows a schematic of an electrochemical (EC) experimental setup usable in the method of the present invention. As shown in FIG. 1, the experimental setup consists of a two-electrode electrochemical cell 100, with a sample 110 connected as an anode and a platinum foil 120 connected as a cathode. The platinum cathode, and at least a portion of the surface layer of the sample, are exposed to an electrolyte 130 by immersion in the electrolyte. A constant current DC power supply 140 is connected between the anode and the cathode, and an ammeter 150 is used to monitor and record the etching current flowing through the circuit.

[0171] Unless otherwise stated, the EC etching experiments described herein were conducted at room temperature with a semiconductor structure as the anode and a platinum foil as the counter electrode (cathode). Oxalic acid with a concentration of 0.25 M was used as the electrolyte. The etching process was carried out in a constant voltage mode controlled by a Keithley 2400 source meter. After etching, samples were rinsed with deionized water and blow dried in N2.

[0172] As discussed above in the summary of invention, the skilled person will appreciate that the term “undoped” is relatively imprecise in semiconductor technology. Practically speaking, all semiconductor material contains inherent impurities which can be thought of as “dopant” atoms. Different methods of semiconductor growth may produce different levels of impurity, and thus different inherent charge carrier concentrations.

[0173] Thus, it is possible that semiconductor materials referred to in the prior art as “undoped” may have high impurity levels, such that they have a natural charge carrier density of above 1×10.sup.17 cm.sup.−3 arising from impurities alone.

[0174] In appreciation of this, the inventors of the present invention prefer to use the term “non-intentionally-doped” (NID) to refer to semiconductor material that has been made without intentional doping. The impurity levels of semiconductor materials naturally depend on factors including the method by which they are formed, the environment in which they are formed, and the purity of the reactants used to form the semiconductor materials.

[0175] In the present application, the term “non-intentionally-doped” (NID) should be understood to refer to semiconductor materials deliberately grown to be as pure as possible, which have been measured to have a charge carrier density of between 1×10.sup.14 cm.sup.−3 and 1×10.sup.17 cm.sup.−3.

[0176] Semiconductor materials which have been intentionally doped with n-type dopants to obtain a charge carrier density greater than 5×10.sup.17 cm.sup.−3, may be referred to as “n+” semiconductor material FIG. 2A shows a schematic diagram of an epitaxial non-polar sample structure, which consists of alternating layers of non-intentionally-doped GaN (NID-GaN) and heavily doped n-type GaN (n+-GaN) layers. The NID-GaN layers have a charge carrier density of less than 1×10.sup.17 cm.sup.−3, while the n+-GaN layers have a nominal silicon doping concentration of 2.3×10.sup.19 cm.sup.−3. Each of the alternating NID-GaN/n+-GaN layers has a thickness of approximately 136 nm.

[0177] The sample comprises an uppermost surface layer of NID-GaN and 10 pairs of alternating NID-GaN/n+-GaN layers, arranged on a sapphire substrate and underlying base layers of lightly doped n-type GaN (n-GaN) and NID-GaN. The n-GaN layer has a thickness of 2 μm and is present for uniform distribution of the anodization bias across the sample.

[0178] The sample was grown by metal-organic vapour phase epitaxy (MOVPE) in a 6×2 in. Thomas Swan close-coupled showerhead reactor on r-plane sapphire substrates using trimethylgallium and ammonia as precursors, hydrogen as a carrier gas and silane for n-type doping. Firstly, a 4 μm thick a-plane GaN pseudosubstrate was grown with a nominal dislocation density of ˜4×10.sup.9 cm.sup.−2, and a basal plane stacking fault density of ˜5×10.sup.5 cm.sup.−1, in which a single SiNx interlayer was used for defect reduction. After the growth of another 500 nm undoped GaN layer, 10 pairs of alternating n+-GaN and NID-GaN layers were grown.

[0179] The sample of FIG. 2A was electrically contacted by soldering an indium wire to the edge of the sample. A portion of the sample, of approximately 1 cm×1 cm in size, was then immersed in the electrolyte. Using the experimental setup shown in FIG. 1, an EC etching process was carried out on the sample in a constant voltage mode, with a DC bias of 6 V, and controlled by monitoring and recording the etching current signal at room temperature without UV illumination.

[0180] The EC porosification process begins with the oxidation of the alternating n+-GaN layers by localised injection of holes upon the application of a positive anodic bias, and localised dissolution of such oxide layer in the acid-based electrolyte will result in the formation of a mesoporous structure. The end of the anodisation process is reached when the etching current drops to the base line level, indicating that all the n+-GaN layers have been etched and transformed into mesoporous GaN layers, typically after approximately 30 minutes.

[0181] The cross-sectional scanning electron microscopy (SEM) image in FIG. 2B shows the morphology of the porous DBR structure 200. The cross-section of FIG. 2B was taken from an edge cleaved post-etching, far away from the original sample edges. This confirms that the porosification process proceeded extremely uniformly across the entire sample area that was immersed in the etching solution. This also confirms that the etched layer morphology is indeed mesoporous, as the average pore size is approximately 30 nm.

[0182] FIG. 2B further shows that the NID-GaN layers stay almost intact during the EC etching, and are not themselves porosified. Only the n+-GaN layers are selectively etched and transformed into mesoporous layers of mesoporous GaN (MP-GaN).

[0183] The 1 cm×1 cm sample is far larger than samples porosified by horizontal etching in the prior art, as horizontal etching would be unable to penetrate horizontally into the centre of such a large sample without regular trenches in the sample surface. Furthermore, the etching time of 30 minutes would be insufficient for horizontal etching to proceed far into the bulk material of the sample. Thus the porous cross-section of FIG. 2B, taken far from the sample edges, is evidence that the n+-GaN layers have been etched through the surface layer of NID-GaN, and not horizontally from the sample edges.

[0184] FIG. 3A shows a top view Nomarski optical image of the as—etched sample, where a boundary (marked by the white arrow) that corresponds to the position of the sample being immersed in the EC etching solution can be seen. The optical contrast between the regions with and without the porous structure arises due to the altered refractive index of the porosified layers, leading to a far higher reflectivity in the etched region. The sharp boundary between etched and non-etched regions provides further evidence of etching through the surface layer, as uniform reflectivity (and thus porosity) is achieved far from the edges of the structure.

[0185] To evaluate possible etching damage of the top surface layer of NID-GaN, atomic force microscopy (AFM) images were taken from non-porous and porous regions, which are shown in FIGS. 3B and 3C, respectively. Apart from some dirt/small particles present in the porous region that may be related to the EC etching products, contaminants in the etching chemicals and/or sample cleaning, no changes to the surface morphology were observed and the root mean square roughness (RRMS) of the top GaN surface is similar in both the etched and unetched regions, at around 1 nm roughness measured over a 1 μm×1 μm area. It appears therefore that the sub-surface EC porosification does not degrade the surface of the GaN surface layer, and the RRMS of the post-etching sample is sufficiently low for further semiconductor overgrowth.

[0186] Such a porous DBR could therefore be used as a bottom mirror template for the regrowth of other heterostructures or, for example, deposition of high quality dielectric DBRs in order to form a planar microcavity.

[0187] The porous DBR structure illustrated in FIGS. 2B to 3C is formed purely by epitaxial growth of alternating NID-GaN/n+-GaN layers, followed by EC porosification. By using the method of the present invention there is no need to protect the sample surface with SiO2, or to pattern the sample with regular trenches. There is also no need to use UV illumination.

[0188] The reflectance spectra of the etched GaN/MP-GaN DBR were measured using a micro-reflectance setup using ambient room light and normalized to a commercial silver mirror with a spot size of ˜1 μm. FIG. 4 shows the measured reflectance spectrum of a GaN/mesoporous-GaN DBR structure with a peak reflectance centred at ˜564 nm and a stop-band with a full-width at half-maximum of 91 nm.

[0189] A peak reflectance of more than 96% is achieved on non-polar GaN/MP-GaN DBR structure with a very large spectral width, more than 80 nm. We note that the measured peak reflectance is slightly lower than that of the simulated values, which could be attributed to the local non-uniformity of the mesoporous GaN layer and the through-layer etching pathways where these lead to some slight porosification of the NID-GaN.

[0190] Nevertheless, to the inventors' knowledge, this is the highest reported peak reflectance from a non-polar III-nitride DBR structure, and there is also an increase of more than a factor of 2 in the stop-band width compared to previously reported structures. This is attributed to the fact that a much larger refractive index contrast can be achieved using mesoporous GaN layers without introducing a significant lattice mismatch which would lead to large strains and degradation of structural quality (via the formation of cracks and generation of dislocations). In contrast, the more usual method for the fabrication of nitride DBRs, the use of Al-containing epitaxial layers on GaN, such as Al(Ga)N and InAlN to achieve a refractive index contrast, inevitably leads to significant strain in at least one in-plane direction for non-polar structures.

[0191] In another experiment, an equivalent DBR structure was epitaxially grown on a circular semiconductor wafer with a diameter of 2 inches (5.08 cm). A portion of the wafer was then immersed in electrolyte and etched as described above in relation to FIGS. 1 to 2B. The etching time for a typical 2-inch wafer at 6 V was less than 6 hours.

[0192] The wafer-scale fabrication of the mesoporous GaN DBR was found to be correlated with the threading dislocation density. The inventors believe that these threading dislocations act as through-layer etching pathways and facilitate sub-surface etching through the surface layer and downwards through the multi-layer structure. Only perfect threading dislocations appear to be responsible for the through-layer etching pathways.

[0193] In order to achieve 2-inch wafer-scale formation of mesoporous GaN DBRs, it may be necessary for the surface layer and sub-surface layers to have a minimum threading dislocation density of at least 1×10.sup.4 cm.sup.−2.

[0194] Due to the presence of threading dislocations, the EC process initiated from the top NID-GaN surface appears to proceed through the threading dislocation sites downwards into the multi-layer structure. Once the etchant reaches a sub-surface layer with a charge carrier density of greater than 5×10.sup.17 cm.sup.−3, etching proceeds outwards from the threading dislocation into the n+-GaN layer, due to the conductivity selective nature of the EC process.

[0195] FIGS. 5A and 5B show AFM images of the top NID-GaN surface of a finished wafer-scale DBR sample and a standard as-grown GaN epitaxial layer. The surface morphology of the porous DBR is almost identical to the as-grown GaN epitaxial layer. The surface roughness (root mean square roughness over 5 μm×5 μm scan) is found to be very similar and can be maintained at ˜0.4 nm.

[0196] FIG. 6 is a photograph of the as—etched 2-inch semiconductor wafer 600 under room light illumination, showing the reflection of a card printed with a logo. While the region close to the wafer-flat is transparent and unetched, the intense reflection in the etched DBR region demonstrates the uniform EC porosification process and the realization of high reflectance non-polar GaN/MP-GaN DBRs on a wafer-scale. Given the fact that uniform porosification occurs across the entire 2-inch wafer, it is confirmed again that the sub-surface layers of n+-GaN are electrochemically etched downwardly through the surface layer of NID-GaN, and all of the intermediate layers of NID-GaN, in addition to any lateral etching occuring at the wafer edges.

[0197] Although the local refractive index of the NID-GaN layers may have been altered by the through-layer etching, the measured reflectivity values are very close to the theoretical values and the density of such through-layer etching pathways is considered to be low enough (˜2×10.sup.9 cm.sup.−2), that the global reflectivity at the wafer scale (˜ 5 cm diameter) is only marginally affected.

[0198] The majority of the material exhibits a sufficient reflectivity, unaffected by these issues, to allow the fabrication of devices such as LEDs and micropillar cavity structures for single photon sources with reasonable yield.

[0199] Improved GaN pseudosubstrates with a much lower density of perfect dislocations still show porosification, even when the typical dislocation spacing is a few microns or more, which will reduce the effect of the vertical etching pathways further while still allowing wafer scale fabrication.

[0200] Tunability of the DBR can be achieved simply by varying the thicknesses of the NID-GaN and n+-GaN layers. FIGS. 7A and 7B show photographs under room light illumination and the measured reflectance spectra of various GaN/porous GaN DBR structures. A widely tunable stop-band with high reflectance (>96%) across the entire visible spectrum is demonstrated, simply by varying the epitaxial layer thicknesses of the NID-GaN and n+-GaN. Due to the large refractive index contrast between the GaN and porous GaN layers, the stop-band widths are also maintained to be very wide (>80 nm).

[0201] Particularly preferably, porous GaN structures according to the present invention may be usable as substrates, or “pseudo-substrates”, for further overgrowth or deposition of additional semiconductor material. In other words, it may advantageously be possible to deposit or overgrow additional layers of III-nitride material, or other semiconductor material, onto the porosified semiconductor structures of the present invention, in order to form a variety of devices. The excellent reflectivity characteristics exhibited by the DBR examples above, for example, make DBRs formed according to the present invention promising as pseudo-substrates for overgrowth of optoelectronic devices such as LEDs.

[0202] Particularly advantageously, the present method allows preparation of porosified semiconductor structures with “epi-ready” surfaces, that is, upper surfaces with sufficiently low roughness that additional semiconductor layers can be epitaxially grown directly onto the structures For example, porous GaN based DBR pseudo-substrates according to embodiments of the present invention can be used for the manufacture of III-nitride LEDs, lasers, single photon sources, and can also be used for the formation of hybrid cavity structures and devices.

[0203] FIG. 8A shows a GaN-based LED structure 800 on a NID-GaN/MP-GaN DBR 850, as described above in relation to FIGS. 2 to 7. Following formation of the DBR according to the method described above, further semiconductor layers are epitaxially grown on the DBR according to known epitaxial techniques, so as to form a light emitting diode (LED).

[0204] The DBR thus acts as a pseudo-substrate for overgrowth of the LED.

[0205] The overgrown LED structure comprises a simple p-i-n structure, containing 5 periods of 2.5 nm InGaN quantum wells separated by 7.5 nm thick GaN barriers. The bottom of the active region is clad by a 500 nm-thick layer of Si-doped n-type GaN with a charge carrier density of 3×10.sup.18 cm.sup.3, and the upper end of the active region is clad by a 300 nm-thick layer of Mg-doped p-type GaN.

[0206] Electrically injected LED devices were fabricated using chlorine based inductively coupled plasma etching to form mesas. A Ti/Al/Ti/Au metal stack annealed in N.sub.2 serves as the n-type contact and a thin Ni/Au layer annealed in a mixture of N.sub.2/O.sub.2 acts as a semi-transparent current spreading layer on top of the p-type GaN layer, beneath a Ti/Au p-type contact.

[0207] FIG. 8B shows a cross-sectional SEM image of the overgrown LED structure 800 on a porous GaN DBR pseudo-substrate 850. The pore morphology of the DBR has been retained the overgrowth process.

[0208] FIG. 8C shows a photograph of a similar LED structure 860 without an underlying porous GaN DBR, while FIG. 8D shows the same LED structure 800 formed on a porous GaN DBR 850 as described above. By comparison, the LED that has been overgrown on a porous GaN DBR is far brighter than the LED without a GaN DBR as a pseudo-substrate. The intensity of the optical emission can be seen to be very uniform across the device of FIG. 8D, and is only interrupted by dislocations and GaN material non-uniformities, which may have resulted from improper cleaning of the DBR before overgrowth.

[0209] FIG. 8E shows the room temperature electroluminescence (EL) “internal quantum efficiency” (IQE) as a function of current density for LEDs with and without porous GaN DBRs as pseudo-substrates. The LEDs formed on a non-porous DBR exhibit a low IQE, and decreases at a low current density, while the IQE of the LED/porous GaN DBR exhibits a much higher peak efficiency and starts to decrease at more than one order of magnitude higher current density.

[0210] FIG. 9A is a schematic diagram of a multi-layer semiconductor structure forming a GaN HEMT transistor structure, according to a preferred embodiment of the present invention. The structure comprises several III-nitride materials.

[0211] The structure shown in FIG. 9A was epitaxially grown by MOVPE on a 2-inch sapphire wafer 910, according to known methods. First, a layer A of NID-GaN, with a charge carrier density of between 1×10.sup.14 cm.sup.−3 and 1×10.sup.17 cm.sup.−3, was deposited on the sapphire substrate, followed by a 5 μm-thick layer B of GaN with a charge carrier density of greater than 5×10.sup.17 cm.sup.−3. A 250 nm-thick layer C of GaN with a charge carrier density greater than 5×10.sup.17 cm.sup.−3. The charge carrier density of layer C was made greater than the charge carrier density of layer B by intentionally doping layer C to a higher degree. A 500 nm-thick layer D of NID-GaN, with a charge carrier density of between 1×10.sup.14 cm.sup.−3 and 1×10.sup.17 cm.sup.−3, was then deposited on top of layer C. A 1 nm-thick layer E of NID-AIN was then formed on layer D, followed by a 25 nm-thick layer F of NID-A10.25GaN and a 2 nm-thick surface layer G of NID-GaN.

[0212] An electrical contact was made on the side of this multi-layer structure, and the wafer was immersed in electrolyte and etched as described in relation to FIG. 1, above.

[0213] FIGS. 9B and 9C are SEM images of a cross-section of the wafer post-etching. The cross section was taken far from the edges of the wafer, demonstrating that the porosification had occurred by etching through the surface layer, and not by horizontal etching from the edges of the wafer. Due to the limitations of the prior art methods, discussed above, horizontal etching of an entire 2-inch wafer is not possible.

[0214] It can be seen from FIGS. 9B and 9C that layers E, F and G, and the NID-GaN layer D have not been porosified, as their charge carrier densities are between 1×10.sup.14 cm.sup.−3 and 1×10.sup.17 cm.sup.−3. GaN layer C below, however, has been porosified to a high degree due to its high charge carrier density, and can be seen to have relatively large pores distributed throughout the layer. GaN layer B has also been porosified, as prior to etching it had a charge carrier density of greater than 5×10.sup.17 cm.sup.−3. However, the pores formed in layer B are far smaller than those in layer C, due to the lower charge carrier density of layer B.

[0215] FIG. 9B therefore shows that electrochemical etching has occurred through the non-intentionally-doped surface layer, as well as the NID layers of AlGaN and AIN. It is therefore clear that the method of the present invention is capable of porosifying multiple sub-surface layers, in a variety of positions in a multi-layered semiconductor structure, and of producing differing porosities based on the initial charge carrier densities of the III-nitride materials.